Testing apparatus for data storage devices
11698408 · 2023-07-11
Assignee
Inventors
Cpc classification
G01R31/2868
PHYSICS
G01R31/2844
PHYSICS
G01R31/2884
PHYSICS
International classification
Abstract
A testing apparatus for Data Storage Devices (DSDs) includes a chassis and at least one interface module configured to be removably inserted into the chassis and house a plurality of interface boards. Each interface board includes a DSD connector for connecting a DSD to the interface board and a backplane connector for connecting to a backplane for communicating with a respective computing unit. In one aspect, the at least one interface module includes a housing and a plurality of openings in a side of the housing with each opening configured to receive a respective interface board. A plurality of guide member pairs is positioned to guide respective interface boards when inserted into respective openings such that the backplane connector is located at a respective predetermined location for connecting to the backplane. In another aspect, the interface boards are removable from the interface module.
Claims
1. A testing apparatus for testing Data Storage Devices (DSDs), the testing apparatus comprising: a chassis; and at least one interface module configured to be removably inserted into the chassis and to house a plurality of interface boards, wherein each interface board of the plurality of interface boards includes a DSD connector for connecting a DSD to the interface board and a backplane connector for directly connecting to a backplane for communicating with a respective computing unit.
2. The testing apparatus of claim 1, wherein the at least one interface module includes a plurality of openings for receiving the plurality of interface boards, and wherein the plurality of interface boards is removable from the at least one interface module such that each interface board of the plurality of interface boards is configured to be inserted into any one of the plurality of openings of the at least one interface module.
3. The testing apparatus of claim 1, wherein the at least one interface module includes a plurality of openings for receiving the plurality of interface boards and respective DSDs, and wherein the plurality of openings includes openings of different sizes for receiving DSDs having different form factors.
4. The testing apparatus of claim 1, wherein the backplane connectors of the plurality of interface boards are of the same type and at least two of the DSD connectors of the plurality of interface boards are of different types from each other.
5. The testing apparatus of claim 1, further comprising a computing module configured to be removably inserted into the chassis and to house a plurality of computing units, wherein each computing unit of the plurality of computing units is configured to connect to the backplane.
6. The testing apparatus of claim 1, wherein the at least one interface module includes a plurality of first openings in a first side, each opening of the plurality of openings configured to receive a respective interface board, and wherein the plurality of openings is arranged in at least one horizontal row with respect to a surface upon which the testing apparatus rests.
7. The testing apparatus of claim 1, wherein the at least one interface module includes: a plurality of first openings in a first side, each opening of the plurality of openings configured to receive a respective interface board; and a plurality of guide member pairs positioned to guide respective interface boards when received in respective first openings of the plurality of first openings such that a backplane connector of the interface board is located at a predetermined location with respect to the chassis for connecting to a backplane.
8. The testing apparatus of claim 1, further comprising a thermal isolation wall separating a first space within the chassis from the backplane, the first space configured to receive the at least one interface module.
9. An interface module of a testing apparatus for testing Data Storage Devices (DSDs), the interface module comprising: a housing; a plurality of openings in a first side of the housing, each opening of the plurality of openings configured to receive a respective interface board; and a plurality of guide member pairs positioned to guide respective interface boards when inserted into respective openings of the plurality of openings such that a backplane connector of each respective interface board is located at a respective predetermined location with respect to the housing for directly connecting to a backplane of the testing apparatus.
10. The interface module of claim 9, wherein the respective interface boards are removable from the plurality of openings such that each of the respective interface boards is configured to be inserted into any one of the plurality of openings.
11. The interface module of claim 9, wherein the plurality of openings are further configured to receive respective DSDs, and wherein the plurality of openings includes openings of different sizes for receiving DSDs having different form factors.
12. The interface module of claim 9, wherein the respective interface boards further include a DSD connector for communicating with a DSD, and wherein the backplane connectors of the respective interface boards are of the same type and at least two of the DSD connectors of the respective interface boards are of different types from each other.
13. The interface module of claim 9, wherein the plurality of openings is arranged in at least one horizontal row with respect to a surface upon which the testing apparatus rests.
14. The interface module of claim 9, wherein the at least one interface module is configured to be removably inserted into a chassis of the testing apparatus.
15. The interface module of claim 9, wherein the testing apparatus includes a thermal isolation wall separating the interface module from the backplane.
16. A testing apparatus for testing Data Storage Devices (DSDs), the testing apparatus comprising: a chassis; means for housing a plurality of removable interface boards in the chassis, wherein each removable interface board of the plurality of removable interface boards is configured to be removably inserted into the means for housing the plurality of removable interface boards, wherein each removable interface board of the plurality of removable interface boards includes a DSD connector for connecting to a DSD and a backplane connector for connecting to a backplane for communicating with a respective computing unit; and a thermal isolation wall separating a first space within the chassis from the backplane, the first space configured to receive the means for housing the plurality of removable interface boards.
17. The testing apparatus of claim 16, wherein the means for housing the plurality of removable interface boards is configured to be removably inserted into the chassis.
18. The testing apparatus of claim 16, wherein the means for housing the plurality of removable interface boards is configured to guide respective removable interface boards such that when the removable interface board is inserted into the means for housing the plurality of removable interface boards, the backplane connector of each respective removable interface board is located at a respective predetermined location with respect to the chassis for connecting to the backplane.
19. The testing apparatus of claim 16, further comprising means for removably inserting a plurality of computing units into the chassis, housing a plurality of computing units, wherein each computing unit of the plurality of computing units is configured to connect to the backplane.
20. The testing apparatus of claim 16, wherein the backplane connector of each removable interface board of the plurality of removable interface boards is configured to directly connect to the backplane.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The features and advantages of the embodiments of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the disclosure and not to limit the scope of what is claimed.
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DETAILED DESCRIPTION
(11) In the following detailed description, numerous specific details are set forth to provide a full understanding of the present disclosure. It will be apparent, however, to one of ordinary skill in the art that the various embodiments disclosed may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the various embodiments.
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(13) As shown in
(14) In the example of
(15) As will be appreciated by those of ordinary skill in the art with reference to the present disclosure, other implementations of testing apparatus 100 can include a different arrangement or number of components than shown in the example of
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(17) Those of ordinary skill in the art will appreciate that other implementations may include a different arrangement for the interior of testing apparatus 100. For example, other implementations may include a different number of interface modules or a different number of DSDs per interface module than shown in
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(19) Each opening also corresponds to a pair of guide members, such as guide members 118.sub.2A and 118.sub.2B, positioned to guide an interface board inserted through the opening so that a backplane connector (e.g., backplane connectors 123 in
(20) Handles 114.sub.1 and 114.sub.2 can facilitate insertion and removal of interface module 110.sub.1 into and from the testing apparatus. In this regard, the first space or chamber of the testing apparatus can include shelves or slats for receiving interface module 110.sub.1 and holding it in place inside chamber 140. The interface modules 110 may also be interchangeable among different testing apparatuses, such as testing apparatus 100. In the implementation of
(21) Those of ordinary skill in the art will appreciate that other implementations of interface module 110.sub.1 may differ. For example, interface module 110.sub.1 may include a mix of different sized openings for receiving DSDs with different form factors, differently sized openings on the rear of interface module 110.sub.1, or no openings on the sides of interface module 110.sub.1.
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(23) As with interface module 110.sub.1 discussed above, the interface boards and DSDs shown in
(24) In the example of
(25) As discussed in more detail below, interface module 110.sub.2 may also be capable of accommodating a variety of different form factors with the replacement of the interface boards in housing 126.sub.2. In some implementations, the front openings may be different sizes to accommodate different form factors or may all be the same size as shown in
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(27) In addition to having different physical dimensions, each DSD in
(28) Backplane connectors 123.sub.1, 123.sub.2, 123.sub.3, 123.sub.4, and 123.sub.5 of interface boards 122.sub.1, 122.sub.2, 122.sub.3, 122.sub.4, and 122.sub.5, respectively, utilize the same Peripheral Component Interconnect express (PCIe) connectors for a uniform backplane connection. This standardization on one backplane connector type, such as PCIe, can facilitate the interchangeability of the different types of interface boards into different slots or bays of the interface modules. In addition to having different DSD connector types, the interface boards 122 in
(29) Each interface board 122 in
(30) Those of ordinary skill in the art will appreciate that other locking mechanisms or interface boards may be used in other implementations. For example, other interface boards may have a different shape or DSD support to accommodate a different form factor.
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(33) With respect to interface module 110.sub.1, DSD 20.sub.3 is secured into interface module 110.sub.1 with DSD support 127.sub.1 and locking tabs 124.sub.1. DSD 20.sub.4 is secured into interface module 110.sub.1 with DSD support 127.sub.1 and locking tabs 124.sub.1, and DSD 20.sub.4 is secured into interface module 110.sub.1 with DSD support 127.sub.2 and locking tabs 124.sub.2. As shown in
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(35) In the example of
(36) In this regard, each of removable computing modules 128.sub.1, 128.sub.2, 128.sub.5 and 128.sub.6 shown in
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(38) In the example of
(39) Backplane 136 allows for a wireless connection to the interface boards in the testing chamber without compromising the thermal isolation provided by thermal isolation wall 134. In contrast, conventional temperature testing apparatuses for DSDs typically use wires with grommets surrounding the wires for communication with DSDs in a temperature-controlled testing chamber. However, bus standards such as PCIe may encounter noise-induced errors due to such wire runs. The arrangement of backplane 136 on thermal isolation wall 134 can provide for direct connections with interface boards, which are in turn directly connected to the DSDs to avoid wire runs while still providing thermal isolation of the testing chamber.
(40) As discussed above, the foregoing arrangements of removable interface modules and removable interface boards can facilitate the testing of DSDs having different form factors using the same testing apparatus. This interchangeability can avoid complicated teardowns of testing equipment to accommodate different form factors. In addition, the interface boards can allow for a wire-free connection to the backplane and computing units, while still thermally isolating the DSDs from the computing units and backplane in a different compartment of the testing apparatus for better temperature control.
Other Embodiments
(41) Those of ordinary skill in the art will appreciate that the various illustrative logical blocks, modules, and processes described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. Furthermore, the foregoing processes can be embodied on a computer readable medium which causes processor or controller circuitry to perform or execute certain functions.
(42) To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, and modules have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
(43) The various illustrative logical blocks, units, modules, processor circuitry, and controller circuitry described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a GPU, a Digital Signal Processor (DSP), an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. Processor or controller circuitry may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, an SoC, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
(44) The activities of a method or process described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by processor or controller circuitry, or in a combination of the two. The steps of the method or algorithm may also be performed in an alternate order from those provided in the examples. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable media, an optical media, or any other form of storage medium known in the art. An exemplary storage medium is coupled to processor or controller circuitry such that the processor or controller circuitry can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to processor or controller circuitry. The processor or controller circuitry and the storage medium may reside in an ASIC or an SoC.
(45) The foregoing description of the disclosed example embodiments is provided to enable any person of ordinary skill in the art to make or use the embodiments in the present disclosure. Various modifications to these examples will be readily apparent to those of ordinary skill in the art, and the principles disclosed herein may be applied to other examples without departing from the spirit or scope of the present disclosure. The described embodiments are to be considered in all respects only as illustrative and not restrictive. In addition, the use of language in the form of “at least one of A and B” in the following claims should be understood to mean “only A, only B, or both A and B.”