Compensation of an arc curvature generated in a wafer

Abstract

This method comprises the steps of: a) forming a set of first trenches on the first surface of the wafer; b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches; c) filling the first trenches with a first material having a CTE .sub.1; d) filling the second trenches with a second material having a CTE .sub.2, and verifying .sub.2>.sub.0 or .sub.2<.sub.0 depending on whether the first material verifies .sub.1>.sub.0 or .sub.1<.sub.0.

Claims

1. Method for performing compensation of a bow generated in a wafer made from a material, the wafer comprising opposite first and second surfaces, the material of the wafer having a coefficient of thermal expansion noted .sub.0; the method comprising the steps of: a) forming a set of first trenches on the first surface of the wafer, the first surface being designed to comprise electronic components; b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches; c) filling the first trenches with a first material having a coefficient of thermal expansion .sub.1; d) filling the second trenches with a second material having a coefficient of thermal expansion .sub.2, and verifying .sub.2>.sub.0 or .sub.2<.sub.0 depending on whether the first material verifies .sub.1>.sub.0 or .sub.1<.sub.0, wherein step a) is executed in such a way that first trenches of the set of first trenches define a cutting path of the wafer and step b) is executed in such a way that the set of second trenches are totally facing said first trenches of the set of first trenches.

2. Method according to claim 1, wherein the first and second materials respectively occupy a first volume V.sub.1 and a second volume V.sub.2 inside the first and second trenches on completion of steps c) and d); and step d) is executed in such a way that $\begin{array}{cc}{V}_2=V_1\frac{.Math.{}_0-{}_1.Math.}{.Math.{}_0-{}_2.Math.}.& \end{array}$

3. Method according to claim 1, wherein the first and second trenches respectively present a first form factor .sub.1 and a second form factor .sub.2 in steps a) and b), defined as the ratio between the width and depth of the corresponding trenches; and step b) is executed in such a way that .sub.2=.sub.120%.

4. Method according to claim 3, wherein step b) is executed in such a way that .sub.2=.sub.115%, or .sub.2=.sub.110%.

5. Method according to claim 1, comprising a step a.sub.1) consisting in coating the first trenches with a dielectric layer before step c), the dielectric layer preferentially being an oxide layer.

6. Method according to claim 1, comprising a step b.sub.1) consisting in coating the second trenches with a dielectric layer before step d), the dielectric layer preferentially being an oxide layer.

7. Method according to claim 6, wherein steps a.sub.1) and b.sub.1) are concomitant.

8. Method according to claim 1, wherein step d) is executed in such a way that the second material is identical to the first material, steps c) and d) preferably being concomitant.

9. Method according to claim 1, comprising: a step c.sub.1) consisting in planarizing the first material so as to be flush with the first surface after step c); and preferably a step d.sub.1) consisting in planarizing the second material so as to be flush with the second surface after step d).

10. Method according to claim 1, wherein the first and second materials are selected from the group comprising polycrystalline silicon, a polyimide, a polyepoxide, an acrylic, an oxide, a nitride, and a glass.

11. Method according to claim 1, wherein the material of the wafer is selected from the group comprising a semiconductor material, a ceramic, a glass, and sapphire; the semiconductor material preferably being silicon-based.

12. Structure for performing compensation of a bow, comprising: a wafer made from a material, comprising opposite first and second surfaces, the material of the wafer having a coefficient of thermal expansion noted .sub.0; a set of first trenches formed on the first surface and filled with a first material having a coefficient of thermal expansion .sub.1; a set of second trenches formed on the second surface, at least partially facing the first trenches and filled with a second material having a coefficient of thermal expansion .sub.2, and verifying .sub.2>.sub.0 or .sub.2<.sub.0 depending on whether the first material verifies .sub.1>.sub.0 or .sub.1<.sub.0 , wherein first trenches of the set of first trenches define a cutting path of the wafer and the set of second trenches are totally facing said first trenches of the set of first trenches.

13. Structure according to claim 12, wherein the first and second materials respectively occupy a first volume V.sub.1 and a second volume V.sub.2 inside the first and second trenches and verifying $\begin{array}{cc}{V}_2=V_1\frac{.Math.{}_0-{}_1.Math.}{.Math.{}_0-{}_2.Math.}.& \end{array}$

14. Structure according to claim 12, wherein the first and second trenches respectively present a first form factor .sub.1 and a second form factor .sub.2, defined as the ratio between the width and depth of the corresponding trenches; and verifying .sub.2=.sub.120%, preferably .sub.2=.sub.115%, more preferentially .sub.2=.sub.110%.

15. Structure according to claim 12, wherein the first trenches are coated with a dielectric layer inserted between the material of the wafer and the first material; and the second trenches are preferably coated with a dielectric layer inserted between the material of the wafer and the second material.

16. Structure according to claim 12, wherein the first material is flush with the first surface; and preferably the second material is flush with the second surface.

17. Method according to claim 1, wherein the set of first trenches comprises primary first trenches and secondary first trenches, the primary first trenches being deeper than secondary first trenches and wherein the primary first trenches define the cutting path and the secondary first trenches are arranged to electrically insulate electronic components on first surface of wafer.

18. Structure according to claim 12, wherein the set of first trenches comprises primary first trenches and secondary first trenches, the primary first trenches being deeper than secondary first trenches and wherein the primary first trenches define the cutting path and the secondary first trenches are arranged to electrically insulate electronic components on first surface of wafer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages will become more clearly apparent from the following description of different embodiments of the invention, given for non-restrictive example purposes, with reference to the appended drawings, in which:

(2) FIG. 1 (already described) is a schematic cross-sectional view of a wafer sustaining a bow;

(3) FIG. 2 (already described) is a schematic cross-sectional view of a wafer sustaining a warp;

(4) FIGS. 3 to 5 are schematic cross-sectional views illustrating steps of a method according to the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(5) For the different embodiments, the technical features described hereafter are to be considered either alone or in any technically possible combination; the same reference numerals are used for parts that are identical or perform the same function, for the sake of simplification of the description.

(6) Definitions

(7) What is meant by wafer is: a sliced part of a semiconductor material ingot, conventionally a disc, used as base material to form components, or more generally a preferably self-supported substrate of a material (e.g. a ceramic, a glass, sapphire).

(8) What is meant by semiconductor is that the material presents an electric conductivity at 300 K comprised between 10.sup.8 S/cm and 10.sup.3 S/cm.

(9) What is meant by dielectric is that the material presents an electric conductivity at 300 K of less than 10.sup.8 S/cm.

(10) What is meant by longitudinal is a direction perpendicular to the normal to the first and second surfaces of the wafer.

(11) The method illustrated in FIGS. 1 to 3 is a method for performing compensation of bow generated in a wafer 1 made from a material, wafer 1 comprising opposite first and second surfaces 10, 11, the material of wafer 1 having a coefficient of thermal expansion, called CTE and noted .sub.0; the method comprising the steps of;

(12) a) forming a set of first trenches 100a, 100b on the first surface 10 of wafer 1;

(13) b) forming a set of second trenches 110 on the second surface 11 of wafer 1, at least partially facing first trenches 100a, 100b;

(14) c) filling first trenches 100a, 100b with a first material M.sub.1 having a CTE .sub.1;

(15) d) filling second trenches 110 with a second material M.sub.2 having a CTE .sub.2, and verifying .sub.2>.sub.0 or .sub.2<.sub.0 depending on whether first material M.sub.1 verifies .sub.1>.sub.0 or .sub.1<.sub.0.

(16) Wafer

(17) The material of wafer 1 is preferentially selected from the group comprising a semiconductor material, a ceramic, a glass, or sapphire. The semiconductor material of wafer 1 is preferentially silicon-based. For example purposes, .sub.0 (Si)=2.510.sup.6 K.sup.1 at 300 K. The silicon is advantageously doped so that wafer 1 presents a resistivity of less than 1 ohm.cm, preferentially less than 10.sup.2 ohm.cm.

(18) First trenches

(19) First trenches 100a, 100b preferentially comprise primary first trenches 100a and secondary first trenches 100b. Step a) is advantageously executed in such a way that primary first trenches 100a define a cutting path of wafer 1. Secondary first trenches 100b are advantageously arranged to electrically insulate electronic components 4 from first surface 10 of wafer 1. Primary first trenches 100a are deeper than secondary first trenches 100b. As illustrated in FIG. 3, first trenches 100a, 100b are formed during step a) preferentially by previously depositing a hard mask 2 and a photoresist 3 on first surface 10 of wafer 1. Then first trenches 100a, 100b are formed during step a) by photolithography and etching steps.

(20) First material M.sub.1 occupies a first volume V.sub.1 inside first trenches 100a, 100b on completion of step c), The method advantageously comprises a step c.sub.1) consisting in planarizing first material M.sub.1 so as to be flush with first surface 10 after step c). Step c.sub.1) is preferentially performed by chemical mechanical polishing.

(21) First material M.sub.1 is advantageously selected from the group comprising polycrystalline silicon, a polyimide, a polyepoxide, an acrylic, an oxide, a nitride, and a glass.

(22) First trenches 100a, 100b present a first form factor .sub.1 in step a). .sub.1 is defined as the ratio between the width I.sub.1 and depth H.sub.1 of the corresponding first trenches 100a, 100b.

(23) The method advantageously comprises a step a.sub.1) consisting in coating first trenches 100a, 100b with a dielectric layer 101 before step c). Dielectric layer 101 is preferentially an oxide layer, such as SiO.sub.2 when the semiconductor material of wafer 1 is Si-based. The oxide layer is preferentially a thermal oxide. First material M.sub.1 can be identical to dielectric layer 101. For example, a (SiO.sub.2)=0.610.sup.6 K.sup.1 at 300 K. However, for certain applications, first trenches 100a, 100b present a depth H.sub.1 comprised between 50 m and 100 m; filling of the latter with a thermal oxide would result in a very long operation time and in a low mechanical strength with temperature. It may therefore be preferable to use a different first material M.sub.1 from SiO.sub.2, such as polycrystalline silicon for certain applications.

(24) Second trenches

(25) Second trenches 110 are formed during step b) preferentially by previously depositing a hard mask 2 and a photoresist 3 on second surface 11 of wafer 1. Then second trenches 110 are formed in step b) by photolithography and etching steps.

(26) Step b) is preferentially executed in such a way that at least one second trench 110 of the set of second trenches 110 is totally facing at least one first trench 100a, 100b. Step b) is advantageously executed in such a way that second trenches 110 are at least partially, preferably totally, facing primary first trenches 100a, as illustrated in FIG. 4, Step b) can also be executed in such a way that second trenches 110 are at least partially, preferably totally, facing primary first trenches 100a and secondary first trenches 100b. Implementation of steps a) and b) is particularly simplified when second trenches 110 are facing primary first trenches 100a, or even primary first trenches 100a and secondary first trenches 100b, in so far as it is possible to use the same mask alignment for their formation. Wafer 1 presents a longitudinal median plane. Second trenches 110 and primary first trenches 100a are advantageously symmetrical with respect to the longitudinal median plane. Second trenches 110 and primary first trenches 100a and secondary first trenches 100b are advantageously symmetrical relatively to the longitudinal median plane.

(27) Second material M.sub.2 occupies a second volume V.sub.2 inside second trenches 110 on completion of step d). The method advantageously comprises a step d.sub.1) consisting in planarizing second material M.sub.2 so as to be flush with second surface 11 after step d), Step d.sub.1) is preferentially performed by chemical mechanical polishing.

(28) Second material M.sub.2 is advantageously selected from the group comprising polycrystalline silicon, a polyimide, a polyepoxide, an acrylic, an oxide, a nitride, and a glass. Second material M.sub.2 is advantageously identical to first material M.sub.1 so that steps c) and d) can be concomitant.

(29) Step d) is advantageously executed in such a way that

(30) $\begin{array}{cc}{V}_2=V_1\frac{.Math.{}_0-{}_1.Math.}{.Math.{}_0-{}_2.Math.}.& \end{array}$
Calculation can be performed using Stoney's formula.

(31) Second trenches 110 present a first form factor .sub.2 in steps b). .sub.2 is defined as the ratio between the width I.sub.2 and the depth H.sub.2 of the corresponding second trenches 110. Step b) is advantageously executed in such a way that .sub.2=.sub.120%, preferably .sub.2=.sub.115%, more preferentially .sub.2=.sub.110%.

(32) The method advantageously comprises a step b.sub.1) consisting in coating second trenches 110 with a dielectric layer 111 before step d). Dielectric layer 111 is preferentially an oxide layer such as SiO.sub.2 when the semiconductor material of wafer 1 is Si-based. The oxide layer is preferentially a thermal oxide. When dielectric layers 101, 111 are thermal oxides, steps a.sub.1) and b.sub.1) are advantageously concomitant. Second material M.sub.2 can be identical to dielectric layer 111. For example purposes, (SiO.sub.2)=0.610.sup.6 K.sup.1 at 300 K. However, for certain applications, second trenches 110 present a depth H.sub.2 comprised between 50 m and 100 m; filling of the latter with a thermal oxide would result in a very long operation time and a low mechanical strength with temperature. It may therefore be preferable to use a different second material M.sub.2 from SiO.sub.2, such as polycrystalline silicon for certain applications.

(33) Simulations enable it to be observed that the parameters (.sub.2, V.sub.2, .sub.2) defined according to the invention optimize compensation of the bow.

(34) Application Example

(35) On completion of the method according to the invention, it is possible to form components 4, such as light-emitting diodes, on first surface 10 of wafer 1. The light-emitting diodes can be formed by epitaxy of GaN, at a temperature of 1050 C. The light-emitting diodes are then preferentially coated with a protective substrate (or support substrate called handle) assembled on first surface 10 of wafer 1 by bonding. The handle can be temporary or permanent. This results in temporary or permanent bonding. The protective substrate is made from a material preferentially selected from the group comprising a glass, silicon, quartz, and sapphire. More generally, any rigid substrate, transparent in the emission spectrum of the light-emitting diodes, can be suitable for use as protective substrate. Then second surface 11 of wafer 1 is thinned until first trenches 110 are reached. Thinned second surface 11 will then be metallized for the contact connections.

(36) Other applications can naturally be envisaged such as: microfluidics applications when the material of wafer 1 is a glass, hybrid microelectronics applications when the material of wafer 1 is a ceramic.