Radio frequency (RF) transceiver and operating method thereof

Abstract

A radio frequency (RF) transceiver includes a first oscillator configured to generate a first oscillation frequency associated with an RF signal, a second oscillator configured to generate a second oscillation frequency associated with a clock frequency, a counter configured to generate a counter output signal using the first oscillation frequency and the second oscillation frequency, and a comparer configured to generate a digital output signal associated with the RF signal by comparing an output value of the counter output signal to a reference value.

Claims

1. A radio frequency (RF) transceiver comprising: a first oscillator configured to generate a first oscillation frequency associated with an RF signal; a second oscillator configured to generate a second oscillation frequency associated with a clock frequency; a quenching wave generator configured to generate a quenching signal to control a negative-R generator of the first oscillator using the second oscillation frequency; and a comparer configured to generate a digital output signal associated with the RF signal based on consideration of the first oscillation frequency, the second oscillation frequency, and a reference.

2. The RF transceiver of claim 1, further comprising: a counter configured to generate a counter output signal based on a result of comparing the first oscillation frequency and the second oscillation frequency, wherein the counter output signal is associated with a ratio of the first oscillation frequency to the second oscillation frequency.

3. The RF transceiver of claim 1, wherein the first oscillator comprises: an antenna configured to receive the RF signal; the negative-R generator being electrically connected to the antenna; and a capacitor bank connected in parallel with the antenna and the negative-R generator.

4. The RF transceiver of claim 1, further comprising: an auto gain calibration controller configured to disable the quenching wave generator and the negative-R generator in response to an input power of the RF signal being greater than or equal to a threshold value.

5. The RF transceiver of claim 1, further comprising: an alternating current (AC) coupling capacitor disposed between the first oscillator and the counter.

6. The RF transceiver of claim 1, further comprising: a data generator configured to generate transmission data; and a modulator configured to modulate the transmission data received from the data generator using the first oscillator.

7. The RF transceiver of claim 1, further comprising: an auto amplitude calibration controller connected to the first oscillator and configured to correct an amplitude of the first oscillator.

8. The RF transceiver of claim 1, further comprising: an auto frequency calibration controller electrically connected to the first oscillator and configured to correct a frequency of the first oscillator.

9. The RF transceiver of claim 1, wherein the first oscillator and the second oscillator are disposed in a single RF transceiver integrated circuit (IC).

10. A radio frequency (RF) transceiver comprising: a first oscillator configured to generate a first oscillation frequency associated with an RF signal; a second oscillator configured to generate a second oscillation frequency associated with a clock frequency; a quenching wave generator configured to generate a quenching signal that controls a negative-R generator of the first oscillator using the second oscillation frequency; an envelope detector configured to detect an envelope signal from the first oscillation frequency; and a modulator configured to modulate transmission data.

11. The RF transceiver of claim 10, further comprising: a counter configured to generate a counter output signal using the first oscillation frequency, the second oscillation frequency, and the envelope signal; and a comparer configured to generate a digital output signal associated with the RF signal by comparing the counter output signal to a reference value, wherein the counter output signal is associated with a ratio of the first oscillation frequency to the second oscillation frequency.

12. The RF transceiver of claim 10, wherein the envelope signal is applied to an enable signal of the counter.

13. The RF transceiver of claim 10, wherein the first oscillator comprises: an antenna configured to receive the RF signal; the negative-R generator being electrically connected to the antenna; and a capacitor bank connected in parallel with the antenna and the negative-R generator.

14. The RF transceiver of claim 10, further comprising: an auto gain calibration controller configured to disable the quenching wave generator and the negative-R generator in response to an input power of the RF signal being greater than or equal to a threshold value.

15. The RF transceiver of claim 10, further comprising: an alternating current (AC) coupling capacitor disposed between the first oscillator and the counter.

16. A radio frequency (RF) transceiver comprising: a first oscillator configured to generate a first oscillation frequency associated with an RF signal; a second oscillator configured to generate a second oscillation frequency associated with a clock frequency; a quenching wave generator configured to generate a quenching signal that controls the first oscillator using the second oscillation frequency; and an auto gain calibration controller configured to selectively enable or disable the quenching wave generator based on an input power of the RF signal, wherein the auto gain calibration controller is further configured to disable the quenching wave generator in response to the input power of the RF signal being determined to be greater than or equal to a threshold value.

17. The RF transceiver of claim 16, wherein the auto gain calibration controller is further configured to enable the quenching wave generator in response to the input power of the RF signal being determined to be less than the threshold value.

18. The RF transceiver of claim 16, further comprising: a counter configured to generate a counter output signal using the first oscillation frequency and the second oscillation frequency; and a comparer configured to generate a digital output signal associated with the RF signal by comparing an output value of the counter output signal to a reference value.

19. A radio frequency (RF) transceiver comprising: a first oscillator configured to generate a first signal of a first oscillation frequency associated with an RF signal, by using an antenna for receiving the RF signal as an inductor of the first oscillator; a second oscillator configured to generate a second signal of a second oscillation frequency associated with an internal clock frequency; a counter configured to generate a counter output signal using the first signal and the second signal, wherein the first signal is used as a clock of the counter and the second signal resets the counter; and a comparer configured to generate a digital output signal associated with the RF signal by comparing the counter output signal to a reference signal.

20. The RF transceiver of claim 19, wherein a first timing at which the first signal is generated when the RF signal corresponds to 1 is faster than a second timing at which the first signal is generated when the RF signal corresponds to 0.

21. The RF transceiver of claim 19, wherein the antenna is directly connected to the first oscillator.

22. The RF transceiver of claim 19, further comprising: a modulator configured to modulate a transmitting signal using the first oscillator.

23. The RF transceiver of claim 22, wherein the modulator comprising at least one of an OOK modulator and a FSK modulator.

24. The RF transceiver of claim 22, wherein the modulator adjusts the first oscillation frequency using Ccode[n:0].

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram illustrating a portion of a radio frequency (RF) transceiver, according to an embodiment.

(2) FIG. 2 is a block diagram illustrating a portion of a radio frequency (RF) transceiver, according to another embodiment.

(3) FIG. 3 is a timing diagram illustrating a signal of a radio frequency (RF) transceiver, according to an embodiment.

(4) FIG. 4 is a block diagram illustrating a portion of a radio frequency (RF) transceiver, according to another embodiment.

(5) FIG. 5 is a timing diagram illustrating a signal of a radio frequency (RF) signal, according to another embodiment.

(6) FIG. 6 is a block diagram illustrating a portion of a radio frequency (RF) transceiver, according to another embodiment.

(7) FIG. 7 is a timing diagram illustrating a signal of a radio frequency (RF) transceiver, according to another embodiment.

(8) FIG. 8 is a block diagram illustrating a portion of a radio frequency (RF) transceiver, according to another embodiment.

(9) FIG. 9 is a timing diagram illustrating a signal of a radio frequency (RF) transceiver, according to another embodiment.

(10) Throughout the drawings and the detailed description, unless otherwise described or provided, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

(11) The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness.

(12) The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.

(13) The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms comprises, includes, and has specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.

(14) The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application.

(15) When describing examples with reference to the accompanying drawings, like reference numerals refer to like constituent elements and a repeated description related thereto will be omitted. When it is determined detailed description related to a related configuration they may make the purpose of the examples unnecessarily ambiguous in describing the examples, the detailed description will be omitted here.

(16) FIG. 1 is a block diagram illustrating a portion of a radio frequency (RF) transceiver 100, according to an embodiment. The RF transceiver 100 includes an integrated circuit (IC) chip 110, a first external component 120, and a second external component 130.

(17) As illustrated in FIG. 1, an input end of a receiver and an output end of a transmitter are included separately in the IC chip 110. Thus, it may be desirable that the first external component 120 includes a matching component (matching circuit (L/C) for the output end of the transmitter and a matching component (matching circuit (L/C) for a transmitting end of the input end of the receiver separately. In addition, the first external component 120 includes a matching component (matching circuit (L/C) for an antenna and one or more switches. The second external component 130 includes a crystal (X-Tal) oscillator for generating a reference frequency and a supply capacitor for stabilizing a power.

(18) The use of the first external component 120 and the second external component 130 may cause an increase in a size of an RF transceiver module 100 because the use of the first external component 120 and the second external component 130 may necessitate the use of a great number of matching components and a large volume X-Tal oscillator.

(19) Thus, a structure capable of receiving an RF signal using an oscillator which may be included in a chip in lieu of using a matching component and an external oscillator is disclosed below. For example, a structure of an RF transceiver, according to an embodiment, includes an LC oscillator configured to receive an RF input signal through an antenna, an RC oscillator configured to generate an internal frequency, a counter configured to sense the RF input signal by comparing a frequency of the LC oscillator to a frequency of the RC oscillator, and a comparer configured to generate a digital output signal by comparing an output value of the counter to a reference value.

(20) The structure of the RF transceiver disclosed below is used to transmit and receive through an RF port by combining the antenna, the matching component for the transmitter, and the matching component for the receiver. The antenna is used as an inductor of the LC oscillator in the chip, and the antenna is directly used to modulate a transmitting signal using the LC oscillator when transmitting is performed.

(21) The structure of the RF transceiver disclosed below has relatively low complexity, such that an amount of power consumption may be relatively small and the RF transceiver may be miniaturized. The structure of the RF transceiver is insensitive to a noise change and a temperature change because a time to digital converter (TDC) method of calculating an output value by comparing the frequency of the LC oscillator to the frequency of the RC oscillator (or a ring oscillator) is implemented in the IC chip.

(22) FIG. 2 is a block diagram illustrating a portion of a radio frequency (RF) transceiver 200, according to another an embodiment. The RF transceiver 200 includes a first oscillator 210, a second oscillator 220, a counter 250, and a comparer 270. The RF transceiver 200 further includes amplifiers 231, 232, and 233, an alternating current (AC) coupling capacitor 240, a quenching wave generator 260, an auto amplitude calibration controller 281, an auto frequency calibration controller 282, an auto gain calibration controller 283, and a temperature compensated current source 290.

(23) The first oscillator 210 generates a first oscillation frequency f.sub.osc1 associated with an RF signal V.sub.RF received from an antenna 211 using a coil of the antenna 211 as an inductor of an LC-tank. For example, the first oscillator 210 is an LC oscillator disposed in an RF transceiver integrated circuit (IC). For example, the first oscillator 210 includes the antenna 211, a capacitor bank (C-bank) 212, and a negative-R generator 213. The antenna 211 is, for example, a loop antenna. The C-bank 212 is connected in parallel with the antenna 211 and the negative-R generator 213. An output signal V.sub.osc1 of the first oscillator 210 associated with the first oscillation frequency f.sub.osc1 is input to a clock Clk of the counter 250 via the amplifiers 231 and 232, and the AC coupling capacitor 240.

(24) The second oscillator 220 generates a second oscillation frequency f.sub.osc2 corresponding to an internal clock frequency. For example, the second oscillator 220 is an RC oscillator or a ring oscillator disposed in the RF transceiver IC. An output signal V.sub.osc2 of the second oscillator 220 associated with the second oscillation frequency f.sub.osc2 is used as a reset signal Rstn of the counter 250. For example, the counter 250 is reset on a rising edge of the output signal V.sub.osc2 of the second oscillator 220.

(25) The output signal V.sub.osc2 of the second oscillator 220 is also used as a quenching signal that controls the first oscillator 210. For example, the quenching wave generator 260 generates a quenching signal that controls a current source of the first oscillator 210 using the output signal V.sub.osc2 of the second oscillator 220. The quenching signal uses the second oscillation frequency f.sub.osc2, but also controls the current source by changing a form and a duty cycle of a signal in the quenching wave generator 260. Thus, a current waveform having various forms may be applied to the LC oscillator.

(26) In an example, the negative-R generator 213 is selectively enabled or disabled based on an input power of the RF signal V.sub.RF. In response to the negative-R generator 213 being disabled, the quenching wave generator 260 is controlled such that a current is not supplied to the negative-R generator 213. For example, in response to the input power of the RF signal V.sub.RF being greater than or equal to a predetermined threshold value, the auto gain calibration controller 283 disables the negative-R generator 213 and the quenching wave generator 260 and thus, the received RF signal V.sub.RF is amplified only by the amplifiers 231 and 232, and the AC coupling capacitor 240. Conversely, in response to the input power of the RF signal V.sub.RF being less than the predetermined threshold value, the auto gain calibration controller 283 enables the negative-R generator 213 and the quenching wave generator 260 and thus, the received RF signal V.sub.RF is received through oscillation of the first oscillator 210.

(27) In an example, the auto gain calibration controller 283 selectively enables and disables the negative-R generator 213 and the quenching wave generator 260 in response to a receiving sensitivity level to be requested. For example, when a relatively high receiving sensitivity level is requested, the auto gain calibration controller 283 enables the negative-R generator 213 and the quenching wave generator 260. Conversely, when the relatively high receiving sensitivity level is not requested, the auto gain calibration controller 283 disables the negative-R generator 213 and the quenching wave generator 260.

(28) The counter 250 generates a counter output signal C.sub.OUT based on a time-to-digital converter (TDC) method using the first oscillation frequency f.sub.osc1 and the second oscillation frequency f.sub.osc2. The counter output signal C.sub.OUT is associated with a ratio of the first oscillation frequency f.sub.osc1 to the second oscillation frequency f.sub.osc2. In response to a difference between the first oscillation frequency f.sub.osc1 and the second oscillation frequency f.sub.osc2 being relatively great, a difference between a number of clocks to be counted by the counter 250 when the RF signal V.sub.RF corresponds to 1 and the number of clocks to be counted by the counter 250 when the RF signal V.sub.RF corresponds to 0 may increase.

(29) For example, when the RF signal V.sub.RF corresponds to 1, the oscillation of the first oscillator 210 may be relatively fast such that the number of the clocks to be counted by the counter 250 may be a relatively great value. Accordingly, the counter output signal C.sub.OUT may have a relatively great value. Conversely, when the RF signal V.sub.RF corresponds to 0, the oscillation of the first oscillator 210 may be relatively slow such that the number of the clocks to be counted by the counter 250 may be a relatively small value. Accordingly, the counter output signal C.sub.OUT may have a relatively small value.

(30) The comparer 270 generates a digital output signal N.sub.OUT associated with the RF signal V.sub.RF by comparing an output value of the counter output signal C.sub.OUT to a reference value N.sub.T. In response to the output value of the counter output signal C.sub.OUT being greater than or equal to the reference value N.sub.T, the digital output signal N.sub.OUT has a value of 1. In response to the output value of the counter output signal C.sub.OUT being less than the reference value N.sub.T, the digital output signal N.sub.OUT has a value of 0.

(31) For example, the RF transceiver 200 includes the auto amplitude calibration controller 281 and the auto frequency calibration controller 282 disposed in the RF transceiver IC and thereby, the first oscillator 210 may operate stably. The auto amplitude calibration controller 281 is electrically connected to the first oscillator 210, and performs a function of automatically correcting an amplitude of the first oscillator 210. The auto frequency calibration controller 282 is electrically connected to the first oscillator 210, and performs a function of automatically correcting a frequency of the first oscillator 210.

(32) All elements of the RF transceiver 200, excluding an antenna, may be disposed in the RF transceiver IC such that it is possible to use fewer external components of a relatively large volume or a relatively large size. Thus, the RF transceiver 200 may be advantageously miniaturized in comparison to related technology that uses a great number of external components. Also, the RF transceiver 200 provides the advantage that a low frequency noise and a DC offset occurring in an amplifier disposed between the first oscillator 210 and the counter 250 may be easily removed by the AC coupling capacitor 240.

(33) FIG. 3 is a timing diagram illustrating a signal of the radio frequency (RF) transceiver 200 of FIG. 2, according to an embodiment. FIG. 3 illustrates examples in which each signal is changed as time elapses during a receiving operation of the RF transceiver 200. A counter output N.sub.OUT1 (e.g., the output of the counter 250 in FIG. 2) when an RF signal V.sub.RF corresponds to 1 and a counter output N.sub.OUT0 (e.g., the output of the counter 250 in FIG. 2) when the RF signal V.sub.RF corresponds to 0 may be expressed as shown below in Equations 1 and 2.

(34) $\begin{array}{cc}{N}_{\mathrm{OUT}1}=\frac{T_{\mathrm{osc}2-2t1}}{2T_{\mathrm{osc}1}}=\frac{t2}{2T_{\mathrm{osc}1}}& \left[\mathrm{Equation}1\right]\\ N_{\mathrm{OUT}0}=\frac{T_{\mathrm{osc}2-2t^{}1}}{2T_{\mathrm{osc}1}}=\frac{t^{}2}{2T_{\mathrm{osc}1}}& \left[\mathrm{Equation2}\right]\end{array}$

(35) In Equations 1 and 2, T.sub.OSC1 is an oscillation period of a first oscillator (e.g., the first oscillator 210 in FIG. 2), and T.sub.OSC2 is an oscillation period of a second oscillator (e.g., the second oscillator 220 in FIG. 2). When a difference between the counter output N.sub.OUT1 and the counter output N.sub.OUT0 corresponds to N, the difference N may be expressed as shown below in Equation 3.

(36) $\begin{array}{cc}N=\frac{\left(D1-D2\right)f_{\mathrm{osc}1}}{2f_{\mathrm{osc}2}}& \left[\mathrm{Equation}3\right]\end{array}$

(37) In Equation 3, D1 is a ratio of the oscillation period of the second oscillator 220 to a duration time during which the first oscillator 210 oscillates when the RF signal V.sub.RF corresponds to 1, and D2 is a ratio of the oscillation period of the second oscillator 220 to the duration time during which the first oscillator 210 oscillates when the RF signal V.sub.RF corresponds to 0. D1 and D2 may be expressed as shown below in Equation 4.

(38) $\begin{array}{cc}D1=\frac{t2}{T_{\mathrm{osc}2}},D2=\frac{t^{}2}{T_{\mathrm{osc}2}}& \left[\mathrm{Equation}4\right]\end{array}$

(39) As shown in above Equations 1, 2, 3, and 4, and FIG. 3, a method that causes a difference of output values of the counter 250 may be used, because a length of the oscillation period of the first oscillator 210 when the RF signal V.sub.RF corresponds to 1 is different from a length of the oscillation period of the first oscillator 210 when the RF signal V.sub.RF corresponds to 0.

(40) When the RF signal V.sub.RF corresponds to 1, the oscillation of the first oscillator 210 may be relatively fast, such that a length t2 of the oscillation period may be relatively great. Thus, a number of clocks to be counted by the counter 250 may be a relatively great value.

(41) When the RF signal V.sub.RF corresponds to 0, the oscillation of the first oscillator 210 may be relatively slow such that a length t2 of the oscillation period may be relatively small. Thus, the number of clocks to be counted by the counter 250 may be a relatively small value.

(42) In response to the output value of the counter output signal C.sub.OUT being greater than or equal to the reference value N.sub.T, the digital output signal N.sub.OUT may have a value of 1. In response to the output value of the counter output signal C.sub.OUT being less than the reference value N.sub.T, the digital output signal N.sub.OUT may have a value of 0.

(43) FIG. 4 is a block diagram illustrating a portion of a radio frequency (RF) transceiver 400, according to another embodiment. In an example, the RF transceiver 400 includes a first oscillator 410, a second oscillator 420, a counter 450, and a comparer 470. The RF transceiver 400 also includes a data generator 491, a serial peripheral interface (SPI) 492, an on-off keying (OOK) modulator 493, and a frequency-shift keying (FSK) modulator 494. The RF transceiver 400 further includes amplifiers 431, 432, and 433, an alternating current (AC) coupling capacitor 440, a quenching wave generator 460, an auto amplitude calibration controller 481, an auto frequency calibration controller 482, and an auto gain calibration controller 483. For example, the first oscillator 410 includes an antenna 411, a capacitor bank (C-bank) 412, and a negative-R generator 413. The C-bank 412 is connected in parallel with the antenna 411 and the negative-R generator 413. The RF transceiver 400 has a configuration to be used to transmit through an RF port used for receiving an RF signal. For example, the data generator 491 generates a data signal V.sub.DATA. The generated data signal V.sub.DATA may be modulated by the OOK modulator 493 that controls an output power of an oscillator or the FSK modulator 494 that uses two oscillation frequencies f1 and f2 used to differentiate between 0 and 1.

(44) Because the antenna 411 is directly connected to the first oscillator 410, an output of the first oscillator 410 is transmitted to an outside source through the antenna 411 even when the modulated data signal V.sub.DATA is transmitted. A oscillation frequency of the first oscillator 410 may be adjusted using Ccode[n:o].

(45) Repeated descriptions will be omitted for increased clarity and conciseness because the descriptions provided with reference to FIG. 2 are also applicable to FIG. 4.

(46) FIG. 5 is a timing diagram illustrating a signal of a radio frequency (RF) signal, according to another embodiment. FIG. 5 illustrates examples in which each signal is changed as time elapses during a transmitting operation of the RF transceiver 400 of FIG. 4.

(47) Referring to FIG. 5, V.sub.RF(OOK) indicates an RF signal that is modulated based on an on-off keying (OOK) method. In the OOK method, an output of an oscillator (e.g., the first oscillator 410) indicates an on state when a data signal V.sub.DATA corresponds to 1, and the output of the first oscillator 410 indicates an off state when the data signal V.sub.DATA corresponds to 0 and thus, the RF signal is modulated.

(48) V.sub.RF(FSK) indicates an RF signal that is modulated using a first oscillation frequency f1 and a second oscillation frequency f2 based on a frequency-shift keying (FSK) method. In the FSK method, the output of the first oscillator 410 indicates the first oscillation frequency f1 when the data signal V.sub.DATA corresponds to 1 and the output of the first oscillator 410 indicates the second oscillation frequency f2 when the data signal V.sub.DATA corresponds to 0 and thus, the RF signal is modulated.

(49) FIG. 6 is a block diagram illustrating a portion of a radio frequency (RF) transceiver 600, according to another embodiment. The RF transceiver 600 includes a first oscillator 610, a second oscillator 620, a counter 650, and a comparer 670. The RF transceiver 600 also includes a filter 691 and a comparer 692. The RF transceiver 600 further includes amplifiers 631, 632, and 633, an alternating current (AC) coupling capacitor 640, a quenching wave generator 660, an auto amplitude calibration controller 681, an auto frequency calibration controller 682, and an auto gain calibration controller 683. In an example, the first oscillator 610 includes an antenna 611, a capacitor bank (C-bank) 612, and a negative-R generator 613. The C-bank 612 is connected in parallel with the antenna 611 and the negative-R generator 613.

(50) The RF transceiver 600 has a configuration for applying, to an enable signal En of the counter 650, an envelope signal V.sub.ED detected using an envelope detector configured to detect a predetermined level V.sub.REF corresponding to a reference value.

(51) Repeated descriptions will be omitted for increased clarity and conciseness because the descriptions provided with reference to FIG. 2 are also applicable to FIG. 6.

(52) FIG. 7 is a timing diagram illustrating a signal of the radio frequency (RF) transceiver 600 of FIG. 6, according to an embodiment. FIG. 7 illustrates examples in which each signal is changed as time elapses during a receiving operation of the RF transceiver 600. As illustrated in FIG. 7, an envelope signal V.sub.ED detected using an envelope detector is applied to an enable signal En of a counter.

(53) When an RF signal V.sub.RF corresponds to 1, oscillation of the first oscillator 610 may be relatively fast such that a length t2 of an oscillation period may be relatively great. Thus, a number of clocks to be counted by the counter may be a relatively great value.

(54) When the RF signal V.sub.RF corresponds to 0, the oscillation of the first oscillator 610 may be relatively slow such that a length t2 of the oscillation period may be relatively small. Thus, the number of clocks to be counted by the counter may be a relatively small value.

(55) In response to an output value of a counter output signal C.sub.OUT being greater than or equal to the reference value N.sub.T, the digital output signal N.sub.OUT may have a value of 1. In response to the output value of the counter output signal C.sub.OUT being less than the reference value N.sub.T, the digital output signal N.sub.OUT may have a value of 0.

(56) FIG. 8 is a block diagram illustrating a portion of a radio frequency (RF) transceiver 800, according to another embodiment. The RF transceiver 800 includes a first oscillator 810, a second oscillator 820, a counter 850, a comparer 870, and a temperature compensated current source 890. The temperature compensated current source 890 includes a first current source 891, a second current source 892, and a temperature compensated calibration controller 893. The RF transceiver 800 further includes amplifiers 831, 832, and 833, an alternating current (AC) coupling capacitor 840, a quenching wave generator 860, an auto amplitude calibration controller 881, an auto frequency calibration controller 882, and an auto gain calibration controller 883. In an example, the first oscillator 810 includes an antenna 811, a capacitor bank (C-bank) 812, and a negative-R generator 813. The C-bank 812 is connected in parallel with the antenna 811 and the negative-R generator 813.

(57) The first current source 891 supplies a current to the first oscillator 810, and the second current source 892 supplies the current to the second oscillator 820. In response to change rates of oscillation frequencies differing based on a temperature of each of the first oscillator 810 and the second oscillator 820, the temperature compensated calibration controller 893 controls the first current source 891 and the second current source 892 in order to compensate for the differing change rates.

(58) Because a structure of the RF transceiver to be proposed uses a method of calculating an output value of a counter output signal based on a ratio of a frequency of the first oscillator 810 to a frequency of the second oscillator 820, a final output signal N.sub.OUT may be insensitive to the change rates based on the temperature. Repeated descriptions will be omitted for increased clarity and conciseness because the descriptions provided with reference to FIG. 2 are also applicable to FIG. 8.

(59) FIG. 9 is a timing diagram illustrating a signal of the radio frequency (RF) transceiver 800, according to an embodiment. FIG. 9 illustrates a comparison between an envelope detector (ED) method according to a related art and a time to digital converter (TDC) method according to an embodiment. A difference between influences of noises when the ED method and the TDC method are used may be learned by referring to FIG. 9.

(60) When the ED method is used, a signal may be distinguished only when a difference V.sub.s between a power V.sub.0 of an output signal in response to a data signal data corresponding to 0 and a power V.sub.1 of the output signal in response to the data signal data corresponding to 1 is greater than a noise V.sub.n to be applied. It may be preferable that an output of a signal is relatively great, but the output of the signal may be limited by a supply voltage V.sub.Limited. Thus, accuracy of a receiving signal deteriorating due to noises may be unavoidable because a power of the signal is limited.

(61) However, when the TDC method is used, a value of N.sub.1 is increased such that a difference N.sub.S between a power N.sub.0 of an output signal in a case in which the data signal data corresponds to 0 and a power N.sub.1 of the output signal in a case in which the data signal data corresponds to 1 is increased. Also, because a degree of time difference is measured in a time domain, the difference Ns is increased when T.sub.osc1 is decreased. That is, an oscillation frequency f.sub.osc1 is relatively fast, and an oscillation speed of a quench wave generator is reduced. A duty cycle of a signal is increased in the quench wave generator such that a length of a period of T.sub.1 is increased.

(62) The difference Ns is increased when a slope S1 based on a settling time is increased, and the slope S1 may be increased when a high Q(LC) is used. In addition, a length of a period of N.sub.0 or a length of a period of N.sub.1 that is changed due to a noise based on a slope may be also decreased.

(63) The components in FIG. 1 (e.g., the auto amplitude calibration controller, the clock generator, the frequency synthesizer, the course/fine calibration controller, the quenching wave generator, and the coarse frequency calibration controller), the components in FIG. 2 (e.g., the first oscillator 210, the negative-R generator 213, the second oscillator 220, the counter 250, the quenching wave generator 260, the comparer 270, the auto amplitude calibration controller 281, the auto frequency calibration controller 282, the auto gain calibration controller 283, and the temperature compensated current source 290), the components in FIG. 4 (e.g., the first oscillator 410, the negative-R generator 413, the second oscillator 420, the counter 450, the quenching wave generator 460, the comparer 470, the auto amplitude calibration controller 481, the auto frequency calibration controller 482, the auto gain calibration controller 483, the data generator 491, the SPI 492, the OOK modulator 493, and the FSK modulator 494), the components of FIG. 6 (e.g., the first oscillator 610, the negative-R generator 613, the second oscillator 620, the counter 650, the quenching wave generator 660, the comparer 670, the auto amplitude calibration controller 681, the auto frequency calibration controller 682, the auto gain calibration controller 683, the filter 691 and the comparer 692), and the components of FIG. 8 (e.g., the first oscillator 810, the negative-R generator 813, the second oscillator 820, the counter 850, the quenching wave generator 860, the comparer 870, the auto amplitude calibration controller 881, the auto frequency calibration controller 882, the auto gain calibration controller 883, the current sources 891 and 892, and the temperature compensated calibration controller 893) that perform the operations described in this application are implemented by hardware components configured to perform the operations described in this application that are performed by the hardware components. Examples of hardware components that may be used to perform the operations described in this application where appropriate include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers. A processor or computer may be implemented by one or more processing elements, such as an array of logic gates, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field-programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices that is configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, a processor or computer includes, or is connected to, one or more memories storing instructions or software that are executed by the processor or computer. Hardware components implemented by a processor or computer may execute instructions or software, such as an operating system (OS) and one or more software applications that run on the OS, to perform the operations described in this application. The hardware components may also access, manipulate, process, create, and store data in response to execution of the instructions or software. For simplicity, the singular term processor or computer may be used in the description of the examples described in this application, but in other examples multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller, may implement a single hardware component, or two or more hardware components. A hardware component may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single-instruction single-data (SISD) multiprocessing, single-instruction multiple-data (SIMD) multiprocessing, multiple-instruction single-data (MISD) multiprocessing, and multiple-instruction multiple-data (MIMD) multiprocessing.

(64) Instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above may be written as computer programs, code segments, instructions or any combination thereof, for individually or collectively instructing or configuring the one or more processors or computers to operate as a machine or special-purpose computer to perform the operations that are performed by the hardware components and the methods as described above. In one example, the instructions or software include machine code that is directly executed by the one or more processors or computers, such as machine code produced by a compiler. In another example, the instructions or software includes higher-level code that is executed by the one or more processors or computer using an interpreter. The instructions or software may be written using any programming language based on the block diagrams and the flow charts illustrated in the drawings and the corresponding descriptions in the specification, which disclose algorithms for performing the operations that are performed by the hardware components and the methods as described above.

(65) The instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above, and any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of a non-transitory computer-readable storage medium include read-only memory (ROM), random-access memory (RAM), flash memory, CD-ROMs, CD-Rs, CD+Rs, CD-RWs, CD+RWs, DVD-ROMs, DVD-Rs, DVD+Rs, DVD-RWs, DVD+RWs, DVD-RAMs, BD-ROMs, BD-Rs, BD-R LTHs, BD-REs, magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state disks, and any other device that is configured to store the instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers so that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed over network-coupled computer systems so that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by the one or more processors or computers.

(66) While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.