Method of signal processing using polling and related analog-to-digital converting system

Abstract

A method of signal processing for handling a digital signal outputted by an analog-to-digital converter includes determining a candidate interval corresponding to each of multiple sampling points in a sampling space of the digital signal, wherein the candidate interval is one of multiple candidate intervals, calculating numbers of sampling points corresponding to each one of the multiple candidate intervals to determine a delegate candidate interval, and calculating a delegate value of the sampling space according to a number of sampling points corresponding to the delegate candidate interval and values of the sampling points corresponding to the delegate candidate interval.

Claims

1. A method of signal processing for handling a digital signal outputted by an analog-to-digital converter, comprising: determining a candidate interval corresponding to each of multiple sampling points in a sampling space of the digital signal, wherein the candidate interval is one of multiple candidate intervals; calculating numbers of sampling points corresponding to each of the multiple candidate intervals to determine a delegate candidate interval; and calculating a delegate value of the sampling space according to a number of sampling points corresponding to the delegate candidate interval and values of the sampling points corresponding to the delegate candidate interval.

2. The method of signal processing of claim 1, wherein the number of sampling points corresponding to the delegate candidate interval is the greatest among numbers of sampling points corresponding to the multiple candidate intervals.

3. The method of signal processing of claim 1, wherein calculating the delegate value of the sampling space according to the number of sampling points corresponding to the delegate candidate interval and the values of the sampling points corresponding to the delegate candidate interval comprises: calculating an average among the values of the sampling points corresponding to the delegate candidate interval to calculate the delegate value of the sampling space.

4. An analog-to-digital converter system, comprising: an analog-to-digital converter configured to convert an analog signal into a digital signal; and a signal processor coupled to the analog-to-digital converter, and configured to perform signal processing to the digital signal to generate a delegate value, wherein the signal processing comprises: determining a candidate interval corresponding to multiple sampling points in a sampling space of the digital signal, wherein the candidate interval is one of multiple candidate intervals; calculating numbers of sampling points corresponding to each of the multiple candidate intervals to determine a delegate candidate interval; and calculating a delegate value of the sampling space according to a number of sampling points corresponding to the delegate candidate interval and values of the sampling points corresponding to the delegate candidate interval.

5. The analog-to-digital converter system of claim 4, wherein the number of sampling points corresponding to the delegate candidate interval is the greatest among numbers of sampling points corresponding to the multiple candidate intervals.

6. The analog-to-digital converter system of claim 4, wherein calculating the delegate value of the sampling space according to the number of sampling points corresponding to the delegate candidate interval and the values of the sampling points corresponding to the delegate candidate interval comprises: calculating an average among the values of the sampling points corresponding to the delegate candidate interval to calculate the delegate value of the sampling space.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates conversion curves using and not using EWMA method according to the prior art.

(2) FIG. 2 is a functional block diagram of an analog-to-digital conversion system according to an embodiment of the present invention.

(3) FIG. 3 is a flowchart of a signal processing process according to an embodiment of the present invention.

DETAILED DESCRIPTION

(4) Please refer to FIG. 2, which is a functional block diagram of an analog-to-digital conversion system 2 according to an embodiment of the present invention. The analog-to-digital conversion system may be utilized in an embedded microcontroller system, and configured to convert an analog input signal into a digital output signal. The analog-to-digital conversion system 2 includes an analog-to-digital converter (hereinafter abbreviated ADC) 20 and a signal processor 22, wherein the signal processor 22 includes a candidate list 220 and a computing unit 222.

(5) The ADC 20 is coupled to the signal processor 22, and configured to convert the analog input signal into digital values. The signal processor 22 is configured to perform signal processing to a group of sampling points (e.g., M sampling points) corresponding to a sampling interval to generate a delegate value corresponding to the sampling group to be the digital output signal. The candidate list 220 is configured to store multiple candidate intervals (e.g., N candidate intervals) and multiple groups of sampling points corresponding to the multiple candidate intervals. The computing unit 222 is coupled to the candidate list 220, and configured to determine a candidate interval corresponding to a sampling point, and count numbers of sampling points corresponding to the multiple candidate intervals, so as to perform polling and count votes of the candidate intervals. From another point of view, the signal processor 22 may perform classification according to values of the sampling points, and count numbers of the sampling points corresponding to multiple classes, so as to choose the delegate interval with the greatest number of the sampling points.

(6) The signal processor 22 may perform a signal processing process 3 to calculate a delegate value corresponding to a group of sampling points in a sampling space, as shown in FIG. 3, the signal processing process 3 includes the following steps.

(7) Step 300: Respectively determine a candidate interval corresponding to each of multiple sampling points in a sampling space of the digital signal, wherein the candidate interval is one of multiple candidate intervals.

(8) Step 301: Respectively calculate numbers of sampling points corresponding to each of the multiple candidate intervals to determine a delegate candidate interval.

(9) Step 302: Calculate a delegate value according to a number and values of the sampling points corresponding to the delegate candidate interval.

(10) For example, given that the ADC 20 may output the converted digital signal with 12-bit, it may present 4096 values. Take 100 values as a group, then the candidate list 220 may include 41 candidate intervals 099, 100199 . . . 39003999, and 40004095 (i.e., N=41). Given that a sampling size is 10 (i.e., M=10), and the ADC 20 may output a group of sampling points 4, 17, 14, 17, 5, 7, 9, 3, 1500, 15 to the signal processor 22. The computing unit 222 of the signal processor 22 may perform polling to the group of sampling points (Step 300), and calculate votes corresponding to each of the candidate intervals (Step 301). The following Table 1 illustrates polling result stored in the candidate list 220.

(11) TABLE-US-00001 TABLE 1 Candidate 0~99 1500~1599 intervals Sampling 4, 17, 14, 17, 5, 7, 9, 3, 15 1500 value Votes 9 1

(12) As can be seen from Table 1, there are 9 votes for the candidate interval 099, while there is only 1 vote for the candidate interval 15001599. Thus, it indicates that a number of sampling points corresponding to the candidate interval 099 is greater than a number of sampling points corresponding to the candidate interval 15001599, and thus a delegate candidate interval is determined to be the candidate interval 099 (Step 301). In one embodiment, when there are two candidate intervals with equal votes and also greater than votes for other candidate intervals, both the candidate intervals are the delegate candidate intervals.

(13) In this embodiment, the signal processor 22 calculates an average among the sampling points corresponding to the delegate candidate intervals 099 (Step 302) to calculate the delegate value corresponding to the candidate interval, i.e., (4+17+14+17+5+7+9+3+15)/9=91/9=10.1, which is not limited.

(14) In other words, the present invention uses polling to determine the delegate candidate interval corresponding to the most sampling points, which excludes sampling points out of the delegate candidate interval to avoid the delegate value from influences from other candidate intervals. Therefore, when the input analog signal contains a noise having a significant difference compared with the main signal, the noise may be excluded by polling or classification to avoid calculation error of the conventional average method. In mathematical theory, a time complexity for sorting n values may be expressed by a function BigO (n log n), while a time complexity for voting n values may be expressed by a function BigO (n). Therefore, the present invention may provide a shorter latency than the latency for the conventional median method.

(15) In addition, since the present invention utilizes the delegate candidate intervals with the greatest votes to calculate the delegate value (i.e., the number of sampling points corresponding to the delegate candidate interval is the greatest among numbers of sampling points corresponding to the multiple candidate intervals), once the input signal level changes, take the input signal level changes from value 0 to value 1500 in FIG. 1 for example. There are four values 0 obtained from the first to fourth sampling cycles, there are five values 1500 obtained from the fifth to ninth sampling cycles, and the signal processor 22 of the present invention may output the correct delegate value at least by the time of the ninth sampling cycle. As can be seen, compare with the conventional EWMA method reaching to the correct value 1500 until the forty-first cycle, the present invention may provide a shorter latency.

(16) Noticeably, those skilled in the art may make modifications and alterations according to practical requirements, which is not limited to the embodiments of the present invention. For example, a designer may set the number M of sampling points and weighting for the sampling space, the number N of candidate intervals and a range of the candidate interval, and duration of the sampling cycle according to practical requirements. In addition to using the average method to calculate the delegate value, the designer may use any method to calculate the delegate value; for example, randomly choosing a sampling value from the delegate candidate interval as the delegate value to speed up outputting the delegate value.

(17) To sum up, for multiple sampling points in a sampling space, the present invention uses polling to determine a delegate candidate interval including the most sampling points, and then calculate a delegate value of the sampling space according to a number and values of sampling points corresponding to the delegate candidate interval. Therefore, it may exclude sampling points not included in the delegate candidate interval, so as to avoid the delegate value from influenced by the noise and avoid lengthy latency.

(18) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.