OPTIMIZER FOR SOLAR STRING POWER GENERATION SYSTEMS AND A METHOD THEREOF
20230216310 · 2023-07-06
Assignee
Inventors
Cpc classification
H02S40/32
ELECTRICITY
G05F1/67
PHYSICS
H02J3/46
ELECTRICITY
Y02E10/56
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H02J2300/26
ELECTRICITY
International classification
G05F1/67
PHYSICS
Abstract
The present invention relates to an optimizer, for a solar string power generation system, comprising an Injection Circuit (IC), connected to at least one string, from an array of strings of solar panels, wherein the output of said IC is connected to the DC bus of the solar inverter. The IC comprises: (i) an MPPT mechanism, for finding the MPP of the connected string; (ii) a DC/DC converter, for converting part of the power of said connected string; wherein the DC/DC converter, converts only a part of the power of the string, that is connected to the IC, when the string is impaired, for compensating for the relative voltage difference between the voltage MPP, of the impaired string, and the MPP voltage of the DC bus of the solar inverter and the array of strings.
Claims
1. An optimizer for a solar string power generation system comprising: an array of strings of solar panels where at least a part of said solar panels are connected in series in said strings, and wherein said strings are connected in parallel to form said array of strings of solar panels; a DC bus, connected to said array of strings; an inverter, connected, at its input, to said DC bus, for converting a solar DC power, from said array of strings, to an AC power; at least one Injection Circuit (IC), connected at an input thereof, to at least one string of said strings comprising: an MPPT mechanism, for finding the MPP of said connected at least one string; a DC/DC converter, for converting at least a part of a power of said connected at least one string; and wherein said DC/DC converter, of said IC, converts, using a power conversion, part of the power of said connected at least one string, for compensating for a relative voltage difference between a MPP voltage, of said connected at least one string, and a voltage of said DC bus thereby compensating for a decrease in voltage, of said connected at least one string, to correspond with a voltage of said DC bus, on an expense of a current of said connected at least one string.
2. The optimizer according to claim 1, where the IC is a phase shift full bridge circuit.
3. The optimizer according to claim 2, where the phase shift full bridge circuit has bottom diodes.
4. The optimizer according to claim 2, where the phase shift full bridge circuit has bottom synchronous MOSFETS.
5. The optimizer according to claim 1, where the operation dynamic range of the input of said string optimizer is between 250V-1400V.
6. The optimizer according to claim 1, where the operation dynamic range of the output voltage of the IC of said optimizer is between 5V-250V.
7. The optimizer according to claim 1, where the compensated voltage is added under the voltage of the connected at least one string.
8. The optimizer according to claim 1, where the compensated voltage is added above the voltage of the connected at least one string.
9. The optimizer according to claim 1, where the IC is also connected, at its input, to another IC which its input is connected to at least one additional string.
10. The optimizer according to claim 1, where the IC is implemented close to the inverter.
11. A method for optimizing a solar string power generation system, the method comprising: providing an array of strings of solar panels where at least a part of said solar panels are connected in series in said strings, and wherein said strings are connected in parallel to form said array of strings of solar panels; and providing an inverter, connected by a DC bus to said array of strings, for converting a solar DC power, from said array of strings, to an AC power; providing an Injection Circuit (IC), connected at an input thereof to at least one string of said strings, wherein said IC comprises an MPPT mechanism and a DC/DC converter; and converting, using a power conversion, part of the power of said connected at least one string, for compensating for a relative voltage difference between a MPP voltage, of said connected at least one string, and a voltage of said DC bus thereby compensating for a decrease in voltage, of said connected at least one string, to correspond with a voltage of said DC bus, on an expense of a current of said connected at least one string.
12. The method according to claim 11, where the IC comprises a phase shift full bridge circuit.
13. The method according to claim 12, where the phase shift full bridge circuit has bottom diodes.
14. The optimizer according to claim 12, where the phase shift full bridge circuit has bottom synchronous MOSFETS.
15. The method according to claim 11, where the operation dynamic range of the output voltage of the IC is between 5V-250V.
16. The method according to claim 11, where the compensated voltage is added under the voltage of the connected at least one string.
17. The method according to claim 11, where the compensated voltage is added above the voltage of the connected at least one string.
18. The method according to claim 11, where the IC is also connected, at its input, to another IC which its input is connected to at least one additional string.
19. The method according to claim 11, where the IC is implemented close to the inverter.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The accompanying drawings, and specific references to their details, are herein used, by way of example only, to illustratively describe some of the embodiments of the invention.
[0027] In the drawings:
[0028]
[0029]
[0030]
[0031]
[0032]
[0033]
[0034]
[0035]
[0036]
[0037]
[0038]
DETAILED DESCRIPTION
[0039]
[0040] When part of the panels in a string are impaired, the impaired panels do not generate as much power as the other normally operating panels, and the I-V curve of the whole string changes, as depicted by curve 32 of
[0041] When at least one of the strings of the array is impaired, the average MPP of the strings is affected. In this case, the inverter, which contains the Maximum Power Point Tracking (MPPT) circuitry, adjusts the voltage (and the current) of the whole array to the average MPP of the strings. However, the average MPP 21, as depicted in graph 11 of
[0042]
[0043] Thus, the overall voltage of the impaired string 200 and its IC 100 can be similar to the voltage of the fully operating string 400, for example.
[0044] In some of the embodiments each string has its own IC, thus, when the voltage of one of the strings drops, its IC can compensate the voltage drop by enhancing the voltage of the interconnected string on the expense of the string's current.
[0045]
[0046]
[0047] For example, if the voltage of the string 200 drops, then the voltage between the lines 500 and 501 drops, and the lost voltage has to be compensated, as described above. Thus, at first, the MPPT circuit 530 may detect that the voltage of the string 200 dropped. At this stage the MOSFETs Qa and Qd are turned on where Qb and Qc are off. Thus, the current flows through Qa and Qd, delivering power to the primary coil 510 of the transformer. The primary coil 510 induces current in the secondary coils 511 which is transformed by capacitor 512 into voltage, effectively enhancing the voltage between the lines 500 and 501. The coil 513 regulates the current flow to the capacitor 512. When Qd is turned off, primary current flows through output capacitance of Qc and discharges it, thus, Load current now flows through the output rectifiers.
Time: t(0)<t<t(1)
[0048] The description below, of the Phase Shifted operation, begins with the conclusion of one power transfer cycle. This may occur when the transformer, e.g. 510-511, had been delivering power to the load 512 and two of diagonal switches of the converter are conducting. The initial current flowing in the primary is referred to as IPri(t(0)). Output voltage determined from Vout_max=Vin/N to Vout_min by changing phase shift that may increase freewheeling period on right and left legs (Active to Passive and Passive to Active legs) of the Full Bridge.
Time: t(1)<t<t(2)
[0049] The primary current flowing at time t(1) is equal to IPri(t(0)) and was being conducted through the diagonal set of transistors Qa in the upper left hand corner of the bridge and the transistor Qd in the lower right. Instantly, at time t(1) the switch Qd is turned off by the control circuitry which begins the resonant transition of the right hand leg of the converter. The primary current flowing is maintained nearly constant at IPri(t(0)) by the resonant inductance of the primary circuit, often referred to as the transformers leakage inductance. Since an external series inductance can be added to alter the effective leakage inductance value, this explanation will refer to the lumped sum of these inductors as the resonant inductance Lr, that may be located in series to coil 510. In a practical application it may be difficult to accurately control the transformers leakage inductance within an acceptable ZVS (Zero Voltage Switching) range, which necessitating an external “shim” inductor to control the accuracy. It's also possible that the transformer leakage inductance can be too low to provide the desired transition times for the application so an external inductor can be added to modify the resonant inductance.
[0050] With switch Qd turned off, the primary current continues to flow using the Qd switch output capacitance, Cd, to provide the path. This may charge the switch capacitance of Qd from essentially zero volts to the upper voltage rail, Vin+. Simultaneously, the transformer capacitance and the output capacitance of switch Qc is discharged, as its source voltage rises from the lower to the upper rail voltage. This resonant transition positions switch Qc with no drain to source voltage prior to turn-on and facilitates lossless, zero voltage switching. The primary current causing this right leg transition can be approximated by the full load primary current of IPri(t(0)). The small change due to the barely resonant circuit contribution may be negligible in comparison to the magnitude of the full load current.
[0051] During this right leg transition, the voltage across the transformers primary has decreased from VIN to zero. At some point in the transition the primary voltage drops below the reflected secondary voltage, VO x N. When this occurs the primary is no longer supplying full power to the secondary, and the output inductor voltage changes polarity. Simultaneously, energy stored in the output choke begins supplementing the decaying primary power until the primary contribution finally reaches zero. Once the right leg transition has been completed there is no voltage across the transformer primary 510. Likewise, there is no voltage across the transformers secondary winding 511 and no power transferred, assuming ideal conditions. The resonant transition not only defines the rate of change in primary and secondary voltages dV/dt, but also the rate of change in current in the output filter network, dI/dt.
Time: t(2)<t<t(3)
[0052] Once the right leg transition is complete, the primary current free wheels through transistor, i.e. switch, Qa and the body diode of switch Qc. The current would remain constant until the next transition occurs assuming that the components are ideal. Switch Qc can be turned on at this time which shunts the body diode with the FET Rds(on) switch impedance thus lowering conduction losses. Although current is flowing opposite to the normal convention (source to drain) the channel of Qc will conduct and divide the current between the switch and body diode.
Time: t(3)<t<t(4)
[0053] At time t(3) a residual current was flowing in the primary of the transformer which is slightly less than IPri(t(0)) due to losses. Switch Qc has been previously turned ON and switch Qa will now be turned OFF. The primary current will continue to flow but the path has changed to the output capacitance (Ca) of switch Qa instead of its channel. The direction of current flowing causes the drain to source voltage of switch Qa to increase and lowers its source from the upper to lower rail voltage. Just the opposite conditions have occurred to switch Qb which previously had the full input across its terminals. The resonant transition now aligns switch Qb with zero voltage across it, enabling lossless switching to occur. Primary current continues to flow and is clamped by the body diode of switch Qb, which is still OFF. This clamping into a short circuit is a necessary condition for fixed frequency, zero voltage switching. Once switch Qb is turned ON, the transformer primary is placed across the input supply rails since switch Qc is already ON and will begin to transfer power. Although zero voltage switching has already been established, turning switch Qb ON, the instant it reaches zero voltage, will cause variable frequency operation.
Time: t(4)<t<t(5)
[0054] This interval of the phase shifted cycle is basically identical to that of conventional square wave power conversion. Two diagonal switches are ON which applies the full input voltage across the transformer primary. Current rises at a rate determined by VIN and the series primary inductance, however, starts at a negative value as opposed to zero. The current will increase to a DC level equal to the output current divided by the turns ratio, JOIN. The two time variant contributors to primary current are the magnetizing current (IMAG) and the output inductor magnetizing contribution reflected to the primary. The exact switch ON time is a function of VIN, VO and N the transformer turns ratio, just as with conventional converters.
Time: >t(5)
[0055] One switching cycle is concluded at time t(5) when Qc the upper right hand corner switch is turned OFF. Current stops flowing in Qc's semiconductor channel but continues through the parasitic output capacitance, Cc of Qc. This increases the drain-to-source voltage from essentially zero to the full input supply voltage, VIN. The output capacitance of the lower switch in the right hand leg (Qd) is simultaneously discharged via the primary current. Transistor Qd is then optimally positioned for zero voltage switching with no drain-to-source voltage. The current during this interval is assumed to be constant, simplifying the analysis. In actuality, it is slightly resonant as mentioned in the left leg transition, but the amplitude may be negligible in comparison to the full load current. The power conversion interval is concluded at this point and an identical analysis occurs as for the opposite diagonal switch set which has thoroughly been described for the switch set Qa and Qd.
[0056]
[0057]
[0058]
[0059]
[0060] In one embodiment, the IC 111, of
[0061] In one embodiment, the IC 112, of
[0062]
[0063]
[0064] The solutions described above may have a better efficiency when dealing with a small percentage of impaired cells. For example, embodiments of the invention may be used for solar strings having less than 10% of impaired panels. This is partially due to the fact than in this case the string may require a very short pulse having a very large power for compensating the small voltage shortage from the impaired cells. Furthermore, since the solutions described above can work even when less than 10% of the cells are impaired, the solutions may work for systems having a dynamic range. Furthermore, since the embodiments described above compensate only the loss of voltage by using relative currency power, the proposed systems may use relatively smaller components which require less cooling.
[0065] In one embodiment, the operation dynamic range of the input of the string optimizer is between 250V-850V. In another embodiment, the operation dynamic range of the input of the string optimizer is between 400V-1400V. In another embodiment, the operation dynamic range of the input of the string optimizer is between 250V-1400V.
[0066] In one embodiment, the operation dynamic range of the delta output of the string optimizer is between 5V-250V. The term “delta output” is meant to include the output voltage of the IC, which is the DC bus voltage minus the connected string's voltage. In another embodiment the operation dynamic range of the output of the string optimizer is between 5V-150V. In another embodiment the operation dynamic range of the output of the string optimizer is between 10V-150V.
[0067] While the above description discloses many embodiments and specifications of the invention, these were described by way of illustration and should not be construed as limitations on the scope of the invention. The described invention may be carried into practice with many modifications which are within the scope of the appended claims.