Abstract
This invention relates to memory resistors, arrays of memory resistors and a method of making memory resistors. In particular, this invention relates to memory resistors having an on state and an off state, comprising: (a) a first electrode; (b) a second electrode; (c) a dielectric layer disposed between the first and second electrodes; wherein the dielectric layer comprises nanoparticles of semiconductor material, and wherein in the on state nanoparticles form at least one conductive filament encapsulated by the dielectric layer, thereby providing a conductive pathway between the first electrode and the second electrode.
Claims
1. A memory resistor having an on state and an off state, comprising: (a) a first electrode; (b) a second electrode; and (c) an inhomogeneous dielectric layer disposed between the first and second electrodes, wherein the dielectric layer comprises an inhomogeneous dielectric material having multiple domains comprising column structures; wherein the dielectric layer further comprises amorphous nanoparticles of semiconductor material, and wherein in the on state the nanoparticles form at least one conductive filament encapsulated by the dielectric layer, thereby providing a conductive pathway between the first electrode and the second electrode, wherein the at least one conductive pathway is formed at least in part along a boundary between two of said domains; wherein the memory resistor is configured to be taken from the off state to the on state when a set voltage is applied in a set process; wherein the on state is low resistance and the off state is high resistance; and wherein the memory resistor is configured to return from the on state to the off state when a reset voltage is used to produce a current in a reset process.
2. The memory resistor of claim 1, wherein the dielectric is an oxide of silicon, or wherein the dielectric is silicon nitride or silicon oxynitride.
3. The memory resistor of claim 2, wherein the dielectric is silicon dioxide (SiO.sub.2).
4. The memory resistor claim 1, wherein the nanoparticles of semiconductor material are silicon nanoparticles, or wherein the nanoparticles of semiconductor material are germanium nanoparticles.
5. The memory resistor of claim 1, wherein the first electrode is p-doped and the second electrode is n-doped, or the first electrode is n-doped and the second electrode is p-doped.
6. The memory resistor of claim 5, wherein at least one of the first electrode and the second electrode is silicon.
7. An array comprising at least one memory resistor as defined in claim 1.
8. The memory resistor of claim 1, wherein: the set voltage has a positive bias and the reset voltage has a negative bias.
Description
(1) Specific embodiments of the present invention are now described, by way of example only, with reference to the accompanying drawings in which:
(2) FIG. 1 shows a cross-sectional diagram of a memory resistor of the present invention;
(3) FIGS. 2(a) to (c) show a series of schematic diagrams illustrating the set and reset processes in a memory resistor of the present invention;
(4) FIG. 3 shows an experimental set-up including a cross-section of a memory resistor of the present application;
(5) FIGS. 4(a) and (b) show current-voltage characteristics for positive and negative bias in a memory resistor of the present invention;
(6) FIG. 4(c) shows sequential cycling between the off and on states of a memory resistor of the present invention;
(7) FIG. 4(d) shows retention times for the off and on states of a memory resistor of the present invention;
(8) FIG. 5(a) shows an STM image of the surface of a memory resistor of the present invention showing individual conductive pathways;
(9) FIG. 5(b) shows a current-voltage curve obtained with the STM tip on one of the bright areas on FIG. 5(a);
(10) FIG. 6 shows Cole-Cole plots with theoretical models under 1V in (a) the off state and (b) the on state;
(11) FIG. 7(a) shows current-voltage characteristics in negative bias showing unipolar switching;
(12) FIGS. 7(b) and (c) show current-voltage characteristics for positive and negative bias in a memory resistor of the present invention;
(13) FIG. 7(d) shows sequential cycling between the off and on states of a memory resistor of the present invention;
(14) FIGS. 8 (a) and (b) show current-voltage graphs under positive bias and negative bias, respectively; and
(15) FIGS. 8 (c) and (d) show current-time graphs under a constant voltage bias of 8V and 10V, respectively.
(16) FIGS. 1 and 2(a) to (c) show cross sections of a memory resistor (10) of the present invention. The memory resistor (10) comprises a first electrode (2), a dielectric layer (4) containing nanoparticles of semiconductor material (not shown in FIG. 1) and a second electrode (6). By forming electrical connections (14) to the first electrode (2) and the second electrode (6), the second electrode (6) can be biased to provide a series of potential differences the dielectric layer (4), allowing the memory resistor (10) to be cycled between an off state and an on state, as required.
(17) In the on state, nanoparticles of semiconductor material form a conductive filament. FIGS. 2(a) to (c) show a series of schematic diagrams illustrating a possible process for the formation of a conductive filament (16) in the memory resistor (10). The memory resistor (10) in FIG. 2(a) is in the off state, where resistance is high relative to the on state and where there is no conductive filament in the dielectric layer (4). Without being bound by theory it is believed that the dielectric layer may contain large semiconductor clusters (8) having a size of about 2 nm or more and small semiconductor particles (12) having a size of <1 nm. On the application of an applied field (14) across the dielectric layer (4), the small semiconductor particles (12) migrate and form a conduction bridge between larger semiconductor clusters (8), thereby forming a conduction filament (16) encapsulated by the dielectric layer (4). The memory resistor (10) in FIG. 2(b) is in the on state. A possible mechanism for the formation of conductive filaments is DC dielectrophoresis. Applying a DC electric field across the dielectric layer (4) produces an induced dipole in the semiconductor nanoparticles (12) within the dielectric layer (4). Given sufficient mobility of semiconductor nanoparticles and a non-uniform field, these nanoparticles interact through dipole-dipole interactions and faun chains (16). As shown in FIG. 2(c), when a high current (18) is passed through the memory resistor (10) destruction of the conductive filament (16) occurs. This returns the memory resistor (10) to the off state as shown in FIG. 2(a). Without being bound by theory it is believed that destruction of the conductive filament (16) is driven by Joule heating (20) due to the high current (18). The memory resistor (10) can be cycled between the on and off states by repeating the steps illustrated in FIGS. 2(a) to (c).
(18) FIG. 3 shows an array (100) of memory resistors (110) of the present invention. The array (100) is supported on a substrate (112) which can be an electrical contact, such as an AuCr contact. The first electrode (114) and the dielectric layer (116) containing semiconductor nanoparticles form continuous layers over the contact (112). A pattern of second electrodes (118) is deposited in order to make an array of memory resistors (110).
EXAMPLE 1
(19) A memory resistor is made by depositing a 37 nm thick layer of silica containing about 5-10% excess silicon onto a layer of p-type (boron doped) silicon. The silica layer is deposited by magnetron co-sputtering using two confocal cathodes, a pure Ar plasma and SiO.sub.2 and Si targets.
(20) The layers are annealed for about 1 hour in nitrogen at 900 C. to form nanometre-sized particles of silicon having an average diameter of about 2 to about 3 nm from the excess silicon. Layer thicknesses are measured using ellipsometry. X-ray photoelectron spectroscopy (XPS) measurements from a Perkin-Elmer PHI-5500 instrument using Ar.sup.+ ion beam at 4 keV are performed to characterize the amount of excess silicon.
(21) A top electrode structure of either 60 nm indium tin oxide (ITO) is deposited by low pressure chemical vapour deposition (LPCVD) onto the layer of silica.
(22) Contacts are deposited underneath the first electrode by successive evaporation of gold and chromium.
EXAMPLE 2
(23) Results of current-voltage measurements performed on the memory resistor prepared in Example 1 using a Keithley 4200-SCS semiconductor Characterization System and a Signatone probe station are shown in FIGS. 4(a) and (b), along with insets showing a logarithmic representation.
(24) All measurements were performed in ambient conditions in an open laboratory.
(25) There is evidence of hysteresis in both positive (FIG. 4(a)) and negative (FIG. 4(b)) bias (positive and negative voltage, respectively) applied to the top electrode. Under positive bias, the initial high impedance state (the off state) switches to a low impedance state (the on state) once a threshold voltage is reached (shown by lines with unfilled circles (200)). It is evident that reducing the voltage below the threshold level does not switch the device to its initial state, and the device now allows a much larger current to flow (line with filled circles). The transition between high and low resistance states is abrupt and does not depend on the voltage sweep speed. The low impedance state is stable, and the device stays in this state until a certain level of current is reached. A prompt drop in current can be seen in FIG. 4(b) (line with filled circles) when the required current level is reached under negative bias.
(26) The switching processes are repeatable and the states are stable. The memory resistors are stable in both states for at least 48 hours and no degradation is observed in the resistive behaviour of the devices. FIG. 4(d) shows retention times for both on and off states tested by +1V pulse over a 4 hour period.
(27) FIG. 4(c) shows the results of sequential cycling between the off and the on states, which is relevant to the application of memory resistors to device programming Short (5 ms) voltage pulses of +15V, 15V and +1V are used for setting, resetting and reading, respectively. A voltage of +1V pulse is used for reading as this does not affect the memory resistor state. The upper trace shows the sequence of programming and read voltages and the lower trace shows the resultant device currents. The memory resistors are stable when subjected to at least 4000 programming cycles.
(28) The resistive switching processes displayed by the memory resistor are attributed intrinsically to the silicon-rich silica layer. Filament formation driven by ion diffusion from the ITO contacts is ruled out as ITO can be used as an effective diffusion barrier. Furthermore, the set/reset process is not dependant on bias polarity, which excludes the possibility that conduction is driven by the migration of a single charged species. In addition, measurements performed on samples fabricated with both an ITO top electrode and an n-type silicon top electrode contact show similar behaviour of clear controllable switching.
EXAMPLE 3
(29) Scanning Tunnelling Microscopy (STM) of an area of the sample away from the top electrode of the ITO electrode memory resistor prepared in Example 1 is shown in FIG. 5(a). Light areas correspond to individual conductive pathways (that is, single conductive filaments). IV characteristics of the light and dark areas on the STM image confirm that dark areas have very high resistance, exhibiting dielectric-like behaviour, while light areas exhibit semiconductor-like conductivity.
(30) FIG. 5b shows a typical IV curve from one of the light areas. Such conductive pathways are of the order of 10 nm in diameter, suggesting that memristive devices based on the memory resistors of the present invention may be scaled down to the nanometre scale to achieve very high levels of integration.
EXAMPLE 4
(31) Impedance Spectroscopy measurements performed on the memory resistor of Example 1 using a 1V sine-wave bias at frequencies up to 10.sup.7 Hz show a clear difference between the device in the high and low resistance state. In the off state (see FIG. 6(a)), the fitted model suggests an equivalent circuit model with a single parallel capacitor and resistor (R=2.0710.sup.8 and C=4.6410.sup.10 F). In the on state (see FIG. 6(b)), there are two small semi-circles, suggesting a model with additional parallel resistors and capacitors in series (R1=1.7410.sup.4, C1=1.0910.sup.10 F. and R2=1.3310.sup.3, C2=3.2710.sup.8 F).
(32) The results are consistent with the formation and destruction of conductive pathways. In the off state, the device appears to behave as a single MOS structure with carrier transport predominantly by Fowler-Nordheim tunnelling between the top and bottom electrodes, while in the on state a continuous chain of nanoparticles allows transport via Poole-Frenkel hopping or trap-assisted tunnelling between adjacent nanoparticles.
EXAMPLE 5
(33) A memory resistor is made by depositing a 37 nm thick layer of silica containing about 5-10% excess silicon onto a layer of p-type (boron doped) silicon. The silica layer is deposited by magnetron co-sputtering using two confocal cathodes, a pure Ar plasma and SiO.sub.2 and Si targets.
(34) The layers are annealed for about 1 hour in nitrogen at 900 C. to form nanometre-sized particles of silicon (silicon nanoclusters) having an average diameter of about 2 to about 3 nm from the excess silicon. Layer thicknesses are measured using ellipsometry. X-ray photoelectron spectroscopy (XPS) measurements from a Perkin-Elmer PHI-5500 instrument using Ar.sup.+ ion beam at 4 keV are performed to characterize the amount of excess silicon.
(35) A top electrode of 200 nm n-type (P-doped) polycrystalline silicon, having a sheet resistance of 1 mcm.sup.1, is deposited by low pressure chemical vapour deposition (LPCVD) onto the layer of silica. The resulting memory resistor has an asymmetric structure in that the doping of the first electrode (p-type) and the second electrode (n-type) are of opposite polarities, allowing the definition of accumulation and inversion bias regimes in the MOS structure.
(36) The polycrystalline silicon top electrode contact is defined using photolithography and plasma etching to be about 10.sup.4 mm.sup.2 in size.
(37) Contacts are deposited underneath the first electrode by successive evaporation of gold and chromium.
EXAMPLE 6
(38) Results of current-voltage measurements performed on the memory resistor prepared in Example 5 using a Keithley 4200-SCS semiconductor Characterization System and a Signatone probe station are shown in FIGS. 7(a) to (c) and FIGS. 8(a) and (b). Results of the current variation with switching cycles are shown in FIG. 7(d). Results of the current variation with time under a constant voltage bias of 8V and 10V are shown in FIGS. 8(c) and (d).
(39) All measurements were performed in ambient conditions in an open laboratory.
(40) The current-voltage graph in FIG. 7(a) in negative bias shows unipolar switching. There is evidence of hysteresis in both positive (FIG. 7(b)) and negative (FIG. 7(c)) bias (positive and negative voltage, respectively) applied to the top electrode. Positive bias is an inversion regime whereas negative bias is an accumulation regime. Under positive bias (inversion), the initial high impedance state (the off state) switches to a low impedance state (the on state) once a threshold voltage is reached (line (300) in FIG. 7(b)). It is evident that reducing the voltage below the threshold level does not switch the device to its initial state, and the device now allows a much larger current to flow (line 400 in FIG. 7(b)). The transition between high and low resistance states is abrupt and does not depend on the voltage sweep speed. The low impedance state is stable, and the device stays in this state until a certain level of current is reached, which can be in either polarity. A prompt drop in current can be seen in FIG. 7(c) (line 500) when the required current level is reached under negative bias.
(41) The formation (set) process is achievable again either in inversion or accumulation and the switching process is intrinsically unipolar as seen in FIG. 7(a).
(42) The switching processes are repeatable and the states are stable. The memory resistor is stable in both states for at least 72 hours and no degradation is observed in the resistive behaviour of the device.
(43) FIG. 7(d) shows the results of sequential cycling between the off and the on states, which is relevant to the application of memory resistors to device programming. Short (5 ms) voltage pulses of +15V, 15V and +1V are used for setting, resetting and reading, respectively. A voltage of +1V pulse is used for reading as this does not affect the state of the memory resistor. Programming is achieved using 10V pulses as short as 90 ns. The switching energy is calculated to be no higher than 2 pJ/bit. The memory resistor is stable when subjected to at least 4000 programming cycles.
(44) FIG. 8(a) shows that the formation/destruction process in the memory resistor is independent of bias polarity. This indicates that conduction is due to migration of a single charged species.
(45) FIG. 8(a), which is an IV curve in positive bias, shows three distinct levels (two set processes and a competing process between setting and resetting). FIG. 8(b), which is an IV curve in negative bias, also shows three distinct levels (two reset processes and competing process). This shows that three levels can be obtained with this device, which may be useful for multi-level logic systems.
(46) FIGS. 8(c) and (d) show current-time graphs under constant voltage biases of 8V and of 10V. Formation (set) and destruction (reset) processes act in opposition. FIGS. 8(c) and (d) show sudden current drops followed by exponential increases. The measurement time resolution (5 ms) is insufficient to track the set/reset process, preventing observation of the complete OFF state. Nevertheless, a very rapid current decrease followed by a slower recovery is observed. Recovery speed is proportional to the applied voltage; the time constant decreases from 10 sec to around 0.5 sec on changing the bias from 8V to 10V. Higher negative voltages reset the device faster than can be resolved by the measurement system without repetitive transitions to the ON state, as the current is sufficient for conductive pathway destruction to dominate. A similar scenario with a stable ON state occurs when the bias is decreased to values lower than 6V. These results indicate that there are two conditions: high field and low current (inversion) in which filament formation is favoured; and high field and high current (accumulation) in which destruction dominates. No reset process is observed by applying a high negative bias with limited current (10.sup.7 A) to the memory resistor, regardless of bias level, indicating that the reset process is current-driven through Joule heating.
(47) The resistive switching processes displayed by the memory resistor are attributed intrinsically to the silicon-rich silica layer. The set/reset process is not dependent on bias polarity, which excludes the possibility that conduction is driven by the migration of a single charged species. In addition, measurements performed on samples fabricated with an n-type silicon top electrode contact show similar behaviour of clear controllable switching compared to those having an ITO top electrode.
(48) It will, of course, be understood that the present invention has been described above purely by way of example and that modifications of detail can be made within the scope of the invention.
