Digital-controlled vector signal modulator

Abstract

A vector modulator includes a quadrature component generator, configured to generate an input in-phase signal and an input quadrature signal according to an input radio frequency (RF) signal; a switching circuit, receiving a plurality of bits, comprising a plurality of switches controlled by the plurality of bits, configured to generate an output in-phase signal and an output quadrature signal according to the plurality of bits, where the output in-phase signal and the output quadrature signal are related to input in-phase signal and the input quadrature signal; and a combining module, configured to generate an output RF signal according to the output in-phase signal and the output quadrature signal.

Claims

1. A vector modulator, comprising: a quadrature component generator, configured to generate an input in-phase signal and an input quadrature signal according to an input radio frequency (RF) signal; a switching circuit, receiving a plurality of bits, comprising a plurality of switches controlled by the plurality of bits, configured to generate an output in-phase signal and an output quadrature signal according to the plurality of bits, where the output in-phase signal and the output quadrature signal are related to input in-phase signal and the input quadrature signal; and a combining module, configured to generate an output RF signal according to the output in-phase signal and the output quadrature signal.

2. The vector modulator of claim 1, wherein the switching circuit comprises: a switching input terminal, coupled to the quadrature component generator; a switching output terminal, coupled to the combining module; a plurality of conducting switches, coupled between the switching input terminal and the switching output terminal, controlled by a plurality of conducting bits within the plurality of bits; and a plurality of diverting switches, coupled to the switching input terminal and receiving a voltage, controlled by a plurality of diverting bits within the plurality of bits, wherein the plurality of diverting bits are complements of the plurality of conducting bits.

3. The vector modulator of claim 1, further comprising an in-phase amplifier, coupled between the quadrature component generator and the switching circuit, configured to receive the input in-phase signal and output an intermediate in-phase signal; and a quadrature amplifier, coupled between the quadrature component generator and the switching circuit, configured to receive the input quadrature signal and output an intermediate quadrature signal.

4. The vector modulator of claim 3, wherein the input in-phase signal comprises a first input in-phase signal and a second input in-phase signal; the input quadrature signal comprises a first input quadrature signal and a second input quadrature signal; the in-phase amplifier comprises a first in-phase output terminal and a second in-phase output terminal; the quadrature amplifier comprises a first quadrature output terminal and a second quadrature output terminal; the intermediate in-phase signal comprises a first intermediate in-phase signal and a negative intermediate in-phase signal; the intermediate quadrature signal comprises a first intermediate quadrature signal and a negative intermediate quadrature signal; the output in-phase signal comprises a first output in-phase signal and a second output in-phase signal; the output quadrature signal comprises a first output quadrature signal and a second output quadrature signal; the output RF signal comprises a first output RF signal and a second output RF signal; and the combining module comprises: a first combining element, configured to generate the first output RF signal according to the first output in-phase signal and the first output quadrature signal; and a second combining element, configured to generate the second output RF signal according to the second output in-phase signal and the second output quadrature signal.

5. The vector modulator of claim 4, wherein the switching circuit comprises: a first in-phase switching sub-circuit, comprising: a first in-phase switching input terminal, coupled to the first in-phase output terminal of the in-phase amplifier; a second in-phase switching input terminal, coupled to the second in-phase output terminal of the in-phase amplifier; a first in-phase switching output terminal; a second in-phase switching output terminal; a plurality of first in-phase conducting switches, coupled between the first in-phase switching input terminal and the first in-phase switching output terminal, controlled by a plurality of in-phase conducting bits within the plurality of bits; and a plurality of second in-phase conducting switches, coupled between the second in-phase switching input terminal and the second in-phase switching output terminal, controlled by the plurality of in-phase conducting bits within the plurality of bits; a plurality of first in-phase diverting switches, coupled to the first in-phase switching input terminal and receiving a voltage, controlled by a plurality of in-phase diverting bits within the plurality of bits, wherein the plurality of in-phase diverting bits are complements of the plurality of in-phase conducting bits; and a plurality of second in-phase diverting switches, coupled to the second in-phase switching input terminal and receiving the voltage, controlled by the plurality of in-phase diverting bits; and a first quadrature switching sub-circuit, comprising: a first quadrature switching input terminal, coupled to the first quadrature output terminal of the quadrature amplifier; a second quadrature switching input terminal, coupled to the second quadrature output terminal of the quadrature amplifier; a first quadrature switching output terminal; a second quadrature switching output terminal; a plurality of first quadrature conducting switches, coupled between the first quadrature switching input terminal and the first quadrature switching output terminal, controlled by a plurality of quadrature conducting bits within the plurality of bits; a plurality of second quadrature conducting switches, coupled between the second quadrature switching input terminal and the second quadrature switching output terminal, controlled by the plurality of quadrature conducting bits within the plurality of bits; a plurality of first quadrature diverting switches, coupled to the first quadrature switching input terminal and receiving the voltage, controlled by a plurality of quadrature diverting bits within the plurality of bits, wherein the plurality of quadrature diverting bits are complements of the plurality of first quadrature conducting bits; and a plurality of second quadrature diverting switches, coupled to the second quadrature switching input terminal and receiving the voltage, controlled by the plurality of quadrature diverting bits.

6. The vector modulator of claim 5, wherein the switching circuit comprises: a second in-phase switching sub-circuit, comprising: a first in-phase switching input terminal, coupled to the second in-phase output terminal of the in-phase amplifier; a second in-phase switching input terminal, coupled to the first in-phase output terminal of the in-phase amplifier; a first in-phase switching output terminal; a second in-phase switching output terminal; a plurality of first in-phase conducting switches, coupled between the first in-phase switching input terminal and the first in-phase switching output terminal, controlled by a plurality of in-phase conducting bits within the plurality of bits; and a plurality of second in-phase conducting switches, coupled between the second in-phase switching input terminal and the second in-phase switching output terminal, controlled by the plurality of in-phase conducting bits within the plurality of bits; a plurality of first in-phase diverting switches, coupled to the first in-phase switching input terminal and receiving the voltage, controlled by a plurality of in-phase diverting bits within the plurality of bits, wherein the plurality of first in-phase diverting bits are complements of the plurality of in-phase conducting bits; and a plurality of second in-phase diverting switches, coupled to the second in-phase switching input terminal and receiving the voltage, controlled by the plurality of in-phase diverting bits; and a second quadrature switching sub-circuit, comprising: a first quadrature switching input terminal, coupled to the second quadrature output terminal of the quadrature amplifier; a second quadrature switching input terminal, coupled to the first quadrature output terminal of the quadrature amplifier; a first quadrature switching output terminal; a second quadrature switching output terminal; a plurality of first quadrature conducting switches, coupled between the first quadrature switching input terminal and the first quadrature switching output terminal, controlled by a plurality of quadrature conducting bits within the plurality of bits; a plurality of second quadrature conducting switches, coupled between the second quadrature switching input terminal and the second quadrature switching output terminal, controlled by the plurality of quadrature conducting bits within the plurality of bits; a plurality of first quadrature diverting switches, coupled to the first quadrature switching input terminal and receiving the voltage, controlled by a plurality of quadrature diverting bits within the plurality of bits, wherein the plurality of first quadrature diverting bits are complements of the plurality of first quadrature conducting bits; and a plurality of second quadrature diverting switches, coupled to the second quadrature switching input terminal and receiving the voltage, controlled by the plurality of quadrature diverting bits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of a vector modulator according to an embodiment of the present invention.

(2) FIG. 2 is a schematic diagram of a switching circuit according to an embodiment of the present invention.

(3) FIG. 3 is a schematic diagram of a conduction status of the switching circuit of FIG. 2.

(4) FIG. 4 is a schematic diagram of a switching circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION

(5) The present invention proposes to realize a vector signal modulator directly from the digital control signal without DACs, saving time and the cost the device considerably.

(6) FIG. 1 is a schematic diagram of a vector modulator 10 according to an embodiment of the present invention. The vector modulator 10 comprises a quadrature component generator 12, an in-phase amplifier I-Amp, a quadrature amplifier Q-Amp, a switching circuit 14 and a combining module 16. Note that, the vector modulator 10 does not include any digital-to-analog converter (DAC). Specifically, the quadrature component generator 12 receives an input radio frequency (RF) signal RF.sub.in and generates an input in-phase signal I.sub.i and an input quadrature signal Q.sub.i according to the RF signal RF.sub.in. The input in-phase signal I.sub.i and the input quadrature signal Q.sub.i have 90 phase difference. The in-phase amplifier I-Amp receives the input in-phase signal I.sub.i and generates an intermediate in-phase signal I.sub.m; the quadrature amplifier Q-Amp receives the input quadrature signal Q.sub.i and generates the intermediate quadrature signal Q.sub.m. The switching circuit 14 comprises a plurality of switches (which will be illustrated later on) and receives a plurality of bits B.sub.i, . . . , B.sub.N, where the bits B.sub.i, . . . , B.sub.N are configured to control an ON-OFF status of the plurality of switches. The switching circuit 14 is configured to adjust the input in-phase signal I.sub.i to generate an output in-phase signal I.sub.o, and to adjust the input quadrature signal Q.sub.i to generate an output quadrature signal Q.sub.o, according to the bits B.sub.i, . . . , B.sub.N. The combining module 16 is configured to combine the output in-phase signal I.sub.o and the output quadrature signal Q.sub.o to generate an output RF signal RF.sub.out.

(7) The signals RF.sub.in, I.sub.i, Q.sub.i, I.sub.m, Q.sub.m, I.sub.o, Q.sub.o and RF.sub.out may be voltage signals or current signals. In an embodiment, the signals RF.sub.in, I.sub.i, Q.sub.i, I.sub.m, Q.sub.m, I.sub.o, Q.sub.o and RF.sub.out are all differential signals, but not limited thereto. For example, as illustrated in FIG. 1, the RF signal RF.sub.in/RF.sub.out comprises a positive input/output RF signal RF.sub.in+/RF.sub.out+ and a negative input/output RF signal RF.sub.in/RF.sub.out, the input/intermediate/output in-phase signal I.sub.i/I.sub.m/I.sub.o comprises a positive input/intermediate/output in-phase signal I.sub.i+/I.sub.m+/I.sub.o+ and a negative input/intermediate/output in-phase signal I.sub.i/I.sub.m/I.sub.o, and the input/intermediate/output quadrature signal Q.sub.i/Q.sub.m/Q.sub.o comprises a positive input/intermediate/output quadrature signal Q.sub.i+/Q.sub.m+/Q.sub.o+ and a negative input/intermediate/output quadrature signal Q.sub.i/Q.sub.m/Q.sub.o.

(8) The in-phase amplifier I-Amp and the quadrature amplifier Q-Amp are full differential amplifiers. The in-phase amplifier I-Amp comprises a positive in-phase output terminal O.sub.I+ and a negative in-phase output terminal O.sub.I. The quadrature amplifier Q-Amp comprises a positive quadrature output terminal O.sub.Q+ and a negative quadrature output terminal O.sub.Q.

(9) In this regard, the combining module 16 may comprise a first combining element CE+ and a second combining element CE. The first combining element CE+ is configured to generate the positive output RF signal RF.sub.out+ by combining the positive output in-phase signal I.sub.o+ and the positive output quadrature signal Q.sub.o+. The positive output RF signal RF.sub.out+ may be expressed as RF.sub.out+=I.sub.o++j*Q.sub.o+. The second combining element CE is configured to generate the negative output RF signal RF.sub.out+ by combining the negative output in-phase signal I.sub.o and the negative output quadrature signal Q.sub.o. The negative output RF signal RF.sub.out may be expressed as RF.sub.out=I.sub.o+j*Q.sub.o.

(10) FIG. 2 is a schematic diagram of a switching circuit 24 according to an embodiment of the present invention. The switching circuit 24 is an embodiment of the switching circuit 14. The switching circuit 24 comprises a first in-phase switching sub-circuit SW.sub.I+ and a first quadrature switching sub-circuit SW.sub.Q+. The in-phase switching sub-circuit SW.sub.I+ and the quadrature switching sub-circuit SW.sub.Q+ have similar circuit structure.

(11) The first in-phase switching sub-circuit STAI.sub.I+ comprises a first in-phase switching input terminal N.sub.Iin+, a second in-phase switching input terminal N.sub.Iin, a first in-phase switching output terminal N.sub.Iout+, a second in-phase switching output terminal N.sub.Iout, in-phase conducting switches S.sub.I1+, S.sub.I0+, S.sub.I0, S.sub.I and in-phase diverting switches S.sub.I1+, S.sub.I0+, S.sub.I1, S.sub.I0. The first in-phase switching input terminal N.sub.Iin+ of the in-phase switching sub-circuit SW.sub.I+ is coupled to the positive in-phase output terminal O.sub.I+. The second in-phase switching input terminal N.sub.Iin of the in-phase switching sub-circuit SW.sub.I+ is coupled to the negative in-phase output terminal O.sub.I. The in-phase conducting switches S.sub.I1+, S.sub.I0+, controlled by in-phase conducting bits B.sub.I0, B.sub.I1, are coupled between the first in-phase switching input terminal N.sub.Iin+ and the first in-phase switching output terminal N.sub.Iout+. The in-phase conducting switches S.sub.I0, S.sub.I1, also controlled by the in-phase conducting bits B.sub.I0, B.sub.I1, are coupled between the second in-phase switching input terminal N.sub.Iin and the second in-phase switching output terminal N.sub.Iout. The in-phase diverting switches S.sub.I1+, S.sub.I0+, controlled by in-phase diverting bits B.sub.I0, B.sub.I1, have one terminal coupled to the first in-phase switching input terminal N.sub.Iin+ and have another terminal to receive a voltage VDD. The in-phase diverting switches S.sub.I1, S.sub.I0, also controlled by the in-phase diverting bits B.sub.I0, B.sub.I1, have one terminal coupled to the second in-phase switching input terminal N.sub.Iin and have another terminal to receive the voltage VDD. The in-phase diverting bits B.sub.I0, B.sub.I1, are complements of the in-phase conducting bits B.sub.I0, B.sub.I1.

(12) The first quadrature switching sub-circuit SW.sub.Q+ comprises a first quadrature switching input terminal N.sub.Qin+, a second quadrature switching input terminal N.sub.Qin, a first quadrature switching output terminal N.sub.Qout+, a second quadrature switching output terminal N.sub.Qout, quadrature conducting switches S.sub.Q1+, S.sub.Q0+, S.sub.Q0, S.sub.Q1 and quadrature diverting switches S.sub.Q1+, S.sub.Q0+, S.sub.Q1, S.sub.Q0. The first quadrature switching input terminal N.sub.Qin+ of the quadrature switching sub-circuit SW.sub.Q+ is coupled to the positive quadrature output terminal O.sub.Q+. The second quadrature switching input terminal N.sub.Qin of the quadrature switching sub-circuit SW.sub.Q+ is coupled to the negative quadrature output terminal O.sub.Q. The quadrature conducting switches S.sub.Q1+, S.sub.Q0+, controlled by quadrature conducting bits B.sub.Q0, B.sub.Q1, are coupled between the first quadrature switching input terminal N.sub.Qin+ and the first quadrature switching output terminal N.sub.Qout+. The quadrature conducting switches S.sub.Q0, S.sub.Q1, also controlled by the quadrature conducting bits B.sub.Q0, B.sub.Q1, are coupled between the second quadrature switching input terminal N.sub.Qin and the second quadrature switching output terminal N.sub.Qout. The quadrature diverting switches S.sub.Q1+, S.sub.Q0+, controlled by quadrature diverting bits B.sub.Q0, B.sub.Q1, have one terminal coupled to the first quadrature switching input terminal N.sub.Qin+ and have another terminal to receive the voltage VDD. The quadrature diverting switches S.sub.Q1, S.sub.Q0, also controlled by the quadrature diverting bits B.sub.Q0, B.sub.Q1, have one terminal coupled to the second quadrature switching input terminal N.sub.Qin and have another terminal to receive the voltage VDD.

(13) The conducting bits B.sub.I0, B.sub.I1, B.sub.Q0, B.sub.Q1 (or the diverting bits B.sub.I0, B.sub.I1, B.sub.Q0, B.sub.Q1) of the switching circuit 24 may be regarded as the bits B.sub.1, . . . , B.sub.N of the switching circuit 14 . The diverting bits B.sub.I0, B.sub.I1, B.sub.Q0, B.sub.Q1 are complements of the conducting bits B.sub.I0, B.sub.I1, B.sub.Q0, B.sub.Q1. That is, B.sub.I0=0 when B.sub.I0=1 and B.sub.I0=1 when B.sub.I0=0, for instance.

(14) Operations of the switching circuit 24 are described as follows. FIG. 3 is a schematic diagram of a conduction status of the switching circuit 24. Suppose that (B.sub.I0, B.sub.I1, B.sub.Q0, B.sub.Q1) is (1, 0, 1, 1) , which means that the switches S.sub.I0+, S.sub.I0, S.sub.I1+, S.sub.I1, S.sub.Q1+, S.sub.Q0+, S.sub.Q0, S.sub.Q1 are conducted (ON) and the switches S.sub.I1+, S.sub.I1, S.sub.I0+, S.sub.I0, S.sub.Q1+, S.sub.Q0+, S.sub.Q1, S.sub.Q0 are cutoff (OFF) . Suppose that an output current of the in-phase amplifier I-Amp is denoted as I.sub.I and an output current of the quadrature amplifier Q-Amp is denoted as I.sub.Q. Within the in-phase switching sub-circuit SW.sub.I+, half of the output current I.sub.I (i.e., 0.5 I.sub.I) would flow through the conducting switches S.sub.I0+, S.sub.I0 and another half of the output current I.sub.I (i.e., 0.5 I.sub.I) would be diverted through the diverting switches S.sub.I1+, S.sub.I1. Current through the in-phase switching output terminals N.sub.Iout+, N.sub.Iout would be 0.5 I.sub.I. On the other hand, within the quadrature switching sub-circuit SW.sub.Q+, all of the output current I.sub.Q would flow through the conducting switches S.sub.Q1+, S.sub.Q0+, S.sub.Q0, S.sub.Q1 and no current is diverted through the diverting switches S.sub.Q1+, S.sub.Q0+, S.sub.Q1, S.sub.Q0. Current through the quadrature switching output terminals N.sub.Qout+, N.sub.Qout would be I.sub.Q. Therefore, the output RF signal RF.sub.out would have a phase as tan.sup.1 (|I.sub.Q|/0.5|I.sub.I|), where tan.sup.1(.Math.) denotes an inverse of tangent function. Suppose that |I.sub.Q|=|I.sub.I|, meaning that the in-phase amplifier I-Amp and the quadrature amplifier Q-Amp produces the same output current, the phase difference is tan.sup.1(2).

(15) In another perspective, the switching circuit 24 is controlled mainly by 4 bits, where 2 bits are used for controlling in-phase component (i.e., the output in-phase signal I.sub.o) and 2 bits are used for quadrature component (i.e., the output quadrature signal Q.sub.o), which is for illustrative purpose. In practice, the switching circuit 14 may be controlled by 2*M bits, where M bits are used for controlling/adjusting in-phase component and M bits are used for controlling/adjusting the quadrature component, and various values of the phase difference would be generated.

(16) In the prior art, the vector modulator utilizes variable gain amplifier (VGA) to adjust the in-phase component and the quadrature component. However, the VGA needs an analog signal to control the gain of the VGA, and a DAC is required, which increases a circuit complexity since the DAC is complicated. In comparison, by utilizing the switching circuit of the present invention, the digital bits B.sub.1, . . . , B.sub.N (e.g., the conducting bits B.sub.I0, B.sub.I1, B.sub.Q0, B.sub.Q1 or the diverting bits B.sub.I0, B.sub.I1, B.sub.Q0, B.sub.Q1) can be directly used to control/adjust the in-phase component and the quadrature component, such that the complexity and the production cost brought by DAC may be spared.

(17) Note that, the switching circuit 24 generates the phase difference only within a range between 0 and 90 , i.e., the first quadrant of a complex plane, and not limited thereto. The switching circuit of the present invention may generate the phase difference distributed over a range between 0 and 360 .

(18) For example, FIG. 4 is a schematic diagram of a switching circuit 44 according to an embodiment of the present invention. The switching circuit 44 is similar to the switching circuit 24, and thus, the same denotations are applied. Different from the switching circuit 24, the switching circuit 44 further comprises a second in-phase switching sub-circuit SW.sub.I and a second quadrature switching sub-circuit SW.sub.Q, in addition to the first in-phase switching sub-circuit SW.sub.I+ and the first quadrature switching sub-circuit SW.sub.Q+. The in-phase switching sub-circuit SW.sub.I has the same circuit structure as the in-phase switching sub-circuit SW.sub.I+, and the quadrature switching sub-circuit SW.sub.Q has the same circuit structure as the quadrature switching sub-circuit SW.sub.Q+. Different from the switching sub-circuit SW.sub.I+ and SW.sub.Q+, a first in-phase switching input terminal N.sub.Iin+ of the second in-phase switching sub-circuit SW.sub.I is coupled to the negative in-phase output terminal O.sub.I, a second in-phase switching input terminal N.sub.Iin of the second in-phase switching sub-circuit SW.sub.I is coupled to the positive in-phase output terminal O.sub.I+, a first quadrature switching input terminal N.sub.Qin+ of the second quadrature switching sub-circuit SW.sub.Q is coupled to the negative quadrature output terminal O.sub.Q, and a second quadrature switching input terminal N.sub.Qin of the second quadrature switching sub-circuit SW.sub.Q is coupled to the positive quadrature output terminal O.sub.Q+.

(19) In other words, a current direction of the current flowing through the second in-phase switching sub-circuit SW.sub.I would be opposite to a current direction of the current flowing through the first in-phase switching sub-circuit SW.sub.I+, and a current direction of the current flowing through the second quadrature switching sub-circuit SW.sub.Q would be opposite to a current direction of the current flowing through the first quadrature switching sub-circuit SW.sub.Q+.

(20) When the sub-circuits SW.sub.I and SW.sub.Q+ are enabled, the switching circuit 44 is able to generate the phase difference within a range between 90 and 180 , i.e. , the second quadrant. When the sub-circuits SW.sub.I and SW.sub.Q are enabled, the switching circuit 44 is able to generate the phase difference within a range between 180 and 270 , i.e., the third quadrant. When the sub-circuits SW.sub.I+ and SW.sub.Q are enabled, the switching circuit 44 is able to generate the phase difference within a range between 270 and 360 , i.e., the fourth quadrant. Therefore, the switching circuit 44 is able to generate the phase difference distributed over the range between 0 and 360 .

(21) In summary, the vector modulator utilizes the switching circuit comprising the plurality of switches and controlled by the plurality of bits to control/adjust the in-phase component and the quadrature component, such that the complexity and the production cost brought by DAC may be spared.

(22) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.