SAMPLING DEVICE

Abstract

A sampling device includes a switch capacitor circuit. First ends of two switches are respectively connected to an input signal. Second end of the first switch is connected to an upper plate of a first capacitor. Second end of the second switch is connected to a lower plate of a second capacitor. A connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source. The first ends of a third switch and a fourth switch are respectively connected to an input common-mode voltage. A second end of the third switch is connected to the upper plate of the first capacitor. A second end of the fourth switch is connected to the lower plate of the second capacitor. The connection node is connected to the power source. Thus, an output common-mode voltage of the sampling device is adjustable.

Claims

1. A sampling device, comprising a switch capacitor circuit, the switch capacitor circuit comprising a first switch, a second switch, a first capacitor and a second capacitor, wherein the first ends of the first switch and the second switch are respectively connected to an input signal, a second end of the first switch is connected to an upper plate of the first capacitor, a second end of the second switch is connected to a lower plate of the second capacitor, a connection node connecting a lower plate of the first capacitor to an upper plate of the second capacitor is connected to a power source, and signal sampling is performed by controlling the closing of the first switch and the second switch.

2. The device according to claim 1, wherein the switch capacitor circuit further comprises a third switch and a fourth switch, wherein the first ends of the third switch and the fourth switch are respectively connected to an input common-mode voltage, a second end of the third switch is connected to the upper plate of the first capacitor, a second end of the fourth switch is connected to the lower plate of the second capacitor, and the connection node is connected to the power source through a sampling switch.

3. The device according to claim 2, wherein the sampling device comprises a plurality of switch capacitor circuit groups; for each switch capacitor circuit group, the switch capacitor circuit group comprises a preset corresponding number of switch capacitor circuits; the connection node of each switch capacitor circuit in the switch capacitor circuit group is connected to a non-power source connection end of a corresponding sampling switch; a power source connection end of the corresponding switch capacitor circuit group is connected to a corresponding power source; and a short-circuit switch is connected between the non-power source connection ends of the sampling switches respectively.

4. The device according to claim 3, wherein at least two of the corresponding power sources connected to the sampling switches respectively are different.

5. The device according to claim 3, wherein the sampling device comprises two switch capacitor circuit groups; a first switch capacitor circuit group comprises the first to the m-th switch capacitor circuit; a second switch capacitor circuit group comprises the (m+1)th to the N-th switch capacitor circuit; in each switch capacitor circuit of the first switch capacitor circuit group, the connection node thereof is connected to a power source V.sub.dd through a sampling switch S.sub.1; in each switch capacitor circuit of the second switch capacitor circuit group, the connection node thereof is connected to a power source V.sub.ss through a sampling switch S.sub.1; and a short-circuit switch S.sub.2 is provided between the non-power source connection ends of the sampling switch S.sub.1 and the sampling switch S.sub.1.

6. The device according to claim 5, wherein the power source V.sub.dd and the power source V.sub.ss are different.

7. The device according to claim 6, wherein the sampling device enters a sampling phase to perform charge sampling by controlling the first switches and the second switches of corresponding switch capacitor circuits in the first switch capacitor circuit group and the second switch capacitor circuit group and the sampling switch S.sub.1 and the sampling switch S.sub.1 to close.

8. The device according to claim 7, wherein the sampling device generates an output voltage and enters a comparison phase by controlling the first switches and the second switches of corresponding switch capacitor circuits in the first switch capacitor circuit group and the second switch capacitor circuit group and the sampling switch S.sub.1 and the sampling switch S.sub.1 to open and controlling the third switches and the fourth switches of corresponding switch capacitor circuit in the first switch capacitor circuit group and the second switch capacitor circuit group and the short-circuit switch S.sub.2 to close.

9. The device according to claim 7, wherein the total charge collected by the sampling device after entering the sampling phase is Q.sub.s=2mC.sub.s0(V.sub.inV.sub.dd)+2(Nm)C.sub.s0(V.sub.inV.sub.ss), where V.sub.s0 represents a reference value of the first capacitor and the second capacitor and V.sub.in represents the input voltage.

10. The device according to claim 9, wherein the total charge stored by the sampling device after entering the comparison phase is Q.sub.c=2NC.sub.s0(V.sub.CMIV.sub.O), where C.sub.s0 represents a reference capacitance value of the first capacitor and the second capacitor, V.sub.CMI represents the input common-mode voltage and V.sub.O represents the output voltage; and according to the law of conservation of charge, it is derived that $V_O=-v_{i.Math..Math.n}+\left[\frac{m}{N}.Math.\left(V_{\mathrm{dd}}-V_{\mathrm{ss}}\right)+V_{\mathrm{ss}}\right],$ where v.sub.in represents an alternating component of the input voltage V.sub.in, an output common-mode voltage of the sampling device is $V_{\mathrm{CMO\_T}}=\frac{m}{N}.Math.\left(V_{\mathrm{dd}}-V_{\mathrm{ss}}\right)+V_{\mathrm{ss}},$ and the output common-mode voltage is adjusted by changing the value of m.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 is a circuit diagram of an embodiment of a switch capacitor circuit in a sampling device according to the present disclosure;

[0019] FIG. 2 is another circuit diagram of an embodiment of a switch capacitor circuit in a sampling device according to the present disclosure; and

[0020] FIG. 3 is a circuit diagram of an embodiment of a sampling device according to the present disclosure.

DETAILED DESCRIPTION

[0021] In order to make a person skilled in the art better understand the technical solution in the embodiments of the present disclosure and make the above objects, features and advantages of the embodiments of the present disclosure more clear and understandable, the technical solution in the embodiments of the present disclosure will be described in further detail with reference to the accompanying drawings.

[0022] In the description of the present disclosure, unless stated and defined otherwise, it should be noted that the term connection should be understood broadly, for example, it can be a mechanical connection or an electrical connection and may also be the internal communication of two elements, may also be a direct connection, and may also be an indirect connection through an intermediate medium, and those skilled in the art can understand the particular meaning of the above term according to the particular situation.

[0023] FIG. 1 is a circuit diagram of an embodiment of a switch capacitor circuit in a sampling device according to the present disclosure. The sampling device may comprise a switch capacitor circuit, the switch capacitor circuit comprising a first switch S.sub.11, a second switch S.sub.11, a first capacitor C.sub.S1 and a fourth capacitor C.sub.S1, wherein the first ends of the first switch S.sub.11 and the second switch S.sub.11 may be both connected to an input voltage V.sub.in, a second end of the first switch S.sub.11 is connected to an upper plate of the first capacitor C.sub.S1, a second end of the second switch S.sub.11 is connected to a lower plate of the second capacitor C.sub.S1, a connection node connecting a lower plate of the first capacitor C.sub.S1 to an upper plate of the second capacitor C.sub.S1 are connected to a power source V.sub.dd, and signal sampling is performed by controlling the closing of the first switch S.sub.11 and the second switch S.sub.11.

[0024] In this embodiment, the closing and opening of the first switch S.sub.11 and the second switch S.sub.11 can be controlled by means of a clock signal .sub.1. For example, when the clock signal .sub.1 has a high level, the first switch S.sub.11 and the second switch S.sub.11 can be closed, and when the clock signal .sub.1 has a low level, the first switch S.sub.11 and the second switch S.sub.11 can be opened. When the first switch S.sub.11 and the second switch S.sub.11 are closed, the input voltage V.sub.in can be sampled, at this moment, the voltage V.sub.O+ of the connection node connecting the lower plate of the first capacitor C.sub.S1 to the upper plate of the second capacitor C.sub.S1 is equal to the power source voltage V.sub.dd.

[0025] In the switch capacitor circuit,

V.sub.Cs1=V.sub.inV.sub.dd

V.sub.Cs1=V.sub.ddV.sub.in(1)

where V.sub.Cs1 represents the voltage of the first capacitor C.sub.S1 and V.sub.Cs1 represents the voltage of the second capacitor C.sub.S1.

[0026] In order to research the effect of the capacitance non-linearity, the capacitance value of the capacitor C.sub.s can be represented as:

C.sub.s=C.sub.s0(1+.sub.1V+.sub.2V.sup.2+ . . . )C.sub.s0(1+.sub.1V)(2),

where .sub.1 is the first-order voltage coefficient of the capacitor C.sub.s, .sub.2 is the second-order voltage coefficient of the capacitor C.sub.s, C.sub.s0 represents the reference value of the first capacitor and the second capacitor, and since the high-order coefficient affects the non-linearity of the capacitor very little, merely the effect of the first-order voltage coefficient to the non-linearity of the capacitor is taken into account. Thus, the capacitance value C.sub.S1 of the first capacitor and the capacitance value C.sub.S1 of the second capacitor can be expressed as:

C.sub.s1=C.sub.s0(1+.sub.1V.sub.cs1)

C.sub.s1=C.sub.s0(1+.sub.1V.sub.cs1)(3)

[0027] The charges Q(V.sub.Cs1) and Q(V.sub.Cs1) collected respectively on the first capacitor C.sub.s1 and the second capacitor C.sub.s1 can be obtained according to equations (1) and (3):

[00003]$\begin{array}{cc}Q\left(V_{\mathrm{Cs}.Math..Math.1}\right)={}_0^{V_{\mathrm{Cs}.Math..Math.1}}.Math.C_{s.Math..Math.1}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1}^2\right)& \left(4\right)\\ Q\left(V_{\mathrm{Cs}.Math..Math.1^{}}\right)={}_0^{V_{\mathrm{Cs}.Math..Math.1^{}}}.Math.C_{s.Math..Math.1^{}}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1^{}}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1^{}}^2\right).& \end{array}$

[0028] By then, the charge Q.sub.1 collected on the switch capacitor circuit can be expressed as:

[00004]$\begin{array}{cc}\begin{array}{c}{Q}_1=.Math.Q\left(V_{C.Math..Math.s.Math..Math.1}\right)-Q\left(V_{\mathrm{Cs}.Math..Math.1^{}}\right)\\ =.Math.C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1}^2\right)-C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1^{}}+\frac{{}_1}{2}.Math.V_{C.Math..Math.s.Math..Math.1^{}}^2\right)\\ =.Math.2.Math.C_{s.Math..Math.0}\left(V_{i.Math..Math.n}-V_{\mathrm{dd}}\right).\end{array}& \left(5\right)\end{array}$

[0029] It can be seen according to equation (5) that the charge Q.sub.1 collected on the switch capacitor switch does not include the second-order term relevant to the input voltage, and thus the sampling device can be avoided from generating second-order non-linearity during capacitance sampling, then the linearity of the sampling device can be improved.

[0030] It can be seen from the above embodiment that by means of providing a capacitor respectively on two paths formed by the input voltage, the input switch and the power source and making the polarities of the capacitors provided on the two paths inverse, the present disclosure can make the collected capacitance charge value merely relevant to the first-order term of the input voltage and irrelevant to the second-order term of the input voltage, and thus the second-order non-linearity generated by the traditional sampling device during capacitance sampling can be eliminated and the linearity of the sampling device can be improved.

[0031] FIG. 2 is a circuit diagram of another embodiment of a switch capacitor circuit in a sampling device according to the present disclosure. The difference between the switch capacitor circuits shown in FIG. 2 and FIG. 1 lies in that it may further comprise a third switch S.sub.12 and a fourth switch S.sub.12, wherein the first ends of the third switch S.sub.12 and the fourth switch S.sub.12 are connected to an input common-mode voltage V.sub.CMI, a second end of the third switch S.sub.12 is connected to the upper plate of the first capacitor C.sub.S1, a second end of the fourth switch S.sub.12 is connected to the lower plate of the second capacitor C.sub.S1, and a connection node connecting the lower plate of the first capacitor C.sub.S1 to the upper plate of the second capacitor C.sub.S1 is connected to the power source V.sub.dd through the sampling switch S.sub.1.

[0032] In this embodiment, the closing or opening of the first switch S.sub.11, the second switch S.sub.11 and the sampling switch S.sub.1 can be controlled by means of a clock signal .sub.1. For example, when the clock signal .sub.1 has a high level, the first switch S.sub.11, the second switch S.sub.11 and the sampling switch S.sub.1 can be closed, and when the clock signal .sub.1 has a low level, the first switch S.sub.11, the second switch S.sub.11 and the sampling switch S.sub.1 can be opened. When the first switch S.sub.11, the second switch S.sub.11 and the sampling switch S.sub.1 are closed, the switch capacitor circuit enters a sampling phase. The closing and opening of the third switch S.sub.12 and the fourth switch S.sub.12 can be controlled by means of a clock signal .sub.2. For example, when the clock signal .sub.2 has a high level, the third switch S.sub.12 and the fourth switch S.sub.12 can be closed, and when the clock signal .sub.2 has a low level, the third switch S.sub.12 and the fourth switch S.sub.12 can be opened. When the third switch S.sub.12 and the fourth switch S.sub.12 are closed and the first switch S.sub.11, the second switch S.sub.11 and the sampling switch S.sub.1 are closed, the switch capacitor circuit enters a comparison phase.

[0033] When the switch capacitor circuit shown in FIG. 2 performs voltage sampling on the input voltage, the first switch S.sub.11, the second switch S.sub.11 and the sampling switch S.sub.1 can be first controlled to be closed, and at this moment, the switch capacitor circuit enters the sampling phase, which can collect the charge Q.sub.1 in equation (5) in the same manner as the embodiment shown in FIG. 1, then the third switch S.sub.12 and the fourth switch S.sub.12 are controlled to be closed and the first switch S.sub.11, the second switch S.sub.11 and the sampling switch S.sub.1 are opened, and at this moment, the switch capacitor circuit enters the comparison phase, which can calculate the stored charge Q.sub.1 in the following manner.

[0034] When the third switch S.sub.12 and the fourth switch S.sub.12 are closed and the sampling switch S.sub.1 is closed. In the switch capacitor circuit,

V.sub.Cs1=V.sub.CMIV.sub.O+

V.sub.Cs1=V.sub.O+V.sub.CMI(6)

where
C.sub.Cs1 represents the voltage of the first capacitor C.sub.S1, V.sub.Cs1 represents the voltage of the second capacitor C.sub.S1, V.sub.O+ represents the voltage across the connection node connecting the lower plate of the first capacitor C.sub.S1 to the upper plate of the second capacitor C.sub.S1, that is, the output voltage.

[0035] The capacitance value C.sub.S1 of the first capacitor and the capacitance value C.sub.S1 of the second capacitor can be expressed as:

C.sub.s1=C.sub.s0(1+.sub.1V.sub.cs1)

C.sub.s1=C.sub.s0(1+.sub.1V.sub.cs1)(7).

[0036] The charges Q(V.sub.Cs1) and Q(V.sub.Cs1) stored respectively on the first capacitor C.sub.S1 and the second capacitor C.sub.S1 can be obtained according to equations (6) and (7):

[00005]$\begin{array}{cc}Q\left(V_{\mathrm{Cs}.Math..Math.1}^{}\right)={}_0^{V_{\mathrm{Cs}.Math..Math.1}^{}}.Math.C_{s.Math..Math.1}^{}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1}^{.Math..Math.2}\right)& \left(8\right)\\ Q\left(V_{\mathrm{Cs}.Math..Math.1^{}}^{}\right)={}_0^{V_{\mathrm{Cs}.Math..Math.1^{}}^{}}.Math.C_{s.Math..Math.1^{}}^{}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1^{}}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1^{}}^{.Math..Math.2}\right).& \end{array}$

[0037] By then, the charge Q.sub.1 stored on the switch capacitor circuit may be expressed as:

[00006]$\begin{array}{cc}\begin{array}{c}{Q}_1^{}=.Math.Q\left(V_{\mathrm{Cs}.Math..Math.1}^{}\right)-Q\left(V_{\mathrm{Cs}.Math..Math.1^{}}^{}\right)\\ =.Math.C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1}^{.Math..Math.2}\right)-C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1^{}}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1^{}}^{.Math..Math.2}\right)\\ =.Math.2.Math.C_{s.Math..Math.0}\left(V_{\mathrm{CMI}}-V_{O+}\right).\end{array}& \left(9\right)\end{array}$

[0038] During the voltage sampling process of the traditional sampling device, not only the charge collected after entering the sampling phase includes second-order terms relevant to the input voltage, but also the charge stored after entering the comparison phase includes second-order terms relevant to the output voltage. It can be seen according to equation (5) that the charge Q.sub.1 collected on the switch capacitor switch after entering the sampling phase does not include the second-order term relevant to the input voltage, and thus the sampling device can be avoided from generating second-order non-linearity during sampling after entering the sampling phase. In addition, it can be seen according to equation (9) that the charge Q.sub.1 stored on the switch capacitor switch after entering the comparison phase does not include the second-order term relevant to the output voltage, and thus the sampling device can be avoided from generating second-order non-linearity relevant to the output voltage after entering the comparison phase.

[0039] According to the law of conservation of charge, equations (5) and (9) are equal to each other, that is:

2C.sub.s0(V.sub.inV.sub.dd)=2C.sub.s0(V.sub.CMIV.sub.O+)(10).

It can be obtained that:

V.sub.O+=V.sub.CMIV.sub.in+V.sub.dd(11).

[0040] By then, the sampling device achieves the voltage sampling of the input signal.

[0041] It can be seen from the above embodiment that by means of providing a capacitor respectively on two paths formed by the input voltage, the input switch and the power source and making the polarities of the capacitors provided on the two paths inverse, the present disclosure can make the collected capacitance charge value merely relevant to the first-order term of the input voltage and irrelevant to the second-order term of the input voltage, and thus the second-order non-linearity generated by the traditional sampling device during voltage sampling after entering the sampling phase can be eliminated and the linearity of the sampling device can be improved. By means of providing a capacitor respectively on two paths formed by the input common-mode voltage, the input switch, the sampling switch and the power source and making the polarities of the capacitors provided on the two paths inverse, the present disclosure can make the stored capacitance charge value merely relevant to the first-order term of the output voltage and irrelevant to the second-order term of the output voltage, and thus the second-order non-linearity relevant to the output voltage and generated by the traditional sampling device when entering the comparison phase can be eliminated and the linearity of the sampling device can be improved.

[0042] In the embodiment shown in FIG. 2, although the sampling device can eliminate the second-order non-linearity generated during the voltage sampling process, the sampled voltage V.sub.O+ is still closely relevant to V.sub.dd, in which V.sub.dd can be viewed as the common-mode voltage of the traditional sampling device. Since V.sub.dd is non-adjustable, a corresponding common-mode voltage generation circuit needs to be designed respectively in order to meet different output common-mode voltage requirements. For this end, the present disclosure proposes a sampling device with adjustable output common-mode voltage, and this sampling device may comprise a plurality of switch capacitor circuit groups, for each switch capacitor circuit group, the switch capacitor circuit group comprises a preset corresponding number of switch capacitor circuits shown in FIG. 2, and for each switch capacitor circuit in the switch capacitor circuit group, a connection node connecting a lower plate of a first capacitor to an upper plate of a second capacitor is connected to a corresponding power source through a corresponding sampling switch; and a short-circuit switch is connected between the non-power source connection ends of the sampling switches respectively. There is at least one switch capacitor circuit in the above switch capacitor circuit groups, the preset number of the switch capacitor circuits included therein is greater than 1, and at least two power sources connected to the sampling switches are different.

[0043] Hereinafter, the sampling device including two switch capacitor circuits is taken as an example, referring to FIG. 3. In this embodiment, the first switch capacitor group includes the first to the m-th switch capacitor circuit shown in FIG. 2, the second switch capacitor circuit group includes the (m+1) to the N-th switch capacitor circuit shown in FIG. 2, the first switch capacitor circuit group is provided with a sampling switch S.sub.1 and a power source V.sub.dd correspondingly, the second switch capacitor circuit group is provided with a sampling switch S.sub.1 and a power source V.sub.ss respectively, and in each switch capacitor circuit of the first switch capacitor circuit group, the connection node connecting the lower plate of the first capacitor to the lower plate of the second capacitor is connected to the power source V.sub.dd through the sampling switch S.sub.1, and in each switch capacitor circuit of the second switch capacitor circuit group, the connection node connecting the lower plate of the first capacitor to the upper plate of the second capacitor is connected to the power source V.sub.ss through the sampling switch S.sub.1, a short-circuit switch S.sub.2 is provided between the non-power source connection ends of the sampling switches S.sub.1 and S.sub.1, and the power source V.sub.dd and the power source V.sub.ss are different.

[0044] In this embodiment, in the first switch capacitor circuit group, taking the first switch capacitor circuit as an example, this switch capacitor circuit may include input switches S.sub.11, S.sub.12, S.sub.11, S.sub.12 and sampling capacitors C.sub.S1 and C.sub.S1; the left end of the input switch S.sub.11 is connected to an input signal V.sub.in and the right end is connected to the upper plate of the sampling capacitor C.sub.S1; the left end of the input switch S.sub.12 is connected to an input common-mode voltage V.sub.CM and the right end is connected to the upper plate of the sampling capacitor C.sub.S1; the left end of the input switch S.sub.11 is connected to the input signal V.sub.in and the right end is connected to the lower plate of the sampling capacitor C.sub.S1; the left end of the input switch S.sub.12 is connected to the input common-mode voltage V.sub.CM and the right end is connected to the lower plate of the sampling capacitor C.sub.S1; and the lower plate of the capacitor C.sub.S1 is connected to net+ and the upper plate of the capacitor C.sub.S1 is connected to net+. Taking the m-th switch capacitor circuit as an example, this switch capacitor circuit may include input switches S.sub.m1, S.sub.m2, S.sub.m1, S.sub.m2 and sampling capacitors C.sub.Sm and C.sub.Sm; the left end of the input switch S.sub.m1 is connected to the input signal V.sub.in and the right end is connected to the upper plate of the sampling capacitor C.sub.Sm; the left end of the input switch S.sub.m2 is connected to the input common-mode voltage V.sub.CM and the right end is connected to the upper plate of the sampling capacitor C.sub.Sm; the left end of the input switch S.sub.m1 is connected to the input signal V.sub.in and the right end is connected to the lower plate of the sampling capacitor C.sub.Sm; the left end of the input switch S.sub.m2 is connected to the input common-mode voltage V.sub.CM and the right end is connected to the lower plate of the sampling capacitor C.sub.Sm; and the lower plate of the capacitor C.sub.Sm is connected to net+ and the upper plate of the capacitor C.sub.Sm is connected to net+.

[0045] In the second switch capacitor circuit group, taking the (m+1)th switch capacitor circuit as an example, this (m+1)th switch capacitor circuit may include input switches S.sub.(m+1)1, S.sub.(m+1)2, S.sub.(m+1)1, S.sub.(m+1)2 and sampling capacitors C.sub.(m+1)2 and C.sub.(m+1)2; the left end of the input switch S.sub.(m+1)1 is connected to the input signal V.sub.in and the right end is connected to the upper plate of the sampling capacitor C.sub.(m+1); the left end of the input switch C.sub.(m+1)2 is connected to the input common-mode voltage V.sub.CM and the right end is connected to the upper plate of the sampling capacitor C.sub.S(m+1); the left end of the input switch S.sub.(m+1)1 is connected to the input signal V.sub.in and the right end is connected to the lower plate of the sampling capacitor C.sub.S(m+1); the left end of the input switch S.sub.(m+1)2 is connected to the input common-mode voltage V.sub.CM and the right end is connected to the lower plate of the sampling capacitor C.sub.S(m+1); and the lower plate of the capacitor C.sub.S(m+1) is connected to net and the upper plate of the capacitor C.sub.S(m+1) is connected to net. Taking the N-th switch capacitor circuit as an example, this N-th switch capacitor circuit may include input switches S.sub.N1, S.sub.N2, S.sub.N1, S.sub.N2 and sampling capacitors C.sub.SV and C.sub.SV; the left end of the input switch S.sub.N1 is connected to the input signal V.sub.in and the right end is connected to the upper plate of the sampling capacitor C.sub.SN; the left end of the input switch S.sub.N2 is connected to the input common-mode voltage V.sub.CM and the right end is connected to the upper plate of the sampling capacitor C.sub.SN; the left end of the input switch S.sub.N1 is connected to the input signal V.sub.in and the right end is connected to the lower plate of the sampling capacitor C.sub.SN; the left end of the input switch S.sub.N2 is connected to the input common-mode voltage V.sub.CM and the right end is connected to the lower plate of the sampling capacitor C.sub.SN; and the lower plate of the capacitor C.sub.SN is connected to net- and the upper plate of the capacitor C.sub.SN is connected to net.

[0046] When the clock signal .sub.1 has a high level, the sampling device enters the sampling phase, and the switches S.sub.11, S.sub.11, S.sub.21, S.sub.21, . . . , S.sub.N1, S.sub.N1, S.sub.1 and S.sub.1 controlled by the clock signal .sub.1 are closed, and at this moment V.sub.O+ is equal to V.sub.dd and V.sub.O is equal to V.sub.ss.

[0047] In the first switch capacitor circuit,

V.sub.Cs1=V.sub.inV.sub.dd

V.sub.Cs1=V.sub.ddV.sub.in(12).

[0048] The sampling capacitance value is

C.sub.s1=C.sub.s0(1+.sub.1V.sub.cs1)

C.sub.s1=C.sub.s0(1+.sub.1V.sub.cs1)(13).

[0049] The charge collected on the sampling capacitor is:

[00007]$\begin{array}{cc}Q\left(V_{\mathrm{Cs}.Math..Math.1}\right)={}_0^{V_{\mathrm{Cs}.Math..Math.1}}.Math.C_{s.Math..Math.1}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1}^2\right)& \left(14\right)\\ Q\left(V_{\mathrm{Cs}.Math..Math.1^{}}\right)={}_0^{V_{\mathrm{Cs}.Math..Math.1^{}}}.Math.C_{s.Math..Math.1^{}}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1^{}}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1^{}}^2\right).& \end{array}$

[0050] Thus, the charge collected by the first switch capacitor circuit is:

[00008]$\begin{array}{cc}\begin{array}{c}{Q}_1=.Math.Q\left(V_{\mathrm{Cs}.Math..Math.1}\right)-Q\left(V_{\mathrm{Cs}.Math..Math.1^{}}\right)\\ =.Math.C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1}^2\right)-C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1^{}}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1^{}}^2\right)\\ =.Math.2.Math.C_{s.Math..Math.0}\left(V_{i.Math..Math.n}-V_{\mathrm{dd}}\right).\end{array}& \left(15\right)\end{array}$

[0051] Likewise, the charge collected by the i (i=1, 2, . . . , m) switch capacitor circuit is:

Q.sub.i=2C.sub.s0(V.sub.inV.sub.dd)(16).

[0052] It can seen from equations (14)-(16) that when i=1, 2, . . . , m, in the ith switch capacitor circuit, the non-linear charge

[00009]$\frac{{}_1}{2}.Math.C_{s.Math..Math.0}.Math.V_{\mathrm{Csi}}^2=\frac{{}_1}{2}.Math.{C_{s.Math..Math.0}\left(V_{i.Math..Math.n}-V_{\mathrm{dd}}\right)}^2$

of the sampling capacitor C.sub.si and the non-linear charge

[00010]$\frac{{}_1}{2}.Math.C_{s.Math..Math.0}.Math.V_{{\mathrm{Csi}}^{}}^2=\frac{{}_1}{2}.Math.{C_{s.Math..Math.0}\left(V_{\mathrm{dd}}-V_{i.Math..Math.n}\right)}^2$

of the sampling capacitor C.sub.si cancel each other, thus eliminating the sampling non-linearity.

[0053] Likewise, in the (m+1) switch capacitor circuit,

V.sub.Cs(m+1)=V.sub.inV.sub.ss

V.sub.Cs(m+1)=V.sub.ssV.sub.in(17).

[0054] The sampling capacitance value is

C.sub.s(m+1)=C.sub.s0(1+.sub.1V.sub.cs(m+1))

C.sub.s(m+1)=C.sub.s0(1+.sub.1V.sub.cs(m+1))(18).

[0055] The charge collected on the sampling capacitor is:

[00011]$\begin{array}{cc}Q\left(V_{\mathrm{Cs}\left(m+1\right)}\right)={}_0^{V_{\mathrm{Cs}\left(m+1\right)}}.Math.C_{s\left(m+1\right)}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}\left(m+1\right)}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}\left(m+1\right)}^2\right)& \left(19\right)\\ Q\left(V_{{\mathrm{Cs}\left(m+1\right)}^{}}\right)={}_0^{V_{{\mathrm{Cs}\left(m+1\right)}^{}}}.Math.C_{{s\left(m+1\right)}^{}}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{{\mathrm{Cs}\left(m+1\right)}^{}}+\frac{{}_1}{2}.Math.V_{{\mathrm{Cs}\left(m+1\right)}^{}}^2\right).& \end{array}$

[0056] Thus, the total charge collected by the (m+1) switch capacitor circuit is:

[00012]$\begin{array}{cc}\begin{array}{c}{Q}_{\left(m+1\right)}=.Math.Q\left(V_{\mathrm{Cs}\left(m+1\right)}\right)-Q\left(V_{{\mathrm{Cs}\left(m+1\right)}^{}}\right)\\ =.Math.C_{s.Math..Math.0}\left(V_{\mathrm{Cs}\left(m+1\right)}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}\left(m+1\right)}^2\right)-\\ .Math.C_{s.Math..Math.0}\left(V_{{\mathrm{Cs}\left(m+1\right)}^{}}+\frac{{}_1}{2}.Math.V_{{\mathrm{Cs}\left(m+1\right)}^{}}^2\right)\\ =.Math.2.Math.C_{s.Math..Math.0}\left(V_{i.Math..Math.n}-V_{\mathrm{ss}}\right).\end{array}& \left(20\right)\end{array}$

[0057] Likewise, the charge collected by the i (i=m+1, 2, . . . , N) switch capacitor circuit is:

Q.sub.i=2C.sub.s0(V.sub.inV.sub.ss)(21).

[0058] It can seen from equations (19)-(21) that when i=m+1, 2, . . . , N, in the ith switch capacitor circuit, the non-linear charge

[00013]$\frac{1}{2}.Math.C_{s.Math..Math.0}.Math.V_{\mathrm{Csi}}^2=\frac{{}_1}{2}.Math.{C_{s.Math..Math.0}\left(V_{i.Math..Math.n}-V_{\mathrm{ss}}\right)}^2$

of the sampling capacitor C.sub.si and the non-linear charge

[00014]$\frac{{}_1}{2}.Math.C_{s.Math..Math.0}.Math.V_{{\mathrm{Csi}}^{}}^2=\frac{{}_1}{2}.Math.{C_{s.Math..Math.0}\left(V_{\mathrm{ss}}-V_{i.Math..Math.n}\right)}^2$

of the sampling capacitor C.sub.s1 cancel each other, thus eliminating the sampling non-linearity.

[0059] The total charge of the sampling phase is:

[00015]$\begin{array}{cc}\begin{array}{c}{Q}_s=.Math.\underset{i-1}{\overset{m}{.Math.}}.Math.Q_i+\underset{i=m+1}{\overset{N}{.Math.}}.Math.Q_i\\ =.Math.{\mathrm{mQ}}_1+\left(N-m\right).Math.Q_{\left(m+1\right)}\\ =.Math.2.Math.{\mathrm{mC}}_{s.Math..Math.0}\left(V_{i.Math..Math.n}-V_{\mathrm{dd}}\right)+2.Math.\left(N-m\right).Math.C_{s.Math..Math.0}\left(V_{i.Math..Math.n}-V_{\mathrm{ss}}\right).\end{array}& \left(22\right)\end{array}$

[0060] It can be seen from the above equation that the collected total charge Q.sub.s merely contain first-order terms relevant to the input signal V.sub.in and does not contain second-order terms relevant to the input signal V.sub.in, and thus no second-order non-linearity is generated during the sampling process.

[0061] When the clock signal .sub.2 has a high level and the clock signal .sub.1 has a low level, the sampling device enters the comparison phase, the switches S.sub.12, S.sub.12, S.sub.22, S.sub.22, . . . , S.sub.N2, S.sub.N2, S.sub.2 controlled by the clock signal .sub.2 are closed, and the switches S.sub.11, S.sub.11, S.sub.21, S.sub.21, . . . , S.sub.N1, S.sub.N1, S.sub.1, S.sub.1 controlled by the clock signal .sub.1 are opened, at this moment V.sub.O+=V.sub.O=V.sub.OO.

[0062] In the first switch capacitor circuit,

V.sub.Cs1=V.sub.CMIV.sub.O+

V.sub.Cs1=V.sub.O+V.sub.CMI(23).

[0063] The sampling capacitance value is

C.sub.s1=C.sub.s0(1+.sub.1V.sub.cs1)

C.sub.s1=C.sub.s0(1+.sub.1V.sub.cs1)(24).

[0064] The charge on the sampling capacitor is:

[00016]$\begin{array}{cc}Q\left(V_{\mathrm{Cs}.Math..Math.1}^{}\right)={}_0^{V_{\mathrm{Cs}.Math..Math.1}^{}}.Math.C_{s.Math..Math.1}^{}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1}^{.Math..Math.2}\right)& \left(25\right)\\ Q\left(V_{\mathrm{Cs}.Math..Math.1^{}}^{}\right)={}_0^{V_{\mathrm{Cs}.Math..Math.1^{}}^{}}.Math.C_{s.Math..Math.1^{}}^{}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1^{}}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1^{}}^{.Math..Math.2}\right).& \end{array}$

[0065] Thus, the total charge on the first switch capacitor circuit is:

[00017]$\begin{array}{cc}\begin{array}{c}{Q}_1=.Math.Q\left(V_{\mathrm{Cs}.Math..Math.1}^{}\right)-Q\left(V_{\mathrm{Cs}.Math..Math.1^{}}^{}\right)\\ =.Math.C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1}^{.Math..Math.2}\right)-C_{s.Math..Math.0}\left(V_{\mathrm{Cs}.Math..Math.1^{}}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}.Math..Math.1^{}}^{.Math..Math.2}\right)\\ =.Math.2.Math.C_{s.Math..Math.0}\left(V_{\mathrm{CMI}}-V_{O+}\right).\end{array}& \left(26\right)\end{array}$

[0066] Likewise, in the (m+1) switch capacitor,

V.sub.Cs(m+1)=V.sub.CMIV.sub.O

V.sub.Cs(m+1)=V.sub.OV.sub.CMI(27).

[0067] The sampling capacitance value is

C.sub.s(m+1)=C.sub.s0(1+.sub.1V.sub.cs(m+1))

C.sub.s(m+1)=C.sub.s0(1+.sub.1V.sub.cs(m+1))(27).

[0068] The charge collected on the sampling capacitor is:

[00018]$\begin{array}{cc}Q\left(V_{\mathrm{Cs}\left(m+1\right)}^{}\right)={}_0^{V_{\mathrm{Cs}\left(m+1\right)}^{}}.Math.C_{s\left(m+1\right)}^{}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{\mathrm{Cs}\left(m+1\right)}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}\left(m+1\right)}^{.Math..Math.2}\right)& \left(29\right)\\ Q\left(V_{{\mathrm{Cs}\left(m+1\right)}^{}}^{}\right)={}_0^{V_{{\mathrm{Cs}\left(m+1\right)}^{}}^{}}.Math.C_{{s\left(m+1\right)}^{}}^{}.Math.\mathrm{dV}=C_{s.Math..Math.0}\left(V_{{\mathrm{Cs}\left(m+1\right)}^{}}^{}+\frac{{}_1}{2}.Math.V_{{\mathrm{Cs}\left(m+1\right)}^{}}^{.Math..Math.2}\right).& \end{array}$

[0069] Thus, the total charge collected by the (m+1) switch capacitor circuit is:

[00019]$\begin{array}{cc}\begin{array}{c}{Q}_{\left(m+1\right)}^{}=.Math.Q\left(V_{\mathrm{Cs}\left(m+1\right)}^{}\right)-Q\left(V_{{\mathrm{Cs}\left(m+1\right)}^{}}^{}\right)\\ =.Math.C_{s.Math..Math.0}\left(V_{\mathrm{Cs}\left(m+1\right)}^{}+\frac{{}_1}{2}.Math.V_{\mathrm{Cs}\left(m+1\right)}^{.Math..Math.2}\right)-\\ .Math.C_{s.Math..Math.0}\left(V_{{\mathrm{Cs}\left(m+1\right)}^{}}^{}+\frac{{}_1}{2}.Math.V_{{\mathrm{Cs}\left(m+1\right)}^{}}^{.Math..Math.2}\right)\\ =.Math.2.Math.C_{s.Math..Math.0}\left(V_{\mathrm{CMI}}-V_{O-}\right).\end{array}& \left(30\right)\end{array}$

[0070] The total charge of the comparison phase is:

[00020]$\begin{array}{cc}\begin{array}{c}{Q}_c=.Math.\underset{i=1}{\overset{m}{.Math.}}.Math.Q_i^{}+\underset{i=m+1}{\overset{N}{.Math.}}.Math.Q_i^{}\\ =.Math.{\mathrm{mQ}}_1+\left(N-m\right).Math.Q_{\left(m+1\right)}\\ =.Math.2.Math.{\mathrm{mC}}_{s.Math..Math.0}\left(V_{\mathrm{CMI}}-V_{O+}\right)+2.Math.\left(N-m\right).Math.C_{s.Math..Math.0}\left(V_{\mathrm{CMI}}-V_{O-}\right)\\ =.Math.2.Math.{\mathrm{NC}}_{s.Math..Math.0}\left(V_{\mathrm{CMI}}-V_{\mathrm{OO}}\right).\end{array}& \left(31\right)\end{array}$

[0071] According to the law of conservation of charge

Q.sub.s=Q.sub.c(32).

[0072] The input signal can be expressed as:

V.sub.in=v.sub.in+V.sub.CMI(33).

[0073] v.sub.in is an alternating component of V.sub.in, V.sub.CMI is the input common-mode voltage, and it can be obtained from (22) and (31)-(33) that

[00021]$\begin{array}{cc}{V}_O=-v_{i.Math..Math.n}+\left[\frac{m}{N}.Math.\left(V_{\mathrm{dd}}-V_{\mathrm{ss}}\right)+V_{\mathrm{ss}}\right].& \left(34\right)\end{array}$

[0074] It can be seen that a direct component of the output signal, that is the output common-mode voltage is

[00022]$\begin{array}{cc}{V}_{\mathrm{CMO\_T}}=\frac{m}{N}.Math.\left(V_{\mathrm{dd}}-V_{\mathrm{ss}}\right)+V_{\mathrm{ss}}.& \left(35\right)\end{array}$

[0075] It can be seen from equation (35) that when m=0, the output common-mode voltage is V.sub.ss, and when m=N, the output common-mode voltage is V.sub.dd, and thus it can be seen that the adjustable range of the output common-mode voltage reaches the entire power source domain, and a flexible output common-mode voltage can be obtained by changing the value of m.

[0076] It can be seen from the above embodiment that, in the present disclosure, a plurality of switch capacitor circuit groups are designed, each switch capacitor circuit group includes a preset corresponding number of switch capacitor circuits, and each switch capacitor circuit is connected to a corresponding power source, thus an output common-mode voltage of the sampling device is adjustable. Compared to the fact that the traditional sampling device needs to design an output common-mode voltage generation circuit, in the sampling device proposed in the present disclosure, the switch capacitor circuit group thereof has a function of generating an output common-mode voltage, and thus there is no need to design an output common-mode voltage generation circuit. Secondly, the traditional sampling device needing to design an output common-mode voltage generation circuit causes the power consumption of the circuit to increase; however, the sampling device proposed in the present disclosure need not an output common-mode voltage generation circuit, which greatly reduces the layout area and power consumption of the sampling circuit. In addition, the output common-mode voltage of the traditional sampling device is non-adjustable; however, the sampling device proposed in the present disclosure can achieve the purpose of adjusting the output common-mode voltage by adjusting the value of m, and the adjustable range of the output common-mode voltage is from V.sub.ss to V.sub.dd, achieving the entire power source domain range with stronger circuit universality.

[0077] After considering the description and practicing the present disclosure disclosed herein, other implementations of the present disclosure may easily occur to those skilled in the art. The present application is intended to cover any modifications, uses or adaptive changes of the present disclosure, and these modifications, uses or adaptive changes follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field which is not disclosed in the present disclosure. The description and embodiments shall be deemed merely illustrative, and the real scope and spirit of the present disclosure are set forth in the following claims.

[0078] It shall be understood that the present disclosure is not limited to the precise structure described above and illustrated in the drawings and can be modified and varied without departing the scope thereof. The scope of the present disclosure is merely limited by the appended claims.