Front-side type image sensors

Abstract

A front-side type image sensor may include a substrate successively including: a P− type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.

Claims

1. A front-side type image sensor, comprising: a substrate including a P− type doped semiconducting support substrate, a P+ type doped semiconducting epitaxial layer over the support substrate, an electrically insulating layer over the P+ type doped semiconducting epitaxial layer, and a semiconducting active layer over the electrically insulating layer; and a matrix array of photodiodes in the active layer of the substrate.

2. The sensor of claim 1, wherein the epitaxial layer and the support substrate comprise the same semiconductor material.

3. The sensor of claim 2, wherein the support substrate and the epitaxial layer comprise silicon.

4. The sensor of claim 3, wherein the active layer comprises silicon.

5. The sensor of claim 4, wherein a thickness of the electrically insulating layer is between 10 and 50 nm.

6. The sensor of claim 5, wherein the thickness of the epitaxial layer is between 0.1 and 3 μm.

7. The sensor of claim 1, wherein the active layer comprises silicon.

8. The sensor of claim 1, wherein a thickness of the electrically insulating layer is between 10 and 50 nm.

9. The sensor of claim 1, wherein a thickness of the epitaxial layer is between 0.1 and 3 μm.

10. The sensor of claim 9, wherein the thickness of the epitaxial layer is between 0.1 and 1 μm.

11. The sensor of claim 1, wherein a thickness of the support substrate is greater than a thickness of the epitaxial layer.

12. The sensor of claim 1, wherein the support substrate comprises silicon and the P+ type doped semiconducting epitaxial layer comprises P+ type doped SiGe.

13. The sensor of claim 1, wherein the substrate is disc-shaped, wherein the substrate comprises a chamfer at a periphery of the substrate, and wherein a surface area of the P+ type doped semiconducting epitaxial layer at the periphery of the substrate is 9 cm.sup.2 or less.

14. The sensor of claim 1, wherein the substrate is free of any barrier layers between the P+ type doped semiconducting epitaxial layer and the support substrate on one side and between the P+ type doped semiconducting epitaxial layer and the electrically insulating layer on an opposite side.

15. The sensor of claim 1, wherein the P− type doped semiconducting support substrate and the P+ type doped semiconducting epitaxial layer are doped with boron.

16. A front-side type image sensor, comprising: a support substrate comprising a semiconductor material, the semiconductor material of the support substrate doped with a P type dopant at a concentration of 10.sup.15 atoms/cm.sup.3 or less; an epitaxial layer located adjacent to the support substrate, the epitaxial layer comprising a semiconductor material doped with a P type dopant at a concentration greater than 10.sup.15 atoms/cm.sup.3; an electrically insulating layer located on a side of the epitaxial layer opposite the support substrate; and an active layer comprising a semiconductor material located on a side of the electrically insulating material opposite the epitaxial layer, the active layer comprising an array of photodiodes.

17. The sensor of claim 16, wherein the concentration of the P type dopant in the support substrate is between 10.sup.14 and 10.sup.15 atoms/cm.sup.3.

18. The sensor of claim 16, wherein the concentration of the P type dopant in the epitaxial layer is less than 10.sup.19 atoms/cm.sup.3 and greater than 10.sup.15 atoms/cm.sup.3.

19. The sensor of claim 16, wherein the sensor is disc-shaped, wherein the sensor comprises a chamfer at a periphery of the sensor, and wherein a surface area of the P+ type doped semiconducting epitaxial layer at the periphery of the sensor is 9 cm.sup.2 or less.

20. The sensor of claim 16, wherein the substrate is free of any barrier layers between the P+ type doped semiconducting epitaxial layer and the support substrate on one side and between the P+ type doped semiconducting epitaxial layer and the electrically insulating layer on an opposite side.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further characteristics and advantages of the disclosure will appear upon reading the detailed description that follows, in reference to the appended drawings in which:

(2) FIG. 1 is a cross-sectional view of a SOI substrate for a front-side image sensor as described in U.S. Patent Application Publication No. 2016/0118431;

(3) FIG. 2 is a cross-sectional view of a substrate in accordance with one embodiment of the disclosure;

(4) FIGS. 3A to 3C illustrate different steps of the method for manufacturing a substrate according to one embodiment of the disclosure;

(5) FIG. 4 is a cross-sectional view of a pixel of a “front-side” type image sensor comprising a substrate according to one embodiment of the disclosure;

(6) FIG. 5 illustrates simulations of the concentration of boron atoms in a substrate according to one embodiment of the disclosure, before applying a heat treatment (curve a) and after applying two usual heat treatments (curves b and c).

(7) For the sake of legibility of the figures, the different layers are not necessarily drawn to scale.

DETAILED DESCRIPTION

(8) FIG. 2 illustrates a substrate for a front-side image sensor according to one embodiment of the disclosure.

(9) The substrate successively comprises, from its back side to its front side, a P− type doped semiconducting support substrate 1, a P+ type doped semiconducting epitaxial layer 4, an electrically insulating layer 2 and a semiconducting layer 3 called an active layer.

(10) The active layer 3 is intended to receive a matrix array of photodiodes (not represented) enabling images to be sensed. Advantageously but not in a limiting way, active layer 3 can be made of silicon. In some embodiments, the active layer 3 can be slightly doped.

(11) The support substrate 1 is generally obtained by cutting a P− doped single crystal ingot. Advantageously, the support substrate 1 is made of silicon.

(12) The P+ type doped semiconducting epitaxial layer 4 is formed on the support substrate 1 by epitaxy. In order to minimize defects in the epitaxial layer 4, the lattice parameter of the epitaxial layer 4 is close to the lattice parameter of the support substrate 1. Thus, the epitaxial layer is advantageously of the same material as the support substrate 1 (for example, of P+ doped silicon if the support substrate 1 is of P− doped silicon) or of another material (for example of P+ doped SiGe if the support substrate 1 is of P− doped silicon). Of course, these example embodiments are not limiting.

(13) The thickness of the epitaxial layer 4 is advantageously between 0.1 and 3 μm, preferably between 0.1 and 1 μm.

(14) The electrically insulating layer 2 sandwiched between the epitaxial layer 4 and the active layer provides an electrical insulation between the layers.

(15) According to one preferred embodiment, the electrically insulating layer 2 is made of silicon oxide, but any other dielectric material could be suitable.

(16) The thickness of the electrically insulating layer 2 is advantageously between 10 and 50 nm. Thus, as will be seen, it is possible to electrically bias the P+ doped layer at a voltage lower than that of the active layer 3, in order to cause build-up of majority carriers of the active layer at the interface between the active layer 3 and the electrically insulating layer 2 of silicon oxide.

(17) In contrast to the known substrate illustrated in FIG. 1, wherein the part located at the rear of the layer of silicon oxide is fully P+ doped, the present disclosure provides a structure formed of two layers having different doping levels, that is the P+ doped epitaxial layer 4, which has a limited thickness, immediately at the rear of the electrically insulating layer 2, and the support substrate 1, which is substantially thicker than the epitaxial layer 4, at the rear of the epitaxial layer 4.

(18) This two-part structure avoids, or at least reduces the contamination phenomenon resulting from diffusion of doping species off the substrate as previously discussed herein.

(19) Indeed, the exposed area (that is in contact with the environment of the substrate) of the P+ doped material is substantially reduced in the embodiments of the present disclosure with respect to the configuration of the prior art. By way of example: for a P+ doped support substrate of 30 cm diameter, 775 μm thickness and a chamfer of 1 mm width (corresponding to a substrate according to the prior art), the exposed area is equal to the sum of the area of the back side of the substrate, the side area of the substrate and the chamfer area, that is:
Π*15.sup.2+2*Π*15*0.0775+Π*(15.sup.2−14.9.sup.2)=724 cm.sup.2 for a P+ doped epitaxial layer of 1 μm thickness formed on a P− doped substrate of 30 cm diameter and having a chamfer of 1 mm width (corresponding to one embodiment of the present disclosure), the exposed area is equal to the sum of the side area of the layer and the chamfer area, that is:
2*Π*15*0.0001+Π*(15.sup.2−14.9.sup.2)=9 cm.sup.2.

(20) It is noted that since the substrates are not perfectly cylindrical but have a peripheral chamfer, the manufacture of a SOI substrate by layer transfer (for example by the SMART CUT® method described below) results in transferring a layer of a donor substrate onto the center part of the receiver substrate except for the chamfer thereof. In other words, the receiver substrate is not covered with the layer transferred into the chamfer region. To avoid complicating the figures, the chamfer is not illustrated in the figures.

(21) In the example set out above, the exposed area of the P+ material is thus close to 80 to 100 times lower in the substrate according to the present disclosure than in the known substrate.

(22) As a result, the doping species contained in the epitaxial layer 4 are likely to generate a much lower contamination than a bulk support substrate.

(23) According to one embodiment not illustrated, it would be possible to further limit the diffusion of the doping species outwardly of the substrate by forming a barrier layer about the P+ doped epitaxial layer. Such a barrier layer can be in particular formed of the same material as the support substrate 1 or a material having a lattice parameter equivalent to that of the epitaxial layer 4 but without doping. However, the formation of such a barrier layer requires additional manufacturing steps which increase the period of time and complexity of the manufacturing method (for example lithography and etching step at the edge, including the chamfer zone or not).

(24) A method for manufacturing a substrate for a front-side type image sensor according to the disclosure, using in particular the well-known SMART CUT® method will now be described in reference to FIGS. 3A to 3C.

(25) In reference to FIG. 3A, the P+ doped support substrate 1 is provided, and the P+ doped epitaxial layer 4 is epitaxially grown until the desired thickness is achieved. A receiving structure is thus formed for transferring the active layer. The thickness of the epitaxial layer 4 depends on the doping level thereof: the higher the doping level (up to 10.sup.19 at/cm.sup.3), the lower the thickness of this layer should be kept to avoid too strong a dissemination of the doping species off the substrate. The barrier layer mentioned before can contribute to keeping a predetermined thickness of the epitaxial layer 4 depending on the doping level contemplated as well as the heat treatments subsequently contemplated.

(26) On the other hand, in reference to FIG. 3B, a donor substrate 30 comprising a superficial layer 31 of semiconductor material intended to form the active layer 3 of the SOI substrate is provided. The superficial layer is advantageously delimited by an embrittlement zone 32. According to one embodiment, the embrittlement zone 32 is formed by implanting atomic species, such as hydrogen and/or helium for example. Alternatively, the embrittlement zone can be a porous zone.

(27) The superficial layer 31 of the donor substrate advantageously comprises an electrically insulating layer intended to form the buried electrically insulating layer 2 of the SOI substrate. This electrically insulating layer 2 can be an oxide of the material of the superficial layer 31. Optionally, such an electrically insulating layer can be present on the epitaxial layer 4 of the receiving structure, or even both on the donor substrate and the receiving structure.

(28) In reference to FIG. 3C, the donor substrate is bonded to the receiving structure, the electrically insulating layer(s) being at the bonding interface.

(29) The applicant has checked that, although the formation of the epitaxial layer on the support substrate is likely to induce deformation of planarity of the receiving structure, the bonding quality between the donor substrate and the receiving structure remains suitable.

(30) Then, the donor substrate 30 is thinned so as to transfer the superficial semiconducting layer 31 onto the support substrate 1. According to the SMART CUT® method, this thinning comprises detaching the donor substrate 30 along the embrittlement zone 32. After possible finishing steps, for example annealing, polishing and/or cleaning steps, the substrate illustrated in FIG. 2 is obtained.

(31) According to one alternative (not represented), the donor substrate does not comprise any embrittlement zone and the transfer of the superficial layer onto the donor substrate is made by material removal by means of polishing the donor substrate through the face opposite to the bonding interface.

(32) A matrix array of photodiodes is then made in the active layer 3. The manufacturing process of such an array of photodiodes is known by the skilled person and will thus not be described in more detail here.

(33) FIG. 4 illustrates a part of a front-side type image sensor in accordance with the disclosure. Only a part of the sensor corresponding to a pixel is represented in this figure, the pixel being electrically insulated from the other pixels formed in the active layer 3 by insulation trenches 7.

(34) An N− doped region 33 is formed under the surface of the front side of the active layer 3. This N− doped region forms a photodiode with the P− doped active layer 3. A region 34 formed between the N− doped region 33 and the front side of the active layer 3 has advantageously a doping level N higher than that of the N− doped region 33 in order to passivate the interface. A passivation layer 6 is formed on the active layer 3 and can encapsulate elements enabling the pixel to be electrically controlled.

(35) Optionally, other layers, such as filters, can be formed on the passivation layer 6, but they are not represented in FIG. 4.

(36) The structure of the image sensor as such and its manufacturing method are known to those skilled in the art and thus will not be described in further detail.

(37) When the electrically insulating layer 2 is thin enough (in the order of 10 to 50 nm), thereby it plays the role of the dielectric element of a capacitor formed by the layers 3 and 4. Upon operating the image sensor, the active layer 3 is biased at an electric voltage which generally corresponds to the ground. The P+ doped epitaxial layer can advantageously be biased at a voltage V4 lower than the voltage of the active layer 3, V4 thus being negative. According to the same principle as that explained in U.S. Patent Application Publication Number 2016/0118431, the application of the negative voltage V4 induces build-up, at the interface between the electrically insulating layer 2 and the active layer 3, of majority carriers (holes) of the active layer 3. This charge build-up creates a positive electrical voltage V3 in the active layer 3 at the interface with the electrically insulating layer 2. The capacitor is thus subjected to a voltage difference V3-V4. The voltage V4 to be applied depends on the thickness of the electrically insulating layer 2.

(38) FIG. 5 illustrates simulations of the concentration of boron atoms in a substrate according to one embodiment of the disclosure, before applying a heat treatment (curve a) and after applying two usual heat treatments within the scope of the manufacture of one image sensor (curves b and c).

(39) The abscissa axis indicates the depth (in μm) in the SOI substrate, the origin corresponding to the front side of the active layer (the marks 1 to 4 correspond to those of FIGS. 2 to 3C). The ordinate axis indicates the concentration (in atoms/cm.sup.3) of boron atoms.

(40) Curve a has the shape of a crenel which shows that the high boron concentration is limited to the epitaxial layer 4.

(41) Curves b and c correspond to the same SOI substrate as that of curve a, but after applying two different heat treatments, that of curve c representing a heat budget higher than that of curve b. Both these curves show a light diffusion of boron atoms from epitaxial layer 4 to the underlying support substrate 1, but which remains limited. Consequently, the doping level of the epitaxial layer, and its effect on reducing the dark current, are maintained.

(42) An additional barrier layer of the same type as mentioned before can be located between the support substrate 1 and the epitaxial layer 4 to avoid diffusion as mentioned above.

(43) Another embodiment can include an epitaxial layer 4 having a predetermined doping gradient, this doping increasing to the front side in contact with the electrically insulating layer 2. Under the influence of heat treatment, the diffusion inside the epitaxial layer 4 having this gradient enables a sufficient average doping to be maintained for the application searched for.