Current mirror circuits

Abstract

A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

Claims

1. A circuit comprising: a first transistor comprising a first terminal, a second terminal and a third terminal, the first terminal of the first transistor comprising an input terminal of the circuit, the second terminal of the first transistor coupled to a power supply bus, the first transistor conducting a first current; and a second transistor comprising a first terminal, a second terminal and a third terminal, the first terminal of the second transistor comprising an output terminal of the circuit, the second terminal of the second transistor coupled to the power supply bus, the third terminal of the second transistor coupled to the third terminal of the first transistor, wherein the second transistor conducts a second current proportional to the first current substantially independent of resistance in the power supply bus between the first transistor and the second transistor.

2. The circuit of claim 1, wherein the first terminal of the first transistor is coupled to the third terminal of the first transistor.

3. The circuit of claim 1, wherein the second current substantially equals the first current.

4. The circuit of claim 1, wherein a voltage at the second terminal of the second transistor substantially equals a voltage at the second terminal of the first transistor independent of distance between the first transistor and the second transistor.

5. The circuit of claim 1, wherein: the second terminal of the first transistor is coupled to a first location on the power supply bus; and the second terminal of the second transistor is coupled to a second location different from the first location on the power supply bus.

6. The circuit of claim 5, wherein a first voltage at the first location of the power supply bus differs from a second voltage at the second location of the power supply bus.

7. The circuit of claim 1, further comprising: a third transistor comprising a first terminal, a second terminal and a third terminal, the first terminal of the third transistor coupled to the power supply bus, the second terminal of the third transistor coupled to the second terminal of the first transistor conducting the first current; and a fourth transistor comprising a first terminal, a second terminal and a third terminal, the first terminal of the fourth transistor coupled to the power supply bus, the second terminal of the fourth transistor coupled to the second terminal of the second transistor, the third terminal of the third transistor coupled to the third terminal of the fourth transistor.

8. The circuit of claim 7, wherein the first terminal of the third transistor is coupled to the third terminal of the third transistor.

9. The circuit of claim 7, wherein the first transistor and the second transistor comprise a first conductivity type and the third transistor and the fourth transistor comprise a second conductivity type different from the first conductivity type.

10. The circuit of claim 1, wherein the power supply bus comprises any of a ground bus, a positive power supply bus, or a negative power supply bus.

11. The circuit of claim 1 comprising a current mirror circuit.

12. A current mirror circuit comprising: a diode-connected first transistor of a first conductivity type coupled to a second transistor of the first conductivity type, a control terminal of the first transistor coupled to a control terminal of the second transistor; and a diode-connected third transistor of a second conductivity type different from the first conductivity type coupled to the first diode-connected transistor and to a fourth transistor of the second conductivity type, the fourth transistor coupled to the second transistor, a control terminal of the third transistor coupled to a control terminal of the fourth transistor, wherein the first transistor and the third transistor each conduct a first current and the second transistor and the fourth transistor each conduct a second current substantially proportional to the first current.

13. The current mirror circuit of claim 12, wherein the second current is substantially proportional to the first current independent of distance between the first transistor and the second transistor and between the third transistor and the fourth transistor.

14. The current mirror circuit of claim 12, wherein the second current substantially equals the first current.

15. The current mirror circuit of claim 12, wherein the third transistor and the fourth transistor are each coupled to a power supply bus that comprises a voltage difference along a length of the power supply bus between the third transistor and the fourth transistor.

16. The current mirror circuit of claim 15, wherein the power supply bus comprises any of a ground bus, a positive power supply bus, or a negative power supply bus.

17. An apparatus comprising: a memory die comprising: a current mirror driver circuit coupled to a power supply bus and comprising a first driver device configured to provide a first bias voltage, and a second driver device configured to provide a second bias voltage different from the first bias voltage, the first driver device and the second driver device conducting a first current; and a memory array comprising a plurality of sub-arrays, each sub array comprising a corresponding first mirror device coupled to the first bias voltage, and a corresponding second mirror device coupled to the second bias voltage and to the power supply bus, the first mirror device and second mirror device conducting a corresponding second current, wherein the corresponding second currents of each of the plurality of sub-arrays are substantially equal independent of resistance in the power supply bus.

18. The apparatus of claim 17, wherein corresponding second currents each are substantially proportional to the first current.

19. The apparatus of claim 17, wherein the first driver device comprises a first conductivity type, and the second driver device comprises a second conductivity type different from the first conductivity type.

20. The apparatus of claim 17, wherein the power supply bus comprises any of a ground bus, a positive power supply bus, or a negative power supply bus.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Like-numbered elements refer to common components in the different figures.

(2) FIG. 1 is a block diagram depicting one embodiment of a memory system.

(3) FIG. 2 is a block diagram of one embodiment of a memory die.

(4) FIG. 3 is a perspective view of a portion of one embodiment of a three dimensional memory structure.

(5) FIG. 4A is a diagram of a conventional current mirror circuit.

(6) FIG. 4B is a diagram of another conventional current mirror circuit.

(7) FIG. 5A is a diagram of an embodiment of a current mirror circuit.

(8) FIG. 5B is a diagram of another embodiment of a current mirror circuit.

(9) FIG. 6 is a diagram of an embodiment of a memory die.

DETAILED DESCRIPTION

(10) Technology is described for current mirror circuits that may be used to generate mirror currents in semiconductor integrated circuits, such as semiconductor memory.

(11) Semiconductor memory may include non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory).

(12) In semiconductor memory, current mirror circuits are often used to generate currents to read and write a selected memory cell. Semiconductor memory often includes a memory array that is divided into sub-arrays, some memory chips having thousands of sub-arrays, each with its own read and write circuitry and current mirror devices.

(13) In many implementations, a reference current generator and current mirror driver device are located outside the memory array. The driver device generates a bias voltage that is distributed to mirror devices in each of the memory sub-arrays. This results in a large and variable distance between the driver device and the numerous mirror devices. If the driver device and the mirror devices share a common power supply bus, voltage differences along the power supply bus due to parasitic resistance in the power supply bus may result in errors in the generated mirror currents.

(14) As a result, currents generated by the mirror devices in the various memory sub-arrays may have unacceptably large errors from desired current values. Technology is described to provide current mirror circuits that generate mirror currents that are proportional to a reference current substantially independent of voltage differences along the power supply bus between the driver device and the mirror device. In addition, the described current mirror circuits generate mirror currents that are proportional to a reference current substantially independent of distance between the driver device and the mirror device.

(15) FIG. 1 is a block diagram of an embodiment of a memory system 100 that implements the described technology. In an embodiment, memory system 100 is an SSD. Memory system 100 also can be a memory card, USB drive or other type of storage system. The proposed technology is not limited to any one type of memory system. Memory system 100 is connected to host 102, which can be a computer, server, electronic device (e.g., smart phone, tablet or other mobile device), appliance, or another apparatus that uses memory and has data processing capabilities. In some embodiments, host 102 is separate from, but connected to, memory system 100. In other embodiments, memory system 100 is embedded within host 102.

(16) The components of memory system 100 depicted in FIG. 1 are electrical circuits. Memory system 100 includes a controller 104 connected to one or more memory die 106 and local high speed volatile memory 108 (e.g., DRAM). The one or more memory die 106 each include a plurality of non-volatile memory cells. More information about the structure of each memory die 106 is provided below. Local high speed volatile memory 108 is used by controller 104 to perform certain functions.

(17) Controller 104 includes a host interface 110 that is connected to and in communication with host 102. In one embodiment, host interface 110 provides a PCIe interface. Other interfaces can also be used, such as SCSI, SATA, etc. Host interface 110 is also connected to a network-on-chip (NOC) 112, which is a communication subsystem on an integrated circuit. In other embodiments, NOC 112 can be replaced by a bus. A processor 114, an ECC engine 116, a memory interface 118, a DRAM controller 120 and hardware accelerators 122 are connected to and in communication with NOC 112.

(18) Processor 114 performs the various controller memory operations, such as programming, erasing, reading, as well as memory management processes. In an embodiment, processor 114 is programmed by firmware. In other embodiments, processor 114 is a custom and dedicated hardware circuit without any software. In an embodiment, processor 114 also implements a translation module, as a software/firmware process or as a dedicated hardware circuit.

(19) In an embodiment, ECC engine 116 performs error correction. For example, ECC engine 116 performs data encoding and decoding, as per the implemented ECC technique. In one embodiment, ECC engine 116 is an electrical circuit programmed by software. For example, ECC engine 116 can be a processor that can be programmed. In other embodiments, ECC engine 116 is a custom and dedicated hardware circuit without any software. In another embodiment, the function of ECC engine 116 is implemented by processor 114.

(20) In an embodiment, memory interface 118 communicates with one or more memory die 106. In an embodiment, memory interface 118 provides a Toggle Mode interface. Other interfaces also can be used. In some example implementations, memory interface 118 (or another portion of controller 104) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory die.

(21) In an embodiment, DRAM controller 120 is used to operate and communicate with local high speed volatile memory 108 (e.g., DRAM). In other embodiments, local high speed volatile memory 108 can be SRAM or another type of volatile memory.

(22) FIG. 2 is a functional block diagram of one embodiment of a memory die 200. Each of the one or more memory die 106 of FIG. 1 can be implemented as memory die 200 of FIG. 2. The components depicted in FIG. 2 are electrical circuits. In an embodiment, each memory die 200 includes a memory structure 202, control circuitry 204, and read/write circuits 206. Memory structure 202 is addressable by word lines via a row decoder 208 and by bit lines via a column decoder 210.

(23) In an embodiment, read/write circuits 206 include multiple sense blocks 212 including SB1, SB2, . . . , SBp (sensing circuitry) and allow a page (or multiple pages) of data in multiple memory cells to be read or programmed (written) in parallel. In an embodiment, each sense block 212 includes a sense amplifier and a set of latches connected to the bit line. The latches store data to be written and/or data that has been read. In an embodiment, the sense amplifier of each sense block 212 includes bit line drivers. In an embodiment, commands and data are transferred between controller 104 and memory die 200 via lines 214. In an embodiment, memory die 200 includes a set of input and/or output (I/O) pins that connect to lines 214.

(24) In an embodiment, control circuitry 204 cooperates with read/write circuits 206 to perform memory operations (e.g., write, read, erase, and others) on memory structure 202. In an embodiment, control circuitry 204 includes a state machine 216, an on-chip address decoder 218, and a power control module 220.

(25) In an embodiment, state machine 216 provides die-level control of memory operations. In an embodiment, state machine 216 is programmable by software. In other embodiments, state machine 216 does not use software and is completely implemented in hardware (e.g., electrical circuits). In some embodiments, state machine 216 can be replaced by a microcontroller or microprocessor. In an embodiment, control circuitry 204 includes buffers such as registers, ROM fuses and other storage devices for storing default values such as base voltages and other parameters.

(26) On-chip address decoder 218 provides an address interface between addresses used by controller 104 to the hardware address used by row decoder 208 and column decoder 210. Power control module 220 controls the power and voltages supplied to the word lines and bit lines during memory operations. Power control module 220 may include charge pumps for creating voltages.

(27) Power control module 220 also may include current mirror driver circuits for creating current mirror bias voltages provided to other circuitry on memory die 200. For example, power control module 220 may include current mirror driver circuits that provide current mirror bias voltages to current mirror devices in one or more of memory structure 202, control circuitry 204, read/write circuits 206, row decoder 208, column decoder 210, sense blocks 212, and/or other circuits on memory die 200.

(28) For purposes of this document, control circuitry 204, read/write circuits 206, row decoder 208 and column decoder 210 comprise a control circuit for memory structure 202. In other embodiments, other circuits that support and operate on memory structure 202 can be referred to as a control circuit. For example, in some embodiments, controller 104 can operate as the control circuit or can be part of the control circuit. The control circuit also can be implemented as a microprocessor or other type of processor that is hardwired or programmed to perform the functions described herein.

(29) In an embodiment, memory structure 202 is a three dimensional memory array of non-volatile memory cells. In an embodiment, memory structure 202 is a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate, such as a wafer. Memory structure 202 may be any type of non-volatile memory that is formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells of memory structure 202 include vertical NAND strings with charge-trapping material such as described. A NAND string includes memory cells connected by a channel.

(30) In another embodiment, memory structure 202 includes a two dimensional memory array of non-volatile memory cells. In an example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR-type flash memory) also can be used.

(31) In still another embodiment, memory structure 202 includes a memory array (two dimensional or three dimensional) that includes multiple memory sub-arrays, with each memory sub-array including multiple non-volatile memory cells.

(32) The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory cell technologies can be used to form memory structure 202. No particular non-volatile memory technology is required for purposes of the new technology described herein.

(33) Other examples of suitable technologies for memory cells of the memory structure 202 include ReRAM memories, magnetoresistive memory (MRAM), phase change memory (PCM), and the like. Examples of suitable technologies for architectures of memory structure 202 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.

(34) One example of a cross point memory includes reversible resistance-switching elements arranged in cross point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element also may be referred to as a programmable metallization cell.

(35) A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes.

(36) MRAM stores data using magnetic storage elements. The magnetic storage elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created.

(37) Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTeSb.sub.2Te.sub.3 super lattice to achieve non-thermal phase changes by simply changing the coordination state of Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited from programming by blocking the memory cells from receiving the light.

(38) A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but covers many relevant memory structures within the scope of the technology as described herein and as understood by one of ordinary skill in the art.

(39) FIG. 3 is a perspective view of a portion of an embodiment of a three dimensional memory array that includes memory structure 202. In an embodiment, memory structure 202 includes multiple non-volatile memory cells. For example, FIG. 3 shows a portion of one block of memory cells. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W.

(40) The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108-300 alternating dielectric layers and conductive layers. One example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers and 110 dielectric layers. More or less than 108-300 layers also can be used. In an embodiment, the alternating dielectric layers and conductive layers are divided into four regions by local interconnects LI. FIG. 3 shows two regions and two local interconnects LI.

(41) A source line layer SL is below the alternating dielectric layers and word line layers. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in FIG. 3 the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers.

(42) In an embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells (also referred to as a memory column). In an embodiment, each memory cell can store one or more bits of data. In an embodiment, each memory hole MH is associated with and coupled to a corresponding one of bit lines BL. In an embodiment, each bit line BL is coupled to one or more memory holes MH.

(43) FIG. 4A depicts a diagram of a conventional current mirror circuit 400a, which has an input terminal in.sub.1, an output terminal out.sub.1, a first transistor M.sub.1 and a second transistor M.sub.2. In the depicted example, first transistor M.sub.1 and second transistor M.sub.2 are each n-channel transistors. First transistor M.sub.1 has a first (e.g., drain) terminal d.sub.1, a second (e.g., source) terminal s.sub.1 and a third (e.g., control or gate) terminal g.sub.1. Second transistor M.sub.2 has a first (e.g., drain) terminal d.sub.2, a second (e.g., source) terminal s.sub.2 and a third (e.g., control or gate) terminal D.

(44) For convenience, first terminal d.sub.1, second terminal s.sub.1 and third terminal g.sub.1 of first transistor M.sub.1 will also be referred to herein as drain d.sub.1, source s.sub.1 and gate g.sub.1, respectively, of first transistor M.sub.1. Likewise, first terminal d.sub.2, second terminal s.sub.2 and third terminal g.sub.2 of second transistor M.sub.2 will also be referred to herein as drain d.sub.2, source s.sub.2 and gate g.sub.2, respectively, of second transistor M.sub.2.

(45) Drain d.sub.1 of first transistor M.sub.1 is coupled to input terminal in.sub.1, gate g.sub.1 of first transistor M.sub.1, and gate g.sub.2 of second transistor M.sub.2. Drain d.sub.2 of second transistor M.sub.2 is coupled to output terminal outs. Source s.sub.1 of first transistor M.sub.1 and source s.sub.2 of second transistor M.sub.2 are both coupled to a first power supply (e.g., GND). Input terminal in.sub.1 receives an input reference current I.sub.REF, depicted here as an ideal current source coupled to a second power supply (e.g., VDD). First transistor M.sub.1, configured as shown in FIG. 4A with drain d.sub.1 and gate g.sub.1 coupled together, is commonly referred to as a diode-connected transistor.

(46) In operation, reference current I.sub.REF flows through diode-connected first transistor M.sub.1. Drain d.sub.1 and gate g.sub.1 of first transistor M.sub.1 are at the same voltage V.sub.gs1, the gate-to-source voltage V.sub.gs1 of first transistor M.sub.1. The conductor coupling gate g.sub.1 of first transistor M.sub.1 to gate g.sub.2 of second transistor M.sub.2 is labeled B.sub.1 in FIG. 4A. No current flows through conductor B.sub.1, and thus gate g.sub.2 of second transistor M.sub.2 also is at voltage V.sub.gs1. As a result, a gate-to-source voltage V.sub.gs2 of second transistor M.sub.2 equals gate-to-source voltage V.sub.gs1 of first transistor M.sub.1:
V.sub.gs2=V.sub.gs1(1)

(47) If first transistor M.sub.1 and second transistor M.sub.2 are of equal size and have equal gate-to-source voltages, second transistor M.sub.2 conducts an output current I.sub.M that equals (to a first order) reference current I.sub.REF:
I.sub.M=I.sub.REF(2)

(48) In this regard, output current I.sub.M mirrors reference current I.sub.REF, and also is referred to herein as mirror current I.sub.M. Accordingly, first transistor M.sub.1 is sometimes referred to a driver device and second transistor M.sub.2 is sometimes referred to as a mirror device, and those two terms also will be used in the remaining discussion.

(49) By rationing the dimensions of mirror device M.sub.2 relative to the dimensions of driver device M.sub.1, output current I.sub.M may be made proportional to reference current I.sub.REF. For example, if driver device M.sub.1 has a width W.sub.1 and a length L, and mirror device M.sub.2 has a width W.sub.2 and a same length L, output current I.sub.M may be expressed as follows:

(50) $\begin{array}{cc}{I}_M=\left(\frac{W_2}{W_1}\right)I_{\mathrm{REF}}& \left(3\right)\end{array}$
For example, if W.sub.2=W.sub.1, I.sub.M=I.sub.REF, Alternatively, if W.sub.2=2W.sub.1, I.sub.M=2 I.sub.REF, and so on.

(51) To replicate mirrored currents I.sub.M to multiple circuits on an integrated circuit die, bus B.sub.1 may be routed throughout the die to multiple instances of mirror device M.sub.2, each having its gate g.sub.2 coupled to bus B.sub.1 and its source s.sub.2 coupled to GND, and each scaled as desired to provide mirror currents that are proportional to reference current I.sub.REF. Because substantially no current flows through bus B.sub.1, the voltage on bus B.sub.1 remains substantially constant at V.sub.gs1 throughout the die.

(52) If driver device M.sub.1 and a particular mirror device M.sub.2 are located in close proximity to one another, current mirror circuit 400a performs well and mirror current I.sub.M closely matches reference current I.sub.REF. If driver device M.sub.1 and a particular mirror device M.sub.2 are not located in close proximity to one another, however, the ability to match currents may become degraded.

(53) For example, driver device M.sub.1 may be located in driver circuitry located in one portion of an integrated circuit die (e.g., a memory die), and a particular mirror device M.sub.2 may be located relatively far away from driver device M.sub.1 (e.g., in a memory sub-array relatively far from driver circuitry).

(54) FIG. 4B depicts such a scenario. In particular, FIG. 4B depicts a diagram of a current mirror circuit 400b, which is similar to current mirror circuit 400a of FIG. 4A. In this embodiment, however, driver device M.sub.1 drives multiple mirror devices M.sub.21, M.sub.22, . . . , M.sub.2n, all sharing a common power supply bus (e.g., ground bus GB). Each mirror device M.sub.21, M.sub.22, . . . , M.sub.2n has a corresponding source s.sub.21, s.sub.22, . . . , s.sub.2n, respectively, coupled to ground bus GB, and a corresponding gate g.sub.21, g.sub.22, . . . , g.sub.2n, respectively, coupled to bus B.sub.1, and each provides a corresponding mirror current I.sub.M1, I.sub.M2, . . . , I.sub.Mn, respectively.

(55) In an embodiment, each mirror device M.sub.21, M.sub.22, . . . , M.sub.2n is located at a different distance from driver device M.sub.1. For example, a memory die typically includes a large number of memory sub-arrays, each located a different distance from driver circuitry, and each memory sub-array includes a corresponding mirror device (e.g., a corresponding one of mirror devices M.sub.21, M.sub.22, . . . , M.sub.2n).

(56) In such an embodiment, some mirror devices (e.g., M.sub.21) are located near driver device M.sub.1, whereas other mirror devices (e.g., M.sub.2n) are located relatively far from driver device M.sub.1. As a consequence, resistance R.sub.1, R.sub.2, . . . , R.sub.n in ground bus GB between source s.sub.2 of driver device M.sub.1 and source s.sub.21, s.sub.22, . . . , s.sub.2n of each of mirror devices M.sub.21, M.sub.22, . . . , M.sub.2n, respectively, may be significant, particularly for mirror devices (e.g., M.sub.2n) located relatively large distances from driver device M.sub.1.

(57) As stated above, the voltage of bus B.sub.1 remains substantially constant at V.sub.gs1 through the die. As a result of ground bus GB resistance R.sub.1, R.sub.2, . . . , R.sub.n, however, the gate-to-source voltage of driver device M.sub.1 and each of mirror devices M.sub.21, M.sub.22, . . . , M.sub.2n are no longer equal. For example, V.sub.gs2n may be expressed as:
V.sub.gs2n=V.sub.gs1?(I.sub.STRAYR.sub.T+I.sub.M1R.sub.1I.sub.M2(R.sub.2+R.sub.1)+ . . . +I.sub.MnR.sub.T)(4)
where I.sub.Mn is the mirror current of mirror device M.sub.2n, I.sub.STRAY represents any unrelated currents flowing in ground bus GB, and R.sub.T is the total resistance in ground bus GB between source s.sub.1 of driver device M.sub.1 and source s.sub.2n of mirror device M.sub.2n. For example, R.sub.T=R.sub.1+R.sub.2+ . . . R.sub.n.

(58) As a result, V.sub.gs2n is less than V.sub.gs1, and in some instances the difference between V.sub.gs2n and V.sub.gs1 may be on the order of about 100 mV-200 mV or more. Therefore mirror current I.sub.Mn does not match reference current I.sub.REF:
I.sub.Mn?I.sub.REF(5)

(59) Indeed, in some instances the resulting error in mirror current I.sub.Mn may be many tens of percent. This magnitude of error is unacceptable for may integrated circuit applications, such as in memory circuit applications.

(60) In addition, because the total ground bus GB resistance R.sub.T between source s.sub.1 of driver device M.sub.1 and source s.sub.21, s.sub.22, . . . , s.sub.2n of corresponding mirror devices M.sub.21, M.sub.22, . . . , M.sub.2n, respectively, will differ from one another, the purportedly matched mirror currents I.sub.M1, I.sub.M2, . . . , I.sub.Mn will vary from one another based on a distance between driver device M.sub.1 and each of mirror devices M.sub.21, M.sub.22, . . . , M.sub.2n, respectively, which is unacceptable in many instances, such as in memory circuit applications.

(61) Technology is described for current mirror circuits that may reduce the impact of power supply bus (e.g., GND, VDD, VSS or other similar power supply bus) resistance on current mirror output currents. FIG. 5A is an embodiment of a current mirror circuit 500a, which has an input terminal in.sub.1a, an output terminal out.sub.1a, a first transistor M.sub.1a, a second transistor M.sub.2a, a third transistor M.sub.3a and a fourth transistor M.sub.4a. In the depicted example, first transistor M.sub.1a and second transistor M.sub.2a are each of a first polarity type (e.g., n-channel transistors), and third transistor M.sub.3a and fourth transistor M.sub.4a are each of a second polarity type different from the first polarity type (e.g., p-channel transistors).

(62) First transistor M.sub.1a has a first (e.g., drain) terminal d.sub.1a, a second (e.g., source) terminal s.sub.1a and a third (e.g., control or gate) terminal g.sub.1a. Second transistor M.sub.2a has a first (e.g., drain) terminal d.sub.2a, a second (e.g., source) terminal s.sub.2a and a third (e.g., control or gate) terminal g.sub.2a. Third transistor M.sub.3a has a first (e.g., drain) terminal d.sub.3a, a second (e.g., source) terminal s.sub.3a and a third (e.g., control or gate) terminal g.sub.3a. Fourth transistor M.sub.4a has a first (e.g., drain) terminal d.sub.4a, a second (e.g., source) terminal s.sub.4a and a third (e.g., control or gate) terminal g.sub.4a.

(63) For convenience, first terminal d.sub.1a, second terminal s.sub.1a and third terminal g.sub.1a of first transistor M.sub.1a also will be referred to herein as drain d.sub.1, source s.sub.1a and gate g.sub.1a, respectively, of first transistor M.sub.1a. Likewise, first terminal d.sub.2a, second terminal s.sub.2a and third terminal g.sub.2a of second transistor M.sub.2a also will be referred to herein as drain d.sub.2a, source s.sub.2a and gate g.sub.2a, respectively, of second transistor M.sub.2a. Similarly, first terminal d.sub.3a, second terminal s.sub.3a and third terminal g.sub.3a of third transistor M.sub.3a also will be referred to herein as drain d.sub.3a, source s.sub.3a and gate g.sub.3a, respectively, of third transistor M.sub.3a. Additionally, first terminal d.sub.4a, second terminal s.sub.4a and third terminal g.sub.4a of fourth transistor M.sub.4a also will be referred to herein as drain d.sub.4, source s.sub.4 and gate g.sub.4, respectively, of fourth transistor M.sub.4.

(64) Drain d.sub.1a of first transistor M.sub.1a is coupled to input terminal in.sub.1a, gate g.sub.1a of first transistor M.sub.1a, and gate g.sub.2a of second transistor M.sub.2a. Drain d.sub.2a of second transistor M.sub.2a is coupled to output terminal out.sub.1a. First transistor M.sub.1a, configured as shown in FIG. 5A with drain d.sub.1a and gate g.sub.1a coupled together, is commonly referred to as a diode-connected transistor.

(65) Drain d.sub.3a of third transistor M.sub.3a is coupled to a first power supply bus (e.g., ground bus GB), gate g.sub.3a of third transistor M.sub.3a, and gate g.sub.4a of fourth transistor M.sub.4a. Drain d.sub.4a of fourth transistor M.sub.4a is coupled to ground bus GB. Third transistor M.sub.3a, configured as shown in FIG. 5A with drain d.sub.3a and gate g.sub.3a coupled together, is commonly referred to as a diode-connected transistor. Resistance in ground bus GB is represented as R.sub.g. In an embodiment, drain d.sub.3a of third transistor M.sub.3a is coupled to a first location of ground bus GB, and drain d.sub.4a of fourth transistor M.sub.4a is coupled to second location different from the first location of ground bus GB.

(66) Source s.sub.1a of first transistor M.sub.1a is coupled to source s.sub.3a of third transistor M.sub.3a, and source s.sub.2a of second transistor M.sub.2a is coupled to source s.sub.4a of fourth transistor M.sub.4a. Input terminal in.sub.1a receives input reference current IREF, depicted here as an ideal current source coupled to a second power supply (e.g., VDD).

(67) In operation, reference current TREF flows through diode-connected first transistor M.sub.1a and diode-connected third transistor M.sub.3a. Drain d.sub.3a and gate g.sub.3a of third transistor M.sub.3a are at the same voltage V.sub.g3a. In the embodiment of FIG. 5A, drain d.sub.3a and gate g.sub.3a of third transistor M.sub.3a are coupled to ground bus GB, and thus voltage V.sub.g3a is at GND (e.g., V.sub.g3a=0V).

(68) The conductor coupling gate g.sub.3a of third transistor M.sub.3a to gate g.sub.4a of fourth transistor M.sub.4a is labeled GB.sub.Q in FIG. 5A. Conductor GB.sub.Q is also referred to herein as quiet ground bus GB.sub.Q. No current flows through quiet ground bus GB.sub.Q, and thus gate g.sub.4a of fourth transistor M.sub.4a is at a voltage V.sub.g4a that is substantially the same as voltage V.sub.g3a at gate g.sub.3a of third transistor M.sub.3a. In the embodiment of FIG. 5A, voltage V.sub.g4a is at GND (e.g., V.sub.g4a=0V).

(69) Source s.sub.3a of third transistor M.sub.3a is at a voltage V.sub.s3a which may be expressed as:
V.sub.s3a=V.sub.ON3+|V.sub.tp|(6)
where V.sub.ON3 is an on voltage of third transistor M.sub.3a and V.sub.tp is a threshold voltage of p-channel third transistor M.sub.3a. Source s.sub.1a of first transistor M.sub.1a is at a voltage V.sub.s1a and is coupled to source s.sub.3a of third transistor M.sub.3a. As a result, voltage V.sub.s1a equals voltage V.sub.s3a:
V.sub.s1a=V.sub.s3a(7)

(70) As stated above, gate g.sub.3a of third transistor M.sub.3a and gate g.sub.4a of fourth transistor M.sub.4a are at substantially the same voltage V.sub.g3a. Because the source voltage of a MOS transistor in saturation is a very weak function of the drain voltage, source s.sub.4a of fourth transistor M.sub.4a is at a voltage V.sub.s4a that is substantially the same as voltage V.sub.s3a at source s.sub.3a of third transistor M.sub.3a:
V.sub.s4a?V.sub.s3a(8)

(71) Without wanting to be bound by any particular theory, it is believed that even a voltage difference of several hundred millivolts between drain d.sub.4a of fourth transistor M.sub.4a and drain d.sub.3a of third transistor M.sub.3a due to a voltage drop across ground bus GB resistance R.sub.g results in very little difference in source voltages V.sub.s3a and V.sub.s4a, primarily due to third transistor M.sub.3a and fourth transistor M.sub.4a operating in the saturation region.

(72) Source s.sub.2a of second transistor M.sub.2a is at a voltage V.sub.s2a and is coupled to source s.sub.4a of fourth transistor M.sub.4a. As a result, voltage V.sub.s2a at source s.sub.2a of second transistor M.sub.2a equals voltage V.sub.s4a at source s.sub.4a of fourth transistor M.sub.4a:
V.sub.s2a=V.sub.s4a(9)
Thus, from Equations (7)-(9), source s.sub.2a of second transistor M.sub.2a and source s.sub.1a of first transistor M.sub.1a are at substantially the same voltage:
V.sub.s2a?V.sub.s1a(10)

(73) In an embodiment, the absolute value of a difference between V.sub.s2a and V.sub.s1a is less than about 5% despite voltage drops in ground bus GB between drain d.sub.3a of third transistor M.sub.3a and drain d.sub.4a of fourth transistor M.sub.4a. In another embodiment, the absolute value of a difference between V.sub.s2a and V.sub.s1a is less than about 2% despite voltage drops in ground bus GB between drain d.sub.3a of third transistor M.sub.3a and drain d.sub.4a of fourth transistor M.sub.4a. In still another embodiment, the absolute value of a difference between V.sub.s2a and V.sub.s1a is less than about 1% despite voltage drops in ground bus GB between drain d.sub.3a of third transistor M.sub.3a and drain d.sub.4a of fourth transistor M.sub.4a.

(74) Gate g.sub.1a of first transistor is at a voltage V.sub.g1a, which may be expressed as:
V.sub.g1a=V.sub.ON1+V.sub.tn+V.sub.s3a(11)
where V.sub.ON1 is an on voltage of first transistor M.sub.1a and V.sub.tn is a threshold voltage of n-channel first transistor M.sub.1a. Substituting Equation (6) into Equation (11), voltage V.sub.g1a may be expressed as:
V.sub.g1a=V.sub.ON1+V.sub.tn+V.sub.ON3+|V.sub.tp|(12)

(75) The conductor coupling gate g.sub.1a of first transistor M.sub.1a to gate g.sub.2a of second transistor M.sub.2a is labeled B.sub.a in FIG. 5A. No current flows through conductor B.sub.a, and thus gate g.sub.2a of second transistor M.sub.2a also is at voltage V.sub.g1a. As a result, gate-to-source voltage V.sub.gs1a of first transistor M.sub.1a substantially equals gate-to-source voltage V.sub.gs2a of second transistor M.sub.2a:
V.sub.gs1a=V.sub.gs2a(13)

(76) Accordingly, if first transistor M.sub.1a and second transistor M.sub.2a are of equal size, second transistor M.sub.2a conducts an output current I.sub.Mn that substantially equals reference current I.sub.REF:
I.sub.Mn=I.sub.REF(14)

(77) In this regard, output current I.sub.Mn mirrors reference current I.sub.REF, and also is referred to herein as mirror current I.sub.Mn.

(78) Following similar terminology described above regarding current mirror circuit 400a of FIG. 4A, first transistor M.sub.1a, second transistor M.sub.2a, third transistor M.sub.3a, and fourth transistor M.sub.4a of current mirror circuit 500a of FIG. 5A are also referred to herein as first driver device M.sub.1a, first mirror device M.sub.2a, second driver device M.sub.3a, and second mirror device M.sub.4a, respectively.

(79) By rationing the dimensions of first mirror device M.sub.2a and second mirror device M.sub.4a relative to the dimensions of first driver device M.sub.1a and second driver device M.sub.3a, respectively, output current I.sub.Mn may be made proportional to reference current I.sub.REF.

(80) For example, if first driver device M.sub.1a has a width W.sub.1 and a length L, first mirror device M.sub.2a has a width W.sub.2 and a length L, second driver device M.sub.3a has a width W.sub.3 and a length L, and second mirror device M.sub.4a has a width W.sub.4 and a length L, and if W.sub.2/W.sub.1=W.sub.4/W.sub.3, output current I.sub.Mn may be expressed as follows:

(81) $\begin{array}{cc}{I}_{\mathrm{Mn}}=\left(\frac{W_2}{W_1}\right)I_{\mathrm{REF}}& \left(15\right)\end{array}$
For example, if W.sub.2=W.sub.1, I.sub.Mn=I.sub.REF. Alternatively, if W.sub.2=2W.sub.1, I.sub.Mn=2?I.sub.REF, and so on.

(82) To replicate mirrored currents I.sub.Mn to multiple circuits on an integrated circuit die, bus B.sub.a and quiet ground bus GB.sub.Q may be routed throughout the die to multiple instances of first mirror device M.sub.2a and second mirror device M.sub.4a, scaled as desired to provide mirror currents proportional to current I.sub.REF. Because substantially no current flows through bus B.sub.a, the voltage on bus B.sub.a remains substantially constant at V.sub.g1a throughout the die. In this regard, first driver device M.sub.1a provides a first bias voltage V.sub.g1a on bus B.sub.a. Likewise, because substantially no current flows through quiet ground bus GB.sub.Q, the voltage on quiet ground bus GB.sub.Q remains substantially constant at V.sub.g3a throughout the die. In this regard, second driver device M.sub.3a provides a second bias voltage V.sub.g3a different from first bias voltage V.sub.g1a on quiet ground bus GB.sub.Q.

(83) As a result, without wanting to be bound by any particular theory, it is believed that despite variations in the voltage at drain d.sub.4a across all instances of second mirror device M.sub.4a throughout the die as a result of resistance R.sub.g in ground bus GB, the gate-to-source voltage across all instances of first mirror device M.sub.2a will be substantially the same throughout the die (for 1:1 ratioed mirror devices), and thus all mirrored currents I.sub.Mn will be substantially the same throughout the die (for 1:1 ratioed mirror devices) independent of voltage differences along the power supply bus between first driver device M.sub.1a and first mirror device M.sub.2a.

(84) In addition, without wanting to be bound by any particular theory, it is believed that despite variations in the voltage at drain d.sub.4a across all instances of second mirror device M.sub.4a throughout the die as a result of resistance R.sub.g in ground bus GB, the gate-to-source voltage across all instances of first mirror device M.sub.2a will be substantially the same throughout the die (for 1:1 ratioed mirror devices), and thus all mirrored currents I.sub.Mn will be substantially the same throughout the die (for 1:1 ratioed mirror devices) independent of distance between first driver device M.sub.1a and first mirror device M.sub.2a.

(85) Although the example current mirror circuit 500a of FIG. 5A is configured with drain d.sub.3a of second driver device M.sub.3a and drain d.sub.4a of second mirror device M.sub.4a coupled to ground bus GB, the same principle applies if ground bus GB were alternatively a negative power supply bus coupled to a negative power supply (e.g., V.sub.SS=?1.7V).

(86) FIG. 5B is another embodiment of a current mirror circuit that may reduce the impact of power supply bus resistance on current mirror output currents. In particular, current mirror circuit 500b has an input terminal in.sub.1b, an output terminal out.sub.1b, a first transistor M.sub.1b, a second transistor M.sub.2b, a third transistor M.sub.3b and a fourth transistor M.sub.4b. In the depicted example, first transistor M.sub.1b and second transistor M.sub.2b are each of a first conductivity type (e.g., p-channel transistors), and third transistor M.sub.3b and fourth transistor M.sub.4b are each of a second conductivity type different from the first conductivity type (e.g., n-channel transistors).

(87) First transistor M.sub.1b has a first (e.g., drain) terminal d.sub.1b, a second (e.g., source) terminal s.sub.1b and a third (e.g., control or gate) terminal g.sub.1b. Second transistor M.sub.2b has a first (e.g., drain) terminal d.sub.2b, a second (e.g., source) terminal s.sub.2b and a third (e.g., control or gate) terminal g.sub.2b. Third transistor M.sub.3b has a first (e.g., drain) terminal d.sub.3b, a second (e.g., source) terminal s.sub.3b and a third (e.g., control or gate) terminal g.sub.3b. Fourth transistor M.sub.4b has a first (e.g., drain) terminal d.sub.4b, a second (e.g., source) terminal s.sub.4b and a third (e.g., control or gate) terminal g.sub.b.

(88) For convenience, first terminal d.sub.1b, second terminal s.sub.1b and third terminal g.sub.1b of first transistor M.sub.1b also will be referred to herein as drain d.sub.1b, source s.sub.1b and gate g.sub.1b, respectively, of first transistor M.sub.1b. Likewise, first terminal d.sub.2b, second terminal s.sub.2b and third terminal g.sub.2b of second transistor M.sub.2b also will be referred to herein as drain d.sub.2b, source s.sub.2b and gate g.sub.2b, respectively, of second transistor M.sub.2b. Similarly, first terminal d.sub.3b, second terminal s.sub.3b and third terminal gab of third transistor M.sub.3b also will be referred to herein as drain d.sub.3b, source s.sub.3b and gate g.sub.3b, respectively, of third transistor M.sub.3b. Additionally, first terminal d.sub.4b, second terminal s.sub.4b and third terminal gab of fourth transistor M.sub.4b also will be referred to herein as drain d.sub.4, source s.sub.4 and gate g.sub.4, respectively, of fourth transistor M.sub.4.

(89) Drain d.sub.1b of first transistor M.sub.1b is coupled to input terminal in.sub.1b, gate g.sub.1b of first transistor M.sub.1b, and gate g.sub.2b of second transistor M.sub.2b. Drain d.sub.2b of second transistor M.sub.2b is coupled to output terminal out.sub.1b. First transistor M.sub.1b, configured as shown in FIG. 5B with drain d.sub.1b and gate g.sub.1b coupled together, is commonly referred to as a diode-connected transistor.

(90) Drain d.sub.3b of third transistor M.sub.3b is coupled to second power supply bus (e.g., positive power bus PB), gate g.sub.4b of third transistor M.sub.3b, and gate g.sub.4b of fourth transistor M.sub.4b. Drain d.sub.4b of fourth transistor M.sub.4b is coupled to positive power bus PB, which is coupled to second power supply VDD. Third transistor M.sub.3b, configured as shown in FIG. 5B with drain d.sub.3b and gate g.sub.3b coupled together, is commonly referred to as a diode-connected transistor. Resistance in power bus PB is represented as R.sub.P. In an embodiment, drain d.sub.3b of third transistor M.sub.3b is coupled to a first location of positive power bus PB, and drain d.sub.4b of fourth transistor M.sub.4b is coupled to second location different from the first location of positive power bus PB.

(91) Source s.sub.1b of first transistor M.sub.1b is coupled to source s.sub.3b of third transistor M.sub.3b, and source s.sub.2b of second transistor M.sub.2b is coupled to source s.sub.4b of fourth transistor M.sub.4b. Input terminal in.sub.1b receives input reference current I.sub.REF, depicted here as an ideal current source coupled to first power supply GND.

(92) In operation, reference current I.sub.REF flows through diode-connected first transistor M.sub.1b and diode-connected third transistor M.sub.3b. Drain d.sub.3b and gate g.sub.4b of third transistor M.sub.3b are at the same voltage V.sub.g3b. In the embodiment of FIG. 5B, drain d.sub.3b and gate g.sub.4b of third transistor M.sub.3b are coupled to positive power bus PB, and thus voltage V.sub.g3b is at VDD (e.g., V.sub.g3b=1.7V).

(93) The conductor coupling gate g.sub.3b of third transistor M.sub.3b to gate g.sub.4b of fourth transistor M.sub.4b is labeled PB.sub.Q in FIG. 5B. Conductor PB.sub.Q is also referred to herein as quiet power bus PB.sub.Q. No current flows through quiet power bus PB.sub.Q, and thus gate g.sub.4b of fourth transistor M.sub.4b is at a voltage V.sub.g4b that is substantially the same as voltage V.sub.g3b at gate g.sub.4b of third transistor M.sub.3b. In the embodiment of FIG. 5B, voltage V.sub.g4b is at VDD (e.g., V.sub.g4a=1.7V).

(94) Source s.sub.3b of third transistor M.sub.3b is at a voltage V.sub.s3b which may be expressed as:
V.sub.s3b=VDD=(V.sub.ON3+V.sub.tn)(16)
where V.sub.ON3 is an on voltage of third transistor M.sub.3b and V.sub.tn is a threshold voltage of n-channel third transistor M.sub.3b. Source so of first transistor M.sub.1b is at a voltage V.sub.s1b and is coupled to source s.sub.3b of third transistor M.sub.3b. As a result, voltage V.sub.s1b equals voltage V.sub.s3b:
V.sub.s1b=V.sub.s3b(17)

(95) As stated above, gate g.sub.3b of third transistor M.sub.3b and gate g.sub.4b of fourth transistor M.sub.4b are at substantially the same voltage V.sub.g3b. Because the source voltage of a MOS transistor in saturation is a very weak function of the drain voltage, source s.sub.4b of fourth transistor M.sub.4b is at a voltage V.sub.s4b that is substantially the same as voltage V.sub.s3b at source s.sub.3b of third transistor M.sub.3b:
V.sub.s4b?V.sub.s3b(18)

(96) Without wanting to be bound by any particular theory, it is believed that even a voltage difference of several hundred millivolts between drain d.sub.4b of fourth transistor M.sub.4b and drain d.sub.3b of third transistor M.sub.3b due to a voltage drop across positive power bus PB resistance R.sub.P results in very little difference in source voltages V.sub.s3b and V.sub.s4b, primarily due to third transistor M.sub.3b and fourth transistor M.sub.4b operating in the saturation region.

(97) Source s.sub.2b of second transistor M.sub.2b is at a voltage V.sub.s2b and is coupled to source s.sub.4b of fourth transistor M.sub.4b. As a result, voltage V.sub.s2b at source s.sub.2b of second transistor M.sub.2b equals voltage V.sub.s4b at source s.sub.4b of fourth transistor M.sub.4b:
V.sub.s2b=V.sub.s4b(19)

(98) Thus, from Equations (17)-(19), source s.sub.2b of second transistor M.sub.2b and source so of first transistor M.sub.1b are at substantially the same voltage:
V.sub.s2b?V.sub.s1b(20)

(99) In an embodiment, the absolute value of a difference between V.sub.s2b and V.sub.s1b is less than about 5% despite voltage drops in positive power bus PB between drain d.sub.3b of third transistor M.sub.3b and drain d.sub.4b of fourth transistor M.sub.4b. In another embodiment, the absolute value of a difference between V.sub.s2b and V.sub.s1b is less than about 2% despite voltage drops in positive power bus PB between drain d.sub.3b of third transistor M.sub.3b and drain d.sub.4b of fourth transistor M.sub.4b. In still another embodiment, the absolute value of a difference between V.sub.s2b and V.sub.s1b is less than about 1% despite voltage drops in positive power bus PB between drain d.sub.3b of third transistor M.sub.3b and drain d.sub.4b of fourth transistor M.sub.4b.

(100) Gate g.sub.1b of first transistor is at a voltage V.sub.g1b, which may be expressed as:
V.sub.g1b=V.sub.s1b?(V.sub.ON1+|V.sub.tp|)(21)
where V.sub.ON1 is an on voltage of first transistor M.sub.1b and V.sub.tp is a threshold voltage of p-channel first transistor M.sub.1b. Substituting Equation (16) into Equation (21), voltage V.sub.g1b may be expressed as:
V.sub.g1b=VDD?(V.sub.ON3+V.sub.tn+V.sub.ON1|V.sub.tp|)(22)

(101) The conductor coupling gate g.sub.1b of first transistor M.sub.1b to gate g.sub.2b of second transistor M.sub.2b is labeled B.sub.b in FIG. 5B. No current flows through conductor B.sub.b, and thus gate g.sub.2b of second transistor M.sub.2b also is at voltage V.sub.g1b. As a result, source-to-gate voltage V.sub.sg1b of first transistor M.sub.1b substantially equals source-to-gate voltage V.sub.sg2b of second transistor M.sub.2b:
V.sub.sg1b=V.sub.sg2b(23)

(102) If first transistor M.sub.1b and second transistor M.sub.2b are of equal size, second transistor M.sub.2b conducts an output current I.sub.Mp that substantially equals reference current I.sub.REF:
I.sub.Mp=I.sub.REF(24)

(103) In this regard, output current I.sub.Mp mirrors reference current I.sub.REF, and also is referred to herein as mirror current I.sub.Mp.

(104) Following similar terminology described above regarding current mirror circuit 400a of FIG. 4A, first transistor M.sub.1b, second transistor M.sub.2b, third transistor M.sub.3b, and fourth transistor M.sub.4b of current mirror circuit 500b of FIG. 5B are also referred to herein as first driver device M.sub.1b, first mirror device M.sub.2b, second driver device M.sub.3b, and second mirror device M.sub.4b, respectively.

(105) By rationing the dimensions of first mirror device M.sub.2b and second mirror device M.sub.4b relative to the dimensions of first driver device M.sub.1b and second driver device M.sub.3b, respectively, output current I.sub.Mp may be made proportional to reference current I.sub.REF.

(106) For example, if first driver device M.sub.1b has a width W.sub.1 and a length L, first mirror device M.sub.2b has a width W.sub.2 and a length L, second driver device M.sub.3b has a width W.sub.3 and a length L, and second mirror device M.sub.4b has a width W.sub.4 and a length L, and if W.sub.2/W.sub.1=W.sub.4/W.sub.3, output current I.sub.Mp may be expressed as follows:

(107) $\begin{array}{cc}{I}_{\mathrm{Mp}}=\left(\frac{W_2}{W_1}\right)I_{\mathrm{REF}}& \left(25\right)\end{array}$
For example, if W.sub.2=W.sub.1, I.sub.Mp=I.sub.REF, if W.sub.2=2W.sub.1. Alternatively, if I.sub.Mp=2?I.sub.REF, and so on.

(108) To replicate mirrored currents I.sub.Mp to multiple circuits on an integrated circuit die, bus B.sub.b and quiet power bus PB.sub.Q may be routed throughout the die to multiple instances of first mirror device M.sub.2b and second mirror device M.sub.4b, scaled as desired to provide mirror currents proportional to reference current I.sub.REF. Because substantially no current flows through bus B.sub.b, the voltage on bus B.sub.b remains substantially constant at V.sub.g1b throughout the die. In this regard, first driver device M.sub.1b provides a first bias voltage V.sub.g1b on bus B.sub.b. Likewise, because substantially no current flows through quiet power bus PB.sub.Q, the voltage on quiet power bus PB.sub.Q remains substantially constant at V.sub.g3b throughout the die. In this regard, second driver device M.sub.3b provides a second bias voltage V.sub.g3b different from first bias voltage V.sub.g1b on quiet power bus PB.sub.Q.

(109) As a result, without wanting to be bound by any particular theory, it is believed that despite variations in the voltages at drain d.sub.4b across all instances of second mirror device M.sub.4b throughout the die as a result of resistance R.sub.P in positive power bus PB, the source-to-gate voltage across all instances of first mirror device M.sub.2b will be substantially the same throughout the die (for 1:1 ratioed mirror devices), and thus all mirrored currents I.sub.Mp will be substantially the same throughout the die (for 1:1 ratioed mirror devices) independent of voltage differences along the power supply bus between first driver device M.sub.1b and first mirror device M.sub.2b.

(110) In addition, without wanting to be bound by any particular theory, it is believed that despite variations in the voltages at drain d.sub.4b across all instances of second mirror device M.sub.4b throughout the die as a result of resistance R.sub.P in positive power bus PB, the source-to-gate voltage across all instances of first mirror device M.sub.2b will be substantially the same throughout the die (for 1:1 ratioed mirror devices), and thus all mirrored currents I.sub.Mp will be substantially the same throughout the die (for 1:1 ratioed mirror devices) independent of distance between first driver device M.sub.1b and first mirror device M.sub.2b.

(111) FIG. 6 is a diagram of an embodiment of a memory die 600. Each of the one or more memory die 106 of FIG. 1 can be implemented as memory die 600 of FIG. 6. Memory die 600 includes a current mirror driver circuit 602 and a memory array 604. Current mirror driver circuit 602 is coupled to a power supply bus (e.g., ground bus GB) and includes a first driver device M.sub.1a configured to provide a first bias voltage VB.sub.a, and a second driver device M.sub.3a configured to provide a second bias voltage VB.sub.Q different from first bias voltage VB.sub.a. First driver device M.sub.1a and second driver device M.sub.3a conduct a first current I.sub.REF.

(112) In an embodiment, memory array 604 includes multiple sub-arrays 606.sub.1, 606.sub.2, 606.sub.3, . . . , 606.sub.n, each of sub arrays 606.sub.1, 606.sub.2, 606.sub.3, . . . , 606.sub.n include a corresponding first mirror device M.sub.2a1, M.sub.2a2, M.sub.2a3, . . . , M.sub.2an, respectively, coupled to the first bias voltage, and a corresponding second mirror device M.sub.4a1, M.sub.4a2, M.sub.4a3, . . . , M.sub.4an, respectively, coupled to the second bias voltage and to ground bus GB.

(113) In an embodiment, each first mirror device M.sub.2a1, M.sub.2a2, M.sub.2a3, . . . , M.sub.2an and second mirror device M.sub.4a1, M.sub.4a2, M.sub.4a3, . . . , M.sub.4an conducts a corresponding second current I.sub.Mn1, I.sub.Mn2, I.sub.Mn3, . . . , I.sub.Mnn, respectively. In an embodiment, corresponding second currents I.sub.Mn2, I.sub.Mn3, . . . , I.sub.Mnn of sub-arrays 606.sub.1, 606.sub.2, 606.sub.3, . . . , 606.sub.n, respectively, are substantially equal.

(114) One embodiment includes a circuit that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

(115) One embodiment includes a current mirror circuit that includes a diode-connected first transistor of a first conductivity type, a second transistor of the first conductivity type, a diode-connected third transistor of a second conductivity type different from the first conductivity, and a fourth transistor of the second conductivity type. The diode-connected first transistor is coupled to the second transistor, a control terminal of the first transistor is coupled to a control terminal of the second transistor. The diode-connected third transistor is coupled to the first diode-connected transistor and to the fourth transistor, the fourth transistor is coupled to the second transistor, and a control terminal of the third transistor is coupled to a control terminal of the second transistor. The first transistor and the third transistor each conduct a first current and the second transistor and the fourth transistor each conduct a second current that is substantially proportional to the first current.

(116) One embodiment includes an apparatus including a memory die comprising a current mirror driver circuit and a memory array. The current mirror driver circuit is coupled to a power supply bus and includes a first driver device configured to provide a first bias voltage, and a second driver device configured to provide a second bias voltage different from the first bias voltage. The first driver device and the second driver device conduct a first current. The memory array includes a plurality of sub-arrays, each sub array including a corresponding first mirror device coupled to the first bias voltage, and a corresponding second mirror device coupled to the second bias voltage and to the power supply bus. The first mirror device and second mirror device conduct a corresponding second current. The corresponding second currents of each of the plurality of sub-arrays are substantially equal.

(117) For purposes of this document, reference in the specification to an embodiment, one embodiment, some embodiments, or another embodiment may be used to describe different embodiments or the same embodiment.

(118) For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are in communication if they are directly or indirectly connected so that they can communicate electronic signals between them.

(119) For purposes of this document, the term based on may be read as based at least in part on.

(120) For purposes of this document, without additional context, use of numerical terms such as a first object, a second object, and a third object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.

(121) For purposes of this document, the term set of objects may refer to a set of one or more of the objects.

(122) The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.