LEVEL CONVERTER

Abstract

The invention relates to a level converter for adjusting a first reference potential and/or a first communication voltage of a first component to a second reference potential and/or a second communication voltage of a second component, wherein the level converter is arranged between the first component and the second component, wherein the level converter has a first transistor with a downstream first resistor, wherein the level converter is configured in such a way that the second reference potential drops at the first resistor in a blocked state of the first transistor and that the second communication voltage drops at the first resistor in an open state of the first transistor.

Claims

1-8. (canceled)

9. A level converter for adjusting a first reference potential and/or a first communication voltage of a first component to a second reference potential and/or a second communication voltage of a second component, wherein the level converter is arranged between the first component and the second component, the level converter comprising: a first transistor with a downstream first resistor, wherein the level converter is configured such that the second reference potential drops at the first resistor in a blocked state of the first transistor and that the second communication voltage drops at the first resistor in an open state of the first transistor.

10. The level converter according to claim 9, wherein the first transistor is a bipolar PNP transistor or a field effect transistor.

11. The level converter according to claim 9, wherein the first resistor is arranged between the first transistor and the second reference potential.

12. The level converter according to claim 9, wherein the first transistor has a first input and a first output, wherein, in the open state of the first transistor, a current flows through the first input and the first output, wherein the first output is connected to the second reference potential, wherein the first input is connected to a first voltage source, wherein the first voltage source outputs a voltage that is identical to the second communication voltage or is a voltage that is higher than the second reference potential, so that in an open state of the first transistor, the second communication voltage drops at the first resistor.

13. The level converter according to claim 9, wherein the open or the blocked state of the first transistor can be set via a first control connection of the first transistor.

14. The level converter according to claim 13, wherein the first control connection is connected to a second transistor, wherein the second transistor is configured such that the first transistor is open in an open state of the second transistor and that the first transistor is blocked in a blocked state of the second transistor.

15. The level converter according to claim 14, wherein the first reference potential is connected to a second output of the second transistor, wherein a second voltage source is connected to the second input of the second transistor, wherein the second voltage source outputs a voltage that is higher than that of the first reference potential, wherein the first transistor is connected between the second voltage source and the second input of the second transistor, wherein a second resistor and a third resistor is provided between the first transistor and the second voltage source and between the first transistor and the second input of the second transistor, respectively.

16. The level converter according to claim 13, wherein the first input is connected to the first control connection via a fourth resistor, wherein a fifth resistor is connected to the first control side in parallel with the fourth resistor.

Description

[0019] The invention is explained in more detail below with reference to FIGS. 1 to 3. In the figures:

[0020] FIG. 1: shows a schematic of the integration of the level converter according to the invention into a circuit.

[0021] FIG. 2: shows a first embodiment of the level converter according to the invention.

[0022] FIG. 3: shows a second embodiment of the level converter according to the invention.

[0023] The level converter according to the invention can especially be used in field devices of all types in which a transformation of the different reference potentials and/or different communication voltages of two components is required.

[0024] FIG. 1 shows a schematic of the level converter L according to the invention, which is arranged between a first component E1 and a second component E2. The first and second components E1, E2 each have different first and second reference potentials P1, P2 and first and second communication voltages K1, K2. According to the invention, the level converter L serves to adjust the first reference potential P1 and/or the first communication voltage K1 of the first component E1 to the second reference potential P2 and/or the second communication voltage K2 of the second component E2. Without the level converter L connected between the two components E1, E2, communication between the two components E1, E2 would not be possible. In order to enable communication in both directions, two level converters L are required, which transform in opposite directions. The first component is, for example, a microprocessor which requires a first reference potential of 0 V or GND and a communication voltage of 3 V, while the second component requires an IO device, a second reference potential of ?10 . . . 0 V or IOL_GND and a second communication voltage of IOL-GND+3 V for communication.

[0025] FIG. 2 shows a first possible embodiment of the level converter L according to the invention. The level converter L has an input in and an output out, via which the level converter L is connected to the first and second components E1, E2, and a first transistor T1 with a downstream resistor R1. The first transistor has a first input G1, a first output A1 and a first control connection B1. In the open state of the first transistor T1, a current flows through the first input G1 and the first output A1. The level converter L is configured to obtain, at the first resistor R1, the second reference potential P2 in a blocked state of the first transistor T1 and the second communication voltage K2 in the open state of the first transistor T1. The first transistor T1 is, for example, a bipolar pnp transistor, wherein a field effect transistor may also be used. The first resistor R1 is arranged, for example, between the first output A1 of the first transistor T1 and the second reference potential P2. As a result of this arrangement, in the blocked state of the transistor T1, the second reference potential P2 drops at the first resistor R1.

[0026] In order for the second communication voltage K2 to drop at the first resistor R1 in the open state of the first transistor T1, the first input G1 of the first transistor T1 is connected, for example, to a first voltage source V1. The first voltage source V1 is used to output a voltage that is either identical to the second communication voltage K2 or is a voltage that is higher than the second reference potential P2 in such a way that the second communication voltage K2 is obtained at the first resistor R1 in the open state of the first transistor T1. Especially if the second reference potential P2 corresponds to GND, the first voltage source V1 can be set to the second communication voltage K2.

[0027] Setting the state of the first transistor T1 or opening and blocking the first transistor T1 takes place, for example, via the first control connection B1. One possibility of controlling the first transistor T1 is to connect a second transistor T2 to the first control connection. The first transistor T1 then assumes the state specified by the second transistor T2, so that both transistors T1, T2 are either simultaneously opened or blocked.

[0028] The second transistor T2 in turn has a second input G2, a second output A2 and a second control connection B2. Thus, for example, the first reference potential P1 is connected to the second output A2 and a second voltage source V2 is connected to the second input G2. In order to open the first transistor, the second voltage source V2 must output a voltage that is higher than that of the first reference potential P1. The voltage output at the second voltage source V2 must, for example, be higher than the first reference potential P1 by at least the base current that is necessary to open the first transistor T1 at the first control connection B1. The first transistor T1 is located between the second voltage source V2 and the second input G2. In addition, two further resistors R2, R3 are provided. The second resistor R2 is located between the first transistor T1 and the second voltage source V2. The third resistor R3 is arranged between the first transistor T2 and the second input G2.

[0029] The second transistor T2 is controlled by the second control connection B2 at which, for example, at least the first reference potential P1 is received. In this case, the second transistor would be blocked since the first reference potential is likewise applied to the second output A2. The second transistor T2 opens when a voltage that is at least as large as the sum of the first reference potential P1 and the voltage that is at least necessary for switching the second transistor T2 is applied to the second control connection B2.

[0030] FIG. 3 shows a second embodiment of the level converter according to the invention. In this case, a combination of resistors rather than a second transistor T2 is used for controlling the first transistor T1. The fourth resistor R4 ensures a connection between the first voltage source V1 and the first control connection B1. In parallel with the fourth resistor R4, a fifth resistor R5 is introduced between the input in the level converter and the first control connection. The voltage received by the level converter drops at the fifth resistor R5, while the voltage of the first voltage source V1 drops at the fourth resistor R4. Only if a voltage that corresponds at most to the difference between the voltage of the first voltage source V1 and the base current of the first transistor T1 drops at the node between the fourth resistor R4 and the fifth resistor R5 is the first transistor T1 opened. For example, the first voltage source outputs 3.3 V. If 3.3 V is also applied to the input in of the level converter L, the first transistor T1 is blocked. As soon as a voltage below 2.6 V is applied to the input of the level converter L, the first transistor T1 is opened since the base voltage of the first transistor T1 is approximately 0.7 V.

LIST OF REFERENCE SIGNS

[0031] L Level converter [0032] E1 First component [0033] E2 Second component [0034] P1 First reference potential [0035] P2 Second reference potential [0036] K1 First communication voltage [0037] K2 Second communication voltage [0038] V1 First voltage source [0039] V2 Second voltage source [0040] T1 First transistor [0041] G1 First input of the first transistor [0042] A1 First output of the first transistor [0043] B1 First control connection of the first transistor [0044] T2 Second transistor [0045] G2 Second input of the second transistor [0046] A2 Second output of the second transistor [0047] B2 Second control connection of the second transistor [0048] R1 First resistor [0049] R2 Second resistor [0050] R3 Third resistor [0051] R4 Fourth resistor [0052] R5 Fifth resistor [0053] in Input signal of the level converter [0054] out Output signal of the level converter