System for Detecting External Reference Resistor in Voltage Supply Path

Abstract

A system includes an operational amplifier which includes a first amplifier input, a second amplifier input and an amplifier output. The system includes a first switch which includes a first terminal and includes a second terminal coupled to the first amplifier input. The system includes a second switch which includes a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input. The system includes a first bias current source coupled between the first amplifier input and a common potential and includes a second bias current source coupled between the first terminal of the first switch and the common potential. The system includes a feedback path between the amplifier output and the first amplifier input.

Claims

1. A system comprising: a system input; a system output; an operational amplifier comprising: a first amplifier input coupled to the system input; a second amplifier input; and an amplifier output; a first switch including a first terminal and including a second terminal coupled to the first amplifier input; a second switch including a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input; a first bias current source coupled between the first amplifier input and a common potential; a second bias current source coupled between the first terminal of the first switch and the common potential; a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; and a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor.

2. The system of claim 1, further comprising a first capacitor coupled between the second amplifier input and the common potential.

3. The system of claim 1, further comprising a second capacitor coupled between the control terminal of the first transistor and the common potential.

4. The system of claim 1, further comprising a second transistor including a first current terminal coupled to the system output, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch.

5. The system of claim 1, further comprising a first resistor coupled between the system input and the first amplifier input.

6. An external resistor detection circuit, comprising: an operational amplifier including a first amplifier input adapted to be coupled to the external resistor and including a second amplifier input and an amplifier output; a first switch including a first terminal and including a second terminal coupled to the first amplifier input; a second switch including a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input; a first bias current source coupled between the first amplifier input and a common potential; a second bias current source coupled between the first terminal of the first switch and the common potential; a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor; a first capacitor coupled between the second amplifier input and the common potential; and a second capacitor coupled between the control terminal of the first transistor and the common potential.

7. The system of claim 6, further comprising a second transistor including a first current terminal coupled to a system output, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch.

8. The system of claim 6, further comprising a first resistor coupled between the external resistor and the first amplifier input.

9. A circuit having an external terminal adapted to be coupled to an external resistor, the circuit comprising: an operational amplifier including a first amplifier input coupled to the external terminal and including a second amplifier input and an amplifier output; a first capacitor coupled between the second amplifier input and a common potential; and a feedback path including a first terminal coupled to the amplifier output and a second terminal coupled to the external terminal, the feedback path configured to provide an output current corresponding to the resistance of the external resistor.

10. The circuit of claim 9, further comprising: a first switch including a first terminal and including a second terminal coupled to the first amplifier input; a second switch including a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input; a first bias current source coupled between the first amplifier input and the common potential; and a second bias current source coupled between the first terminal of the first switch and the common potential.

11. The circuit of claim 9, wherein the feedback path comprises: a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; and a fourth switch including a first terminal coupled to the external terminal and a second terminal coupled to the first current terminal of the first transistor.

12. The circuit of claim 11, further comprising a second capacitor coupled between the control terminal of the first transistor and the common potential.

13. The circuit of claim 11, further comprising a second transistor including a first current terminal coupled to a circuit output, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch.

14. The circuit of claim 9, further comprising a first resistor coupled between the external terminal and the first amplifier input.

15. A system comprising: a system input; a system output; an operational amplifier comprising: a first amplifier input coupled to the system input; a second amplifier input; and an amplifier output; a first switch including a first terminal and including a second terminal coupled to the first amplifier input; a second switch including a first terminal coupled to the first amplifier input and a second terminal coupled to the second amplifier input; a first bias current source coupled between the first amplifier input and a common potential; a second bias current source coupled between the first terminal of the first switch and the common potential; and a feedback path including a first terminal coupled to the amplifier output and a second terminal coupled to the system input.

16. The system of claim 15, wherein the feedback path comprises: a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; and a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor.

17. The system of claim 15, further comprising a first capacitor coupled between the second amplifier input and the common potential.

18. The system of claim 15, further comprising a second capacitor coupled between the control terminal of the first transistor and the common potential.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is a block diagram illustrating a system of an example embodiment.

[0013] FIGS. 2A, 2B and 2C are circuit diagrams illustrating a detector circuit of an example embodiment.

[0014] FIG. 3 is a timing diagram illustrating voltages generated in the detector circuit of FIGS. 2A-2C.

[0015] FIG. 4 is a circuit diagram illustrating a detector which is an example implementation of the detector of FIGS. 2A-2C.

[0016] The same reference numerals or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features.

DETAILED DESCRIPTION

[0017] FIG. 1 is a block diagram illustrating system 100 of an example embodiment. System 100 may be used, for example, in industrial systems, automotive systems, petrochemical systems, fire control systems, communication systems and power systems. In some example embodiments, system 100 may be implemented in an integrated circuit (IC) or a semiconductor die.

[0018] System 100 includes system input 120 and system input/output 122. In some example embodiments, system input 120 and system input/output 122 may be connected to external terminals of an IC. The external terminals may be pins, leads (e.g., J-leads), balls (such as in a ball-grid array) or leadless terminals. The external terminals allow connections between system 100 and other circuitry or systems.

[0019] System 100 includes detector 104 which includes detector input 124 coupled to system input 120 and incudes detector output 126. System 100 includes input buffer 108 which includes buffer input 128 coupled to detector output 126 and includes buffer output 130 coupled to system output 122. In some example embodiments, input buffer 108 may include an analog-to-digital (A/D) converter (not shown in FIG. 1), a buffer amplifier (not shown in FIG. 1), and/or a micro-controller or processor (not shown in FIG. 1).

[0020] Input buffer 108 may be coupled to sensor 112. Sensor 112 includes sensor input/output 132 coupled to system input/output 122. Sensor 112 may, for example, be a temperature sensor, a pressure sensor or a motion sensor. Sensor 112 provides output signal Spur at sensor output 134 which may represent a measured quantity such as a temperature, a pressure or a motion. Sensor output 134 may be coupled to processor and/or other analog or digital circuitry (which may be included in system 100 or another system).

[0021] System 100 is configured to detect a resistance of an external reference resistor R.sub.EXT (e.g., between around 700 ohms to around 4K ohms) in a supply path. Here, the supply path refers to a conduction path between voltage supply V.sub.CC (e.g., around 24V) and system input 120. External reference resistor R.sub.EXT includes first terminal 134 coupled to system input 120 and includes second terminal 136. Voltage supply V.sub.CC includes first terminal 138 coupled to second terminal 136 of R.sub.EXT and includes second terminal 140 coupled to common potential 150 (e.g., ground). When system input 120 is coupled to voltage supply V.sub.CC via R.sub.EXT, voltage A.sub.VDD appears at system input 120.

[0022] To operate sensor 112 properly, input buffer 108 draws a particular amount of current from sensor 112 or provides a particular amount of current into sensor 112. In some example embodiments, detector 104 determines a resistance of R.sub.EXT and based on the resistance value provides output current I.sub.OUT (which corresponds to the resistance value of R.sub.EXT). Based on the value of I.sub.OUT, input buffer 108 draws current I.sub.IN from sensor 112 or provides current I.sub.IN into sensor 112. A user may, for example, connect R.sub.EXT in the supply path between system input 120 and supply voltage V.sub.CC, and based on the resistance value of R.sub.EXT, detector 104 provides a corresponding I.sub.OUT to input buffer 108. In response to the value of I.sub.OUT, input buffer 108 current draws I.sub.IN from sensor 112 or provides current I.sub.IN to sensor 112. As such, system 100 provides a current programmability based on R.sub.EXT.

[0023] FIG. 2A illustrates detector 200 which is an example implementation of detector 104 of FIG. 1. Detector 200 includes detector input 124 and detector output 126. Detector input 124 is adapted to be coupled to system input 120. Detector output 126 is coupled to system output 122 via input buffer 108 (shown in FIG. 1).

[0024] Detector 200 includes operational amplifier A.sub.1 which includes first amplifier input 204 (e.g., non-inverting input), second amplifier input 206 (e.g., inverting input) and amplifier output 208. First amplifier input 204 is coupled to detector input 124 via resistor R.sub.INT (e.g., around 500K ohms) (may also be referred to as the first resistor). Detector 200 includes first switch S.sub.1 which includes first terminal 210 and includes second terminal 212 coupled to first amplifier input 204. When S.sub.1 is closed (e.g., S.sub.1 is conducting such that terminal 210 is connected to terminal 212), and thus a conduction path is provided for a current through S.sub.1. When S.sub.1 is opened (e.g., S.sub.1 is non-conducting such that terminal 210 is electrically isolated from terminal 212) current does not flow through S.sub.1. Detector 200 includes second switch S.sub.2 which includes first terminal 214 coupled to first amplifier input 204 and includes second terminal 216 coupled to second amplifier input 206. S.sub.1 and S.sub.2 may be implemented using similar (or identical) components. In some example embodiments, S.sub.1 and S.sub.2 are implemented with transistors (e.g., n-channel transistors or NMOS transistors).

[0025] Detector 200 includes first bias current source I.sub.BIAS1 (e.g., around 40 micro-amps) coupled between first amplifier input 204 and common potential 150 (e.g., ground). Detector 200 includes second bias current source I.sub.BIAS2 (e.g., around 1 micro-amp) coupled between first terminal 210 of first switch S.sub.1 and common potential 150.

[0026] Detector 200 includes third switch S.sub.3 which includes first terminal 218 coupled to amplifier output 208 and includes second terminal 220. Detector 200 includes first transistor M.sub.1 (e.g., NMOS transistor) which includes first current terminal 222 (e.g., drain), second current terminal 224 (e.g., source) coupled to common potential 150, and control terminal 226 (e.g., gate) coupled to second terminal 220 of third switch S.sub.3.

[0027] Detector 200 includes fourth switch S.sub.4 which includes first terminal 240 coupled to system input 120 (and also coupled to detector input 124) and second terminal 242 coupled to first current terminal 222 of first transistor M.sub.1. In some example embodiments, S.sub.3 and/or S.sub.4 are implemented with transistors (e.g., NMOS transistors).

[0028] Detector 200 includes first capacitor C.sub.1 (e.g., around 5 pico-farads) coupled between second amplifier input 206 and common potential 150 and includes second capacitor C.sub.2 (e.g., around 15 pico-farads) coupled between control terminal 226 of first transistor M.sub.1 and common potential 150.

[0029] In some example embodiments, detector 200 includes second transistor M.sub.2 (e.g., NMOS transistor) which includes first current terminal 230 (e.g., drain) coupled to detector output 126 which is coupled to system output 122 via input buffer 108 (illustrated in FIG. 1). Second transistor M.sub.2 includes second current terminal 232 (e.g., source) coupled to common potential 150 and includes control terminal 234 (e.g., gate) coupled to second terminal 220 of third switch S.sub.3. Thus, control terminal 234 of M.sub.2 is coupled to control terminal 226 of M.sub.1. In some example embodiments, M.sub.1 and M.sub.2 are identical (or similar) to one another (e.g., M.sub.1 and M.sub.2 have the same characteristics).

[0030] A user may couple external reference resistor R.sub.EXT between system input 120 and voltage supply V.sub.CC in the supply path. As a result, voltage Av DD appears at system input 120.

[0031] In some example embodiments, detector 200 operates in three phases. The states of switches S.sub.1, S.sub.2, S.sub.3 and S.sub.4 in phases 1, 2 and 3 are shown in FIGS. 2A, 2B and 2C, respectively. FIG. 3 illustrates voltages generated in phases 1, 2 and 3. In FIG. 3, the x-axis represents time (in micro-seconds), and the y-axis represents voltage (in volts). In FIG. 3, graph 250 represents voltage A.sub.VDD at system input 120, graph 252 represents a voltage at first amplifier input 204, graph 254 represents a voltage at second amplifier input 206, and graph 256 represents a voltage across control terminal 226 and second terminal 224 of M.sub.1 (e.g., gate-to-source voltage V.sub.GS of M.sub.1).

[0032] In phase 1, illustrated in FIG. 2A, switches S.sub.1 and S.sub.2 are closed, and switches S.sub.3 and S.sub.4 are opened. Thus, first amplifier input 204 and second amplifier input 206 are connected. Since the voltage across first amplifier input 204 and second amplifier input 206 is zero, the voltage at amplifier output 208 is near zero. In phase 1, current conducts through S.sub.2 and, as a result, capacitor C.sub.1 is charged (e.g., C.sub.1 is charged to around 1.95V).

[0033] In phase 1, voltage A.sub.VDD (graph 250) is approximately 24V. Because in phase 1 first amplifier input 204 and second amplifier input 206 are shorted together, the voltage at first amplifier input 204 (graph 252) and the voltage at second amplifier input 206 (graph 254) are at the same potential (e.g., around 1.95V). Also, in phase 1, because switch S.sub.3 is opened and capacitor C.sub.2 is not charged, the voltage across control terminal 226 and second current terminal 224 of M.sub.1 (graph 256) is approximately zero.

[0034] In phase 2, illustrated in FIG. 2B, switches S.sub.1 and S.sub.2 are opened, and switches S.sub.3 and S.sub.4 continue to remain open. Because second current source I.sub.BIAS2 is disconnected from R.sub.INT, current through R.sub.INT falls (e.g., current through R.sub.INT falls by around 1 micro-amp), and, as a result, the voltage at first amplifier input 204 rises (e.g., voltage at first amplifier input 204 rises by around 500 mV). Because the voltage at second amplifier input 206 is held constant (as shown by graph 254 in FIG. 3) by capacitor C.sub.1 and the voltage at first amplifier input 204 rises above the voltage at second amplifier input 206 (e.g., the voltage at first amplifier input 204 is around 500 mV higher than voltage at second amplifier input 206), the voltage at amplifier output 208 rises (e.g., the voltage at amplifier output 208 rises to around A*500 mV, where A is the open loop gain of amplifier A.sub.1). Because the resistance of R.sub.INT (e.g., around 500K ohms) is much greater than the resistance of R.sub.EXT (e.g., between around 700 ohms to around 4K ohms), any change in the voltage across R.sub.EXT, due to the removal of I.sub.BIAS2, is negligible, and, as such, voltage A.sub.VDD remains approximately the same.

[0035] Thus, in phase 2, voltage A.sub.VDD (graph 250) remains approximately the same (e.g., around 24V); the voltage at first amplifier input (graph 252) rises by around 500 mV; and the voltage at second amplifier input (graph 254) is held constant. Because in phase 2, switch S.sub.3 remains open, capacitor C.sub.2 is not charged. Thus, the voltage across control terminal 226 and second current terminal 224 of M.sub.1 (graph 256) is approximately zero.

[0036] In phase 3, illustrated in FIG. 2C, switches S.sub.1 and S.sub.2 remain open but switches S.sub.3 and S.sub.4 are closed. Thus, amplifier output 208 is coupled to control terminal 226 of first transistor M.sub.1, and first current terminal 222 of M.sub.1 is coupled to detector input 124. As such, capacitor C.sub.2 is charged and the voltage across control terminal 226 and second current terminal 224 of M.sub.1 (e.g., the gate-to-source voltage of M.sub.1) rises which causes M.sub.1 to conduct. As current I.sub.M1 through M.sub.1 rises, current through R.sub.EXT also rises which causes voltage A.sub.VDD to fall. Transistor M.sub.1 and resistor R.sub.INT effectively form a negative feedback path from amplifier output 208 to first amplifier input 204, because as M.sub.1 draws more current voltage A.sub.VDD falls further. Since in phase 3, current through R.sub.INT remains constant (e.g., I.sub.BIAS1), the voltage at first amplifier input 204 falls as voltage A.sub.VDD falls. At steady state, the negative feedback path forces the voltage at first amplifier input 204 to fall (e.g., the voltage at first amplifier input 204 falls by 500 mV) to be approximately equal to the voltage at second amplifier input 206. Thus, voltage A.sub.VDD falls by an equal amount (e.g., voltage A.sub.VDD falls by around 500 mV) which causes the voltage across R.sub.EXT to rise by an equal amount (e.g., the voltage across R.sub.EXT rises by ?V which in some example embodiments is around 500 mV). Because the rise in the voltage (e.g., ?V) across R.sub.EXT is caused by current I.sub.M1 flowing through transistor M.sub.1, the resistance of R.sub.EXT may be determined from ?V and current I.sub.M1 flowing through M.sub.1. In some example embodiments, ?V can be determined by:

?V=(I.sub.BIAS2)*(R.sub.INT)(1)

[0037] where ?V is the rise in the voltage across R.sub.EXT.

[0038] Because current I.sub.M1 through transistor M.sub.1 is correlated to the voltage across control terminal 226 and second current terminal 224 of M.sub.1 (e.g., gate-to-source voltage V.sub.GS of M.sub.1), the voltage across control terminal 226 and second current terminal of M.sub.1 may be measured from the voltage across capacitor C.sub.2. Based on the voltage across capacitor C.sub.2, current I.sub.M1 through M.sub.1 is determined, and the resistance of R.sub.EXT is determined from I.sub.M1 and ?V.

[0039] In some example embodiments, transistors M.sub.1 and M.sub.2 are identical to one another (e.g., M.sub.1 and M.sub.2 have the same characteristics). Because control terminal 226 of M.sub.1 is coupled to control terminal 234 of M.sub.2, and second current terminal 224 of M.sub.1 and second current terminal 232 of M.sub.2 are both coupled to common potential 150, M.sub.1 and M.sub.2 conduct equal amount of current. Thus, current I.sub.OUT through M.sub.2 is equal to current I.sub.M1 through M.sub.1. In response to I.sub.OUT, input buffer 108 (shown in FIG. 1) draws I.sub.IN from sensor 132 (illustrated in FIG. 1) or provides I.sub.IN to sensor 132.

[0040] In phase 3, voltage A.sub.VDD (graph 250) falls by approximately 500 mV to around 23.5V, the voltage at first amplifier input (graph 252) falls by 500 mV to around 1.95V and the voltage at second amplifier input (graph 254) is held constant. Because in phase 3, switch S.sub.3 is closed, capacitor C.sub.2 is charged. Thus, the voltage across control terminal 226 and second terminal 224 of M.sub.1 (graph 256) rises (e.g., voltage rises to around 1.32V).

[0041] In some example embodiments, input buffer 108 may include an A/D converter (not shown in FIG. 1) which converts I.sub.OUT to digital codes. The digital codes may be provided to a micro-controller or a processor in input buffer 108 (not shown in FIG. 1) which draws or provides current I.sub.IN.

[0042] FIG. 4 illustrates detector 400 which is an example implementation of detector 200 of FIGS. 2A-2C. Portions of detector 400 of FIG. 4 are the same as detector 200 of FIGS. 2A-2C. As such, these similar features share the same reference numbers in FIGS. 4 and 2A-2C.

[0043] Detector 400 includes first bias current source I.sub.BIAS1 coupled between first amplifier input 204 and common potential 150. In some example embodiments, I.sub.BIAS1 is implemented with transistor M.sub.10 (e.g., NMOS transistor), switch S.sub.10 and capacitor C.sub.13. Transistor M.sub.10 includes first current terminal 402 (e.g., drain) coupled to first amplifier input 204, second current terminal 404 (e.g., source) coupled to common potential 150 and includes control terminal 406 (e.g., gate). Switch S.sub.10 includes first terminal 408 coupled to control terminal 406 of M.sub.10 and includes second terminal 410 coupled to first current terminal 402 of M.sub.10. Capacitor C.sub.13 is coupled between control terminal 406 of M.sub.1 and common potential 150. When switch S.sub.10 is closed, first current terminal 402 and control terminal 406 of M.sub.1 are coupled together, and, as such, M.sub.10 has a diode connection and capacitor C.sub.13 is charged. When switch S.sub.10 is opened, capacitor C.sub.13 maintains a constant voltage across control terminal 406 and second current terminal 404 of M.sub.10, and, as such, a constant current (e.g., I.sub.BIAS1) flows through M.sub.10. In some example embodiments, capacitor C.sub.13 is charged to a voltage level necessary to operate M.sub.10 in a saturation region so that a constant current (e.g., I.sub.BIAS1) flows through M.sub.10. In some example embodiments, switch S.sub.10 is periodically opened and closed to recharge capacitor C.sub.13, thus replenishing any charge which may be lost in capacitor C.sub.13 due to leakage. In some example embodiments, current source I.sub.BIAS2 may be implemented in similar or substantially similar manner as current source I.sub.BIAS1.

[0044] Detector 400 includes switch S.sub.4 which is implemented with transistor M.sub.11 (e.g., NMOS transistor) and switch S.sub.11. Transistor M.sub.11 includes first current terminal 420 (e.g., drain) coupled to detector input 124, second current terminal 422 (e.g., source) coupled to first current terminal 222 of transistor M.sub.1 and includes control terminal (e.g., gate). Switch S.sub.11 includes first terminal 426 coupled to voltage supply V.sub.DD and includes second terminal 428 coupled to control terminal 424 of M.sub.11. When switch S.sub.11 is closed, control terminal 424 of M.sub.11 is coupled to voltage supply V.sub.DD, and, as such, M.sub.11 conducts. Thus, first current terminal 222 of M.sub.1 is coupled to detector input 124 via M.sub.11. When switch S.sub.11 is opened, V.sub.DD is disconnected from control terminal 424 of M.sub.11, and, as such, M.sub.11 does not conduct, and first current terminal 222 of M.sub.1 is disconnected from detector input 124.

[0045] In some example embodiments, resistor R.sub.2 (e.g., around 50K ohms) is coupled between control terminal 226 of M.sub.1 and capacitor C.sub.2. Resistor R.sub.2 includes first terminal 430 coupled to control terminal 226 of M.sub.1 and includes second terminal 432. Capacitor C.sub.2 includes first terminal 434 coupled to second terminal 432 of resistor R.sub.2 and includes second terminal 436 coupled to common potential 150.

[0046] In some example embodiments, detector 400 includes capacitor C.sub.10 coupled between control terminal 234 of M.sub.2 and common potential 150. Detector 400 includes switch S.sub.12 which includes first terminal 440 coupled to first terminal 434 of capacitor C.sub.2 and includes second terminal 442 coupled to control terminal 234 of M.sub.2. When switch S.sub.12 is closed, control terminal 234 of M.sub.2 is coupled to control terminal 226 of M.sub.1 and capacitor C.sub.10 is charged. As such, transistor M.sub.2 conducts and draws current I.sub.OUT. The voltage across control terminal 226 and second current terminal 224 of M.sub.1 (e.g., gate-to-source voltage V.sub.GS of M.sub.1) is approximately at the same level as the voltage across control terminal 234 and second current terminal 232 of M.sub.2. Thus, M.sub.1 and M.sub.2 conduct the same amount of current (e.g., I.sub.OUT is equal to I.sub.M1). When switch S.sub.12 is opened, the voltage across control terminal 234 and second current terminal 232 of M.sub.2 is held at a constant voltage by capacitor C.sub.10, thus allowing transistor M.sub.2 to continue to conduct. In some example embodiments, switch S.sub.12 is periodically opened and closed to recharge capacitor C.sub.10, thereby replenishing any charge which may be lost in capacitor C.sub.10 due to leakage.

[0047] To protect detector 400 from an instantaneous surge in voltage supply V.sub.CC, surge resistor R.sub.SURGE (e.g., around 1K ohms) is coupled in series in the supply path. Resistor R.sub.SURGE includes first terminal 460 coupled to first terminal 138 of V.sub.CC and includes second terminal 462 coupled to second terminal 136 of resistor R.sub.EXT. Resistor R.sub.SURGE limits current flowing in the supply path. Capacitor C.sub.11 (e.g., around 1 micro-farad) is coupled between second terminal 462 of R.sub.SURGE and common potential 150. At high frequencies, capacitor C.sub.11 acts as a short circuit (e.g., capacitor C.sub.11 has a very low impedance at high frequencies), thereby providing a path for any instantaneous surge current to flow to ground. At low frequencies, capacitor C.sub.11 acts as an open circuit (e.g., capacitor C.sub.11 has a very high impedance at low frequencies), thereby coupling V.sub.CC to system input 120.

[0048] In some example embodiments, capacitor C.sub.12 (e.g., around 1 micro farad) is coupled between system input 120 and common potential 150. Capacitor C.sub.12 maintains a stable DC voltage (e.g., AVDD) at system input 120 by reducing AC ripple.

[0049] Because detectors 100, 200 and 400 are configured to sense and determine the resistance of an external resistor (e.g., R.sub.EXT) coupled in the supply path without requiring an additional pin in an IC, the number of pins in an IC package is reduced. As a result, the size of an IC package is reduced, thereby reducing fabrication cost of an IC package.

[0050] The circuits described herein may include one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and/or inductors), and/or one or more sources (such as voltage and/or current sources). The circuits may include only semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end-user and/or a third party. While some example embodiments may include certain elements implemented in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term integrated circuit means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.

[0051] In this description, the term couple may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal provided by device A. Also, in this description, a device that is configured to perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Furthermore, in this description, a circuit or device that includes certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, such as by an end-user and/or a third party.

[0052] As used herein, the terms terminal, node, interconnection, ball and pin are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.

[0053] While some example embodiments suggest that certain elements are included in an integrated circuit while other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term integrated circuit means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.

[0054] While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a metal-oxide-silicon FET (MOSFET) (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a bipolar junction transistor (BJTe.g. NPN or PNP), insulated gate bipolar transistors (IGBTs), and/or junction field effect transistor (JFET) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other type of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

[0055] While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term integrated circuit means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.

[0056] While certain components may be described herein as being of a particular process technology, these components may be exchanged for components of other process technologies. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available before the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series or in parallel between the same two nodes as the single resistor or capacitor. Also, uses of the phrase ground or ground terminal in this description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, about, approximately, or substantially preceding a value means +/?10 percent of the stated value, or, if the value is zero, a reasonable range of values around zero.