CAPACITANCE MEASUREMENT CIRCUIT

Abstract

A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.

Claims

1. A capacitance measurement circuit, comprising: a charge to voltage converter (CVC), comprising: an excitation signal generation circuit, arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor; a differential amplifier, having an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal, wherein the inverting input terminal is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor; a first switch circuit, coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier; and at least one first variable capacitor, wherein the first switch circuit and the at least one variable capacitor are connected in parallel at the inverting input terminal and the non-inverting output terminal of the differential amplifier.

2. The capacitance measurement circuit of claim 1, wherein an input offset voltage is at the inverting input terminal or the non-inverting input terminal of the differential amplifier, and the input offset voltage is reduced by the first switch circuit, the at least one first variable capacitor, and the differential amplifier.

3. The capacitance measurement circuit of claim 2, wherein the first switch circuit is controlled by a control signal, the control signal and the excitation signal are in-phase, and the CVC further comprises: an acquisition circuit, arranged to: in response to the first switch circuit being closed, acquire a first voltage difference between the inverting output terminal and the non-inverting output terminal of the differential amplifier; and in response to the first switch circuit being open, acquire a second voltage difference between the inverting output terminal and the non-inverting output terminal of the differential amplifier; and a subtraction circuit, arranged to subtract the first voltage difference from the second voltage difference, to reduce the input offset voltage and generate an output voltage of the CVC.

4. The capacitance measurement circuit of claim 3, wherein the output voltage is proportional to the sensing capacitance value.

5. The capacitance measurement circuit of claim 1, wherein the differential amplifier is a chopper amplifier.

6. The capacitance measurement circuit of claim 1, wherein a supply voltage is supplied to the CVC, and a high voltage level of the excitation signal is different from the supply voltage.

7. The capacitance measurement circuit of claim 6, wherein an output voltage of the CVC is insensitive to the supply voltage.

8. The capacitance measurement circuit of claim 1, wherein a capacitance value of one of multiple capacitors is selected as a capacitance value of the at least one first variable capacitor according to the sensing capacitance value, to make a ratio of the sensing capacitance value to said one of multiple capacitance values be a fixed value.

9. The capacitance measurement circuit of claim 1, wherein the excitation signal generation circuit comprises: a clock generator, arranged to generate a clock signal; and a slew rate limiter, arranged to perform a slew rate limitation operation upon the clock signal to generate the excitation signal, and connect the excitation signal to the first terminal of the capacitance sensor.

10. The capacitance measurement circuit of claim 9, wherein the CVC further comprises: a parasitic capacitance cancellation circuit, arranged to reduce a parasitic capacitance value from the sensing capacitance value.

11. The capacitance measurement circuit of claim 10, wherein the parasitic capacitance cancellation circuit comprises: an inverter, coupled to the slew rate limiter, and arranged to invert the excitation signal to generate an inverted excitation signal; and at least one second variable capacitor, coupled to an output terminal of the inverter and the inverting input terminal of the differential amplifier, wherein a capacitance value of one of multiple capacitors that is equal to the parasitic capacitance value is selected as a capacitance value of the at least one second variable capacitor, to perform parasitic capacitance reduction according to the inverted excitation signal.

12. The capacitance measurement circuit of claim 10, wherein the parasitic capacitance cancellation circuit comprises: at least one second variable capacitor, coupled between the slew rate limiter and the non-inverting input terminal of the differential amplifier, and arranged to perform parasitic capacitance reduction.

13. The capacitance measurement circuit of claim 1, wherein the CVC further comprises: a parasitic capacitance cancellation circuit, arranged to reduce a parasitic capacitance value from the sensing capacitance value.

14. The capacitance measurement circuit of claim 13, wherein the parasitic capacitance cancellation circuit comprises: a second switch circuit, having a first terminal and a second terminal, wherein the first terminal of the second switch circuit is arranged to receive a high voltage level of the excitation signal, the second switch circuit is controlled by a first control signal for connecting the high voltage level of the excitation signal to the second terminal of the second switch circuit, and the first control signal and the excitation signal are out-of-phase; a third switch circuit, having a first terminal and a second terminal, wherein the first terminal of the third switch circuit is arranged to receive a low voltage level of the excitation signal, the second switch circuit is controlled by a second control signal for connecting the low voltage level of the excitation signal to the second terminal of the third switch circuit, and the second control signal and the excitation signal are in-phase; and at least one second variable capacitor, coupled to the second terminal of the second switch circuit, the second terminal of the third switch circuit, and the inverting input terminal of the differential amplifier, wherein a capacitance value of one of multiple capacitors that is equal to the parasitic capacitance value is selected as a capacitance value of the at least one second variable capacitor, to perform parasitic capacitance reduction.

15. The capacitance measurement circuit of claim 1, wherein the CVC is arranged to generate an output voltage according to the sensing capacitance value; and the capacitance measurement circuit is a capacitance to digital converter (CDC), and further comprises: an analog to digital converter (ADC), arranged to convert the output voltage into a digital pulse stream.

16. The capacitance measurement circuit of claim 15, wherein the ADC is a sigma-delta ADC, and the sigma-delta ADC at least comprises: a subtraction circuit, arranged to receive the output voltage from the CVC, and subtract a feedback signal from the output voltage, to generate a processed signal; an integrator circuit, coupled to the subtraction circuit, and arranged to integrate the processed signal to generate the digital pulse stream; and a feedback circuit, coupled to the integrator circuit and the subtraction circuit, and arranged to derive the feedback signal from the digital pulse stream, and transmit the feedback signal to the subtraction circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 is a diagram illustrating a charge to voltage converter according to a first embodiment of the present invention.

[0009] FIG. 2 is a diagram illustrating a charge to voltage converter according to a second embodiment of the present invention.

[0010] FIG. 3 is a diagram illustrating a charge to voltage converter according to a third embodiment of the present invention.

[0011] FIG. 4 is a diagram illustrating a charge to voltage converter according to a fourth embodiment of the present invention.

[0012] FIG. 5 is a diagram illustrating a capacitance measurement circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0013] FIG. 1 is a diagram illustrating a charge to voltage converter (CVC) 100 according to a first embodiment of the present invention. As shown in FIG. 1, the CVC 100 may include an excitation signal generation circuit 102, a differential amplifier 104, a switch circuit 106, at least one variable capacitor 108, a parasitic capacitance cancellation circuit (for brevity, labeled as PC cancellation circuit in FIG. 1) 110, an acquisition circuit 112, and a subtraction circuit 114, and a supply voltage VDD may be supplied to the CVC 100. In addition, there is a capacitance sensor 120 external to the CVC 100, wherein the capacitance sensor 120 has a two-terminal connection architecture. The capacitance sensor 120 may act as a variable component where the dynamic range of the sensing capacitance value Cs will be changed according to the external environment. The CVC 100 may be arranged to generate an output voltage V.sub.OUT according to the sensing capacitance value C.sub.s.

[0014] The excitation signal generation circuit 102 may include a clock generator 103 and a slew rate limiter 105. The clock generator 103 may be arranged to generate a clock signal O.sub.R. In this embodiment, the clock signal ?.sub.R may be a square wave with 32 kHz, wherein a high voltage level of the clock signal ?.sub.R may be the supply voltage VDD, and a low voltage level of the clock signal ?.sub.R may be a reference voltage (e.g. a ground voltage GND). Under a condition that the clock signal ?.sub.R is directly connected to the capacitance sensor 120 for capacitance sensing, the square wave rises and falls sharply between the high voltage level and the low voltage level, which may cause the electromagnetic interference (EMI) and interfere the electronic components nearby. In addition, if the supply voltage VDD is supplied by a battery, the supply voltage VDD may drop during the long term operation of the CVC 100, and a voltage signal that is arranged to charge and discharge the sensing capacitance 120 through the clock signal ?.sub.R (e.g. the high voltage level of the clock signal ?.sub.R) may not be a fixed value, which may cause the output voltage V.sub.OUT generated by the CVC 100 to change with the supply voltage VDD. To solve this issue, the slew rate limiter 105 may be arranged to perform a slew rate limitation operation upon the clock signal ?.sub.R, to generate an excitation signal EXC1 to a first terminal of the capacitance sensor 120.

[0015] In this embodiment, the CVC 100 may further include a low dropout (LDO) regulator 107. The LDO regulator 107 may be arranged to regulate the supply voltage VDD, and generate an excitation voltage V.sub.EXT+ that is different from the supply voltage VDD and another excitation voltage V.sub.EXT? that is different from the ground voltage GND and lower than the excitation voltage V.sub.EXT+, wherein the excitation voltages V.sub.EXT+ and V.sub.EXT? may be transmitted to the slew limiter 105, and the slew limiter 105 may be arranged to perform a slew rate limitation operation upon the clock signal ?.sub.R (e.g. limit the high voltage level of the clock signal ?.sub.R as the excitation voltage V.sub.EXT+, and limit the low voltage level of the clock signal ?.sub.R as the excitation voltage V.sub.EXT?), to generate the excitation signal EXC1. In this way, the output voltage V.sub.OUT of the CVC 100 is insensitive to the supply voltage VDD.

[0016] The differential amplifier 104 has an inverting input terminal (labeled as ? in FIG. 1), a non-inverting input terminal (labeled as + in FIG. 1), a non-inverting output terminal (i.e. a terminal from which a first differential output voltage V.sub.OUT+ is output), and an inverting output terminal (i.e. a terminal from which a second differential output voltage V.sub.OUT? is output), wherein the inverting input terminal may be arranged to receive the sensing capacitance value C.sub.s from a second terminal of the capacitance sensor 120, the non-inverting input terminal may be coupled to a common-mode voltage (labeled as VCM in FIG. 1), and the output voltage V.sub.OUT is a voltage difference between the inverting output terminal and the non-inverting output terminal of the differential amplifier 104 (i.e. V.sub.OUT=V.sub.OUT+?V.sub.OUT?). The switch circuit 106 may be coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier 104, wherein the switch circuit 106 is controlled by a control signal that is in-phase with the excitation signal EXC1. For example, the control signal may be the clock signal ?.sub.R. It is assumed that in response to the clock signal ?.sub.R being at the high voltage level (i.e. the supply voltage VDD), the switch circuit 106 is closed. In response to the clock signal ?.sub.R being at the low voltage level (i.e. the ground voltage GND), the switch circuit 106 is open. In addition, the switch circuit 106 and the at least one variable capacitor 108 may be connected in parallel at the inverting input terminal and the non-inverting output terminal of the differential amplifier 104.

[0017] The configuration between the switch circuit 106, the at least one variable capacitor 108, and the differential amplifier 104 may be arranged to reduce/cancel an input offset voltage V.sub.os at the inverting input terminal of the differential amplifier 104, but the present invention is not limited thereto. In some embodiments, the input offset voltage V.sub.os is at the non-inverting terminal of the differential amplifier 104. In detail, under a condition that the switch circuit 106 is closed, a first voltage difference V.sub.OUT1 between the inverting output terminal and the non-inverting output terminal of the differential amplifier 104 (i.e. V.sub.OUT1=V.sub.OUT+?V.sub.OUT?) may be obtained by an equation expressed as follows:

[00001]$\left(\frac{V_{\mathrm{OUT}1}}{-A}\right)+V_{\mathrm{OS}}=V_{\mathrm{OUT}1}$

wherein A is a gain of the differential amplifier 104, and V.sub.os is the input offset voltage V.sub.os. The above equation may be simplified as follows:

[00002]$V_{\mathrm{OUT}1}=\left[\frac{A}{\left(1+A\right)}\right]V_{\mathrm{OS}}?V_{\mathrm{OS}}$

wherein the first voltage difference V.sub.OUT1 is approximately equal to the input offset voltage V.sub.os.

[0018] Under a condition that the switch circuit 106 is open, a second voltage difference V.sub.OUT2 between the inverting output terminal and the non-inverting output terminal of the differential amplifier 104 (i.e. V.sub.OUT2=V.sub.OUT+?V.sub.OUT?) may be obtained by an equation expressed as follows:

C.sub.S*(V.sub.OS?V.sub.EXT+)=C.sub.i*(V.sub.OS?V.sub.OUT2)+C.sub.S*(V.sub.OS?V.sub.EXT?)

wherein C.sub.s is the sensing capacitance value C.sub.s, V.sub.os is the input offset voltage V.sub.os, V.sub.EXT+ is the high voltage level of the excitation signal EXC1, C.sub.i is a capacitance value of the at least one variable capacitor 108, and V.sub.EXT? is the low voltage level of the excitation signal EXC1. The above equation may be simplified as follows:

[00003]$V_{\mathrm{OUT}2}=\left(V_{\mathrm{EXT}+}-V_{\mathrm{EXT}-}\right)*\frac{C_S}{C_i}+V_{\mathrm{OS}}$

[0019] In response to the switch circuit 106 being closed, the acquisition circuit 112 may be arranged to acquire the first voltage difference V.sub.OUT1. In response to the switch circuit 106 being open, the acquisition circuit 112 may be arranged to acquire the second voltage difference V.sub.OUT2. The subtraction circuit 114 may be coupled to the acquisition circuit 112, and may be arranged to subtract the first voltage difference V.sub.OUT1 from the second voltage difference V.sub.OUT2, to reduce/cancel the input offset voltage V.sub.os and generate the output voltage V.sub.OUT of the CVC 100 (i.e. V.sub.OUT=V.sub.OUT2?V.sub.OUT1). The output voltage V.sub.OUT may be expressed by the following equation:

[00004]$V_{\mathrm{OUT}}=\left(V_{\mathrm{EXT}+}-V_{\mathrm{EXT}-}\right)*\frac{C_S}{C_i}$

wherein the output voltage V.sub.OUT is proportional to the sensing capacitance value C.sub.s, and the output voltage V.sub.OUT is insensitive to the supply voltage VDD.

[0020] It should be noted that, the differential amplifier 104 may be a chopper amplifier, that is, the differential amplifier 104 may be equipped with function of several pairs of switches. In addition, the maximum value of the sensing capacitance value C.sub.s obtained by the capacitance sensor 120 may vary according to the operation environment. Under a condition that a capacitance value C.sub.i of the at least one variable capacitor 108 is a fixed value, a full-load output voltage V.sub.OUT_FULL of the CVC 100 may change with the maximum value of the sensing capacitance value C.sub.s. To solve this issue, the at least one variable capacitor 108 may have multiple capacitance values to be selected. For example, a register (not shown) may be arranged to set up the at least one variable capacitor 108 to select one of the multiple capacitance values as the capacitance value C.sub.i of the at least one variable capacitor 108, to make a ratio of the sensing capacitance value C.sub.s to said one of multiple capacitance values be a fixed value. In this way, by adjusting the capacitance value C.sub.i of the at least one variable capacitor 108, a dynamic range of the external capacitor can be adjusted.

TABLE-US-00001 TABLE 1 C.sub.s C.sub.i V.sub.OUT.sub..sub.FULL 4 pF 13.728 pF ?V * 0.2914 2 pF 6.864 pF ?V * 0.2914 1 pF 3.432 pF ?V * 0.2914 0.5 pF 1.716 pF ?V * 0.2914

[0021] Table 1 illustrates an example of selection of the multiple capacitance values by the at least one variable capacitor 108 according to the sensing capacitance value C.sub.s. It is assumed that the maximum value of the sensing capacitance value C.sub.s may be 4 pF, 2 pF, 1 pF, or 0.5 pF, and the multiple capacitance values that may be selected as the capacitance value C.sub.i of the at least one variable capacitor 108 may be 13.728 pF, 6.864 pF, 3.432 pF, and 1.716 pF. Under a condition that the maximum value of the sensing capacitance value C.sub.s is 4 pF, 13.728 pF may be selected as the capacitance value C.sub.i of the at least one variable capacitor 108, to make the ratio of the sensing capacitance value C.sub.s to the capacitance value C.sub.i be 0.2914 (i.e.

[00005]$\frac{C_S}{C_i}=0.2914),$

and the full-load output voltage V.sub.OUT_FULL may be ?V*0.2914, wherein ?V is a voltage difference between the high voltage level of the excitation signal EXC1 and the low voltage level of the excitation signal EXC1 (i.e. ?V=V.sub.EXT+?V.sub.EXT?). Under a condition that the maximum value of the sensing capacitance value C.sub.s is 2 pF, 6.864 pF may be selected as the capacitance value C.sub.i of the at least one variable capacitor 108, to make the ratio of the sensing capacitance value C.sub.s to the capacitance value C.sub.i be 0.2914 (i.e.

[00006]$\frac{C_S}{C_i}=0.2914),$

and the full-load output voltage V.sub.OUT_FULL may be ?V*0.2914. Under a condition that the maximum value of the sensing capacitance value C.sub.s is 1 pF, 3.432 pF may be selected as the capacitance value C.sub.i of the at least one variable capacitor 108, to make the ratio of the sensing capacitance value C.sub.s to the capacitance value C.sub.i be 0.2914 (i.e.

[00007]$\frac{C_S}{C_i}=0.2914),$

and the full-load output voltage V.sub.OUT_FULL may be ?V*0.2914. Under a condition that the maximum value of the sensing capacitance value C.sub.s is 0.5 pF, 1.716 pF may be selected as the capacitance value C.sub.i of the at least one variable capacitor 108, to make the ratio of the sensing capacitance value C.sub.s to the capacitance value C.sub.i be 0.2914 (i.e.

[00008]$\frac{C_S}{C_i}=0.2914),$

and the full-load output voltage V.sub.OUT_FULL may be ?V*0.2914.

[0022] The parasitic capacitance cancellation circuit 110 may be arranged to reduce/cancel a parasitic capacitance value C.sub.P from the sensing capacitance value C.sub.s. In this embodiment, the parasitic capacitance cancellation circuit 110 may be coupled between the slew rate limiter 105 and the inverting input terminal of the differential amplifier 104. In some embodiment, the parasitic capacitance cancellation circuit 110 may be coupled between the slew rate limiter 105 and the non-inverting input terminal of the differential amplifier 104 (i.e. the non-inverting input terminal of the differential amplifier 104 may be modified to be coupled to the parasitic capacitance cancellation circuit 110). In some embodiment, the parasitic capacitance cancellation circuit 110 may only be coupled to the inverting input terminal of the differential amplifier 104.

[0023] The implementation of the parasitic capacitance cancellation circuit 110 may be illustrated in FIG. 2, FIG. 3, and FIG. 4. FIG. 2 is a diagram illustrating a CVC 200 according to a second embodiment of the present invention. The difference between the CVC 100 shown in FIG. 1 and the CVC 200 shown in FIG. 2 is that the parasitic capacitance cancellation circuit 110 of the CVC 100 may be implemented by an inverter 202 and at least one variable capacitor 204 of the CVC 200. As shown in FIG. 2, the inverter 202 may be coupled to the slew rate limiter 105, and may be arranged to invert the excitation signal EXC1 to generate an inverted excitation signal EXC2. The at least one variable capacitor 204 may be coupled to the inverter 202 and the inverting input terminal of the differential amplifier 104, and may have multiple capacitance values to be selected. For example, the at least one variable capacitor 204 can be configured as a certain value (e.g. a capacitance value selected from the multiple capacitance values) that is equal to the parasitic capacitance value C.sub.P, to perform parasitic capacitance reduction/cancellation according to the inverted excitation signal EXC2. The output voltage V.sub.OUT may be expressed by the following equation:

[00009]$V_{\mathrm{OUT}}=\left(V_{\mathrm{EXT}+}-V_{\mathrm{EXT}-}\right)*\frac{C_S-C_{\mathrm{DAC}}}{C_i}$

wherein C.sub.DAC is the capacitance value of the at least one variable capacitor 204, and the parasitic capacitance value C.sub.P from the sensing capacitance value C.sub.s can be reduced/canceled by the capacitance value C.sub.DAC of the at least one variable capacitor 204.

[0024] FIG. 3 is a diagram illustrating a CVC 300 according to a third embodiment of the present invention. The difference between the CVC 100 shown in FIG. 1 and the CVC 300 shown in FIG. 3 is that the parasitic capacitance cancellation circuit 110 of the CVC 100 may be implemented by at least one variable capacitor 302 of the CVC 300. As shown in FIG. 3, the at least one variable capacitor 302 may be coupled between the slew limiter 105 and the non-inverting input terminal of the differential amplifier 104 (i.e. the non-inverting input terminal of the differential amplifier 104 may be modified to be coupled to the at least one variable capacitor 302), and may have multiple capacitance values to be selected. For example, a register (not shown) may be arranged to set up the at least one variable capacitor 302 to select one of the multiple capacitance values that is equal to the parasitic capacitance value C.sub.P as a capacitance value of the at least one variable capacitor 302, to perform parasitic capacitance reduction/cancellation. For brevity, similar descriptions for this embodiment are not repeated in detail here.

[0025] FIG. 4 is a diagram illustrating a CVC 400 according to a fourth embodiment of the present invention. The difference between the CVC 100 shown in FIG. 1 and the CVC 400 shown in FIG. 4 is that the parasitic capacitance cancellation circuit 110 of the CVC 100 may be implemented by two switch circuits 402 and 404 and at least one variable capacitor 406 of the CVC 400. As shown in FIG. 4, the switch circuit 402 has a first terminal and a second terminal, wherein the first terminal of the switch circuit 402 may be arranged to receive the excitation voltage V.sub.EXT+ (which is the high voltage level of the excitation signal EXC1) from the LDO regulator 107, the switch circuit 402 is controlled by a control signal ?.sub.R for connecting the excitation voltage V.sub.EXT+ to the second terminal of the switch circuit 402, and the control signal ?.sub.R and the excitation signal EXC1 are out-of-phase. It is assumed that in response to the control signal ?.sub.R being at the high voltage level (i.e. the excitation signal EXC1 is at the low voltage level), the switch circuit 402 is closed. In response to the control signal ?.sub.R being at the low voltage level (i.e. the excitation signal EXC1 is at the high voltage level), the switch circuit 402 is open.

[0026] The switch circuit 404 has a first terminal and a second terminal, wherein the first terminal of the switch circuit 404 may be arranged to receive the excitation voltage V.sub.EXT? (which is the low voltage level of the excitation signal EXC1) from the LDO regulator 107, and the switch circuit 404 is controlled by a control signal that is in-phase with the excitation signal EXC1 (e.g. the clock signal ?.sub.R) for connecting the excitation voltage V.sub.EXT? to the second terminal of the switch circuit 404. It is assumed that in response to the clock signal ?.sub.R being at the high voltage level (i.e. the excitation signal EXC1 is also at the high voltage level), the switch circuit 404 is closed. In response to the clock signal ?.sub.R being at the low voltage level (i.e. the excitation signal EXC1 is also at the low voltage level), the switch circuit 404 is open.

[0027] The at least one variable capacitor 406 may be coupled to the second terminal of the switch circuit 402, the second terminal of the switch circuit 404, and the inverting terminal of the differential amplifier 104, and may have multiple capacitance values to be selected. For example, a register (not shown) may be arranged to set up the at least one capacitor 406 to select one of the multiple capacitance capacitor values that is equal to the parasitic capacitance value C.sub.P as a capacitance value C.sub.DAC of the at least one capacitor 406, to perform parasitic capacitance reduction/cancellation. For brevity, similar descriptions for this embodiment are not repeated in detail here.

[0028] FIG. 5 is a diagram illustrating a capacitance measurement circuit 500 according to an embodiment of the present invention, wherein the capacitance measurement circuit 500 is a capacitance to digital converter (CDC). As shown in FIG. 5, the capacitance measurement circuit 500 may include the CVC 100 shown in FIG. 1 and an analog to digital converter (ADC) 510, wherein the ADC 510 may be arranged to convert the output voltage V.sub.OUT into a digital pulse stream D_S. In this embodiment, the ADC 510 is a sigma-delta ADC, but the present invention is not limited thereto. In practice, any ADC architecture that is capable of converting the output voltage V.sub.OUT into the digital pulse stream D_S may be employed by the ADC 510. These alternative designs all fall within the scope of the present invention.

[0029] The ADC 510 may at least include a subtraction circuit 502, an integrator circuit 504, and a feedback circuit 506. The subtraction circuit 502 may be arranged to receive the output voltage V.sub.OUT from the CVC 100 (more particularly, the subtraction circuit 114), and subtract a feedback signal F_S from the output voltage V.sub.OUT, to generate a processed signal P_S. The integrator circuit 504 may be coupled to the subtraction circuit 502, and may be arranged to integrate the processed signal P_S to generate the digital pulse stream D_S. The feedback circuit 506 may be coupled to the integrator circuit 504 and the subtraction circuit 502, and may be arranged to derive the feedback signal F_S from the digital pulse stream D_S, and transmit the feedback signal F_S to the subtraction circuit 502. Since the sigma-delta ADC is well known to those skilled in the art, the details of the ADC 510 will be omitted for brevity.

[0030] In summary, in the CVC 100 of the present invention, the differential amplifier 104 within the CVC 100 will not have the input offset voltage problem by the configuration between the differential amplifier 104, the switch circuit 106, and the at least one variable capacitor 108. Under a condition that the sensing capacitance value C.sub.s sensed by the capacitance sensor 120 includes a parasitic capacitance value C.sub.P, the parasitic capacitance value C.sub.P can be eliminated by the parasitic capacitance cancellation circuit 110. In addition, the CVC 100 is a single-terminal input and double-terminal output configuration through the differential amplifier 104, which can increase the design flexibility, and the output voltage V.sub.OUT generated by the CVC 100 will not vary with the supply voltage VDD by the slew rate limiter 105.

[0031] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.