SEMICONDUCTOR DEVICE
20230215764 · 2023-07-06
Assignee
Inventors
Cpc classification
H01L27/0292
ELECTRICITY
H01L29/49
ELECTRICITY
H01L21/76895
ELECTRICITY
International classification
H01L21/768
ELECTRICITY
H01L21/3205
ELECTRICITY
H01L23/482
ELECTRICITY
H01L29/49
ELECTRICITY
Abstract
A semiconductor device including an interconnect. The interconnect is arranged to transfer current from one terminal to another, and the interconnect includes a first layer including a plurality of interweaved fingers, and each of the interweaved fingers varies in width in a direction of propagation current thereby resulting in a difference of resistance within each of the interweaved fingers in the direction of propagation of current; a second layer arranged below the first layer. The second layer compensates for the difference of resistance in the first layer.
Claims
1. A semiconductor device comprising an interconnect, wherein the interconnect is arranged to transfer current from one terminal to another, wherein the interconnect comprises: a first layer comprising a plurality of interweaved fingers, wherein each of the interweaved fingers varies in width in a direction of propagation of current thereby resulting in a difference of resistance in each of the interweaved fingers in the direction of propagation of current; a second layer arranged below the first layer, wherein the second layer is arranged to compensate the difference of resistance in the first layer.
2. The semiconductor device according to claim 1, wherein the second layer comprises a plurality of strips arranged perpendicular to the direction of propagation of current, wherein the width of the strips vary to compensate the resistance difference in the first layer.
3. The semiconductor device according to claim 1, wherein the second layer has a physical parameter that is varied in the direction of propagation of current to compensate the resistance difference in the first layer.
4. The semiconductor device according to claim 1, wherein both the first layer and the second layer are metallic.
5. The semiconductor device according to claim 1, wherein the plurality of interweaved fingers in the first layer has a pyramidal shape.
6. The semiconductor device according to claim 1, wherein the semiconductor device is selected from the group consisting of: an ESD diode, a TVS diode, and a lateral MOSFET.
7. The semiconductor device according to claim 2, wherein the second layer has a physical parameter that is varied in the direction of propagation of current to compensate the resistance difference in the first layer.
8. The semiconductor device according to claim 2, wherein both the first layer and the second layer are metallic.
9. The semiconductor device according to claim 2, wherein the plurality of interweaved fingers in the first layer has a pyramidal shape.
10. The semiconductor device according to claim 2, wherein the semiconductor device is selected from the group consisting of: an ESD diode, a TVS diode, and a lateral MOSFET.
11. The semiconductor device according to claim 3, wherein both the first layer and the second layer are metallic.
12. The semiconductor device according to claim 3, wherein the plurality of interweaved fingers in the first layer has a pyramidal shape.
13. The semiconductor device according to claim 3, wherein the semiconductor device is selected from the group consisting of: an ESD diode, a TVS diode, and a lateral MOSFET.
14. The semiconductor device according to claim 4, wherein the plurality of interweaved fingers in the first layer has a pyramidal shape.
15. The semiconductor device according to claim 4, wherein the semiconductor device is selected from the group consisting of: an ESD diode, a TVS diode, and a lateral MOSFET.
16. The semiconductor device according to claim 5, wherein the semiconductor device is selected from the group consisting of: an ESD diode, a TVS diode, and a lateral MOSFET.
Description
BRIEF DESCRIPTION OF DRAWINGS
[0027]
[0028]
[0029]
[0030]
[0031]
[0032]
[0033]
DETAILED DESCRIPTION
[0034] The ensuing description above provides preferred exemplary embodiment(s) only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the ensuing description of the preferred exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing a preferred exemplary embodiment of the disclosure, it being understood that various changes may be made in the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of the disclosure.
[0035] Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” As used herein, the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, electromagnetic, or a combination thereof. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
[0036] The teachings of the technology provided herein can be applied to other systems, not necessarily the system described below. The elements and acts of the various examples described below can be combined to provide further implementations of the technology. Some alternative implementations of the technology may include not only additional elements to those implementations noted below, but also may include fewer elements.
[0037] These and other changes can be made to the technology in light of the following detailed description. While the description describes certain examples of the technology, and describes the best mode contemplated, no matter how detailed the description appears, the technology can be practiced in many ways. Details of the system may vary considerably in its specific implementation, while still being encompassed by the technology disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the technology should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the technology with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the technology to the specific examples disclosed in the specification, unless the Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the technology encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the technology under the claims.
[0038] The present disclosure is described in conjunction with the appended figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
[0039] In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
[0040]
[0041] Since the fingers are of equal width, they offer a uniform resistance to the current flow path. This is further understood from the schematic model 10 of the device as shown in
[0042] The skilled person understands that irrespective of the current flow path from electrode 5 to electrode 3, the total path resistance for each path remains the same. Thus, although current flow will be uniform over all paths, the amount of current that can be carried is limited by the width at the base of the finger.
[0043]
[0044]
[0045] For example, when considering finger 23 of electrode 5, the resistance 32, 34, 36, 38 are in an increasing order of size. This implies that resistance 38 is higher than resistance 36, which is, in turn, higher than resistance 34, which is higher than resistance 32. This also corresponds with the structure of the finger since it has wide base corresponding with a low resistance 32 and a narrow top corresponding to a high resistance 38. A similar consideration can be made for resistances 31, 33, 35 and 37 of finger 21 of electrode 3.
[0046] It is further understood that the two fingers 21 and 23 are identical in size, and differ only in orientation. Hence, the resistances 31 and 32 are equal, resistances 33 and 34 are equal, resistances 35 and 36 are equal and finally resistances 37 and 38 are equal. For example, Resistance 31 = 32 = 0.5 Ω (Ohms) [0047] Resistance 33 = 34 = 1 Ω (Ohms) [0048] Resistance 35 = 36 = 2 Ω (Ohms) [0049] Resistance 37 = 38 = 4 Ω (Ohms)
[0050] The skilled person understands that these values used are merely exemplary and do not necessarily reflect the actual values in a structure. In such a structure as shown in
[0055] Although four paths have been described for this exemplary model, it is seen that paths A and D offer a greater resistance (8 Ohms) compared to paths B and C (5 Ohms). This would mean that current would primarily flow through the middle of the structure, and not flow on the outer periphery of the structure. This would result in a device without a uniform current distribution.
[0056]
[0057] The width of the strips in the bottom layer is smaller in the center than in the outer regions. For example, the width of strip 45 is smaller than the width of strip 43. This would mean that the resistance of the strip 45 is much higher than that of the strip 43. This difference in resistance compensates for the difference of resistance in the top layer. As a result, uniform distribution of current can be achieved. The skilled person understands that measures other than the width of the strips in the second layer could be used for resistance compensation. As an example, the inner resistance of the silicon structure, modelled as a diode, might be adjusted. Alternately, parameters or properties other than the width of the strip could be adjusted to achieve the required resistance compensation. For example, materials of different resistivity could be employed so as to achieve the requires resistance compensation.
[0058] The skilled person also understands that the values of the resistance in the bottom layer may be chosen such that they compensate the resistance differences in the top metal layer. As a result, all current paths have the same resistance and the total current capacity is maximized. This is further elaborated with the schematic model 50 shown in
[0059] The model 50 is similar to the model 30 shown in
[0060] As an example, resistances 52 in block 51 and resistances 61 in block 60 are assumed to have a value of 0.2 Ohms each. Resistances 55 in block 54 and resistances 58 in block 57 are assumed to have a value of 0.9 Ohms each. This corresponds with the physical reality since the width of the strips in the center is much smaller than the width of the strips at the outer peripheries. This results in a higher resistance in the center, and hence the higher value for resistances 55 and 58.
[0061] At least four current paths E - H can be observed. The path and the total resistance values are described here below. The skilled person understands that although multiple current paths are possible within each of the blocks 51, 54, 57 and 60, each of these paths offer the same amount of resistance. Hence, for the purpose of simplicity, these alternatives are considered as one single path. [0062] Path E: 32 - 60 - 37 - 35 - 33 - 31; Total resistance = 9.5 Ω (Ohms) [0063] Path F: 32 - 34 - 57 - 35 - 33 - 31; Total resistance = 9.5 Ω (Ohms) [0064] Path G: 32 - 34 - 36 - 54 - 33 - 31; Total resistance = 9.5 Ω (Ohms) [0065] Path H: 32 - 34 - 36 - 38 - 51 - 31; Total resistance = 9.5 Ω (Ohms)
[0066] Thus, with these chosen values, it is seen that all four paths offer the same resistance and hence current is equally likely to flow through each of these available paths. As a result, current distribution will be uniform resulting in a higher current carrying capacity.
[0067]