SEMICONDUCTOR DEVICE INCLUDING MOSFET REGION AND DIODE REGION AND MANUFACTURING METHOD THEREOF

Abstract

Disclosed are a semiconductor device (1) including a MOSPET region and an integrated diode region, and a manufacturing method thereof. More particularly, a semiconductor device (1) including a silicon carbide (SiC) MOSPET region and an integrated Schottky bather diode that reduce forward voltage drop (Vf), device area, and switching oscillation resulting from parasitic inductance are disclosed.

Claims

1. A semiconductor device, comprising: a substrate including a MOSFET region and a Schottky bather diode (SBD) region; a lightly doped second conductivity type drift region on the substrate in the MOSFET region and the SBD region; a first conductivity type well in the drift region in the MOSFET region; a heavily doped second conductivity type source in the well; a gate in the MOSFET region and comprising a gate insulating film on the drift region and a gate electrode on the gate insulating film; and a JFET region in the drift region and below the gate.

2. The semiconductor device of claim 1, wherein the MET region surrounds or is in contact with one sidewall and a lowermost surface of the well.

3. The semiconductor device of claim 1, further comprising: a first high concentration impurity region in contact with the source and the well in the MOSFET region and the JFET region, the first high concentration impurity region having a first conductive type; and a first ohmic contact at least partially in contact with the source and the first high concentration impurity region.

4. The semiconductor device of claim 3, further comprising a second high concentration impurity region in the drift region in the SBD region, the second high concentration impurity region having the first conductivity type.

5. The semiconductor device of claim 4, further comprising a second ohmic contact on the second high concentration impurity region in the SBD region.

6. The semiconductor device of claim 4, further comprising a contact region on the drift region in the SBD region.

7. A semiconductor device, comprising: a substrate having a plurality of MOSPET regions and one or more Schottky bather diode (SBD) regions; a lightly doped second conductivity type drift region on the substrate in the MOSPET regions and the one or more SBD regions; and a plurality of unit cells having a first substantially hexagonal shape and at least a partial honeycomb structure, the unit cells comprising the MOSPET regions; wherein the one or more SBD regions are between at least two of the unit cells and have a second substantially hexagonal shape.

8. The semiconductor device of claim 7, wherein each of the unit cells comprises: a gate having a third substantially hexagonal shape; a well in the drift region and below the gate; a source in contact with the well in the drift region; a first high concentration impurity region surrounded by the source in the drift region, the first high concentration impurity region having a first conductivity type; and a JFET region in the drift region and below the gate.

9. The semiconductor device of claim 7, comprising a plurality of the SBD regions, wherein the SBD regions are not in contact with each other.

10. The semiconductor device of claim 7, wherein the one or more SBD regions has six outer surfaces in contact with respective unit cells.

11. The semiconductor device of claim 8, wherein the one or more SBD regions comprises: a second high concentration impurity region in the drift region, the second high concentration impurity region having the first conductivity type; and a second ohmic contact on the second high concentration impurity region.

12. The semiconductor device of claim 11, further comprising: a source metal or source electrode covering the gate on the drift region; and a drain metal or drain electrode under the substrate.

13. A semiconductor device, comprising: a substrate having a plurality of MOSPET regions and one or more Schottky bather diode (SBD) regions; a lightly doped second conductivity type drift region on the substrate in the MOSPET regions and the one or more SBD regions; and a plurality of unit cells having a first substantially hexagonal shape and at least a partial honeycomb structure, and arranged in n columns, the unit cells comprising the MOSPET regions; wherein the one or more SBD regions are between two or more of the unit cells, have a second substantially hexagonal shape, and are not in adjacent ones of the n columns.

14. The semiconductor device of claim 13, wherein each of the one or more SBD regions is directly surrounded by a subset of the plurality of the unit cells.

15. The semiconductor device of claim 13, wherein the one or more SBD regions alternate with the unit cells in at least one of the n columns.

16. The semiconductor device of claim 15, wherein the SBD regions have an area equal to or less than 25% or less of a total area of an active region.

17. The semiconductor device of claim 13, further comprising a heavily doped first conductivity type impurity region in the drift region and in a center of each of the one or more SBD regions.

18. A method of manufacturing a semiconductor device, comprising: forming a drift region on a substrate; forming unit cells in n columns, the unit cells comprising MOSPET regions; and forming SBD regions, wherein forming the unit cells comprises: forming second conductivity type JFET regions having a substantially hexagonal shape in the drift region and in the MOSPET regions; forming first conductivity type wells in the JFET regions; forming first high concentration impurity regions in the JFET regions in contact with the wells, the first high concentration impurity regions having a first conductivity type; forming first heavily doped second conductivity type sources in the wells; forming second heavily doped second conductivity type sources in the drift region; and forming gates having a substantially hexagonal shape on the JFET regions, the wells, and the sources to having at least a partial honeycomb structure.

19. The method of claim 18, wherein the SBD regions are not in contact with each other.

20. The method of claim 18, wherein the SBD regions are not in consecutive ones of the n columns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other objectives, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0039] FIGS. 1A and 1B are reference views illustrating the use of a SiC Schottky bather diode in or with a conventional SiC MOSPET device;

[0040] FIG. 2 is a plan or layout view illustrating a semiconductor device including a MOSPET region and a diode region according to an embodiment of the present disclosure;

[0041] FIG. 3 is a cross-sectional view illustrating the semiconductor device including an integrated MOSPET and diode illustrated in FIG. 2, taken along line A-A;

[0042] FIG. 4 is a cross-sectional view illustrating the semiconductor device including the MOSPET and the diode illustrated in FIG. 2, taken along line B-B;

[0043] FIG. 5 is a plan or layout view illustrating only first high concentration impurity regions, sources, and wells in the semiconductor device illustrated in FIG. 2;

[0044] FIG. 6 is a plan view illustrating only gates in the semiconductor device illustrated in FIG. 2; and

[0045] FIGS. 7 to 17 are cross-sectional views illustrating a method of manufacturing a semiconductor device including one or more MOSPET regions and one or more integrated diode regions according to one or more embodiments of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0046] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The embodiments of the present disclosure can be modified in various forms. Therefore, the scope of the present disclosure should not be construed as being limited to the following embodiments, but should be construed on the basis of the descriptions in the appended claims. The embodiments of the present disclosure are provided for complete disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0047] As used herein, the singular forms may include the corresponding plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprise and/or comprising, etc. when used herein specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof.

[0048] As used herein, when an element (or layer) is referred to as being on another element (or layer), it can be directly on the other element, or one or more intervening elements (or layers) may be therebetween. In contrast, when an element is referred to as being directly on or above another component, no intervening element is therebetween. Further, the terms on, above, below, upper, lower, one side, side surface, etc. are used to describe one element's positional relationship to one or more other elements illustrated in the drawings.

[0049] Meanwhile, when an embodiment can be implemented differently, functions or operations described herein may occur in a different way from that described herein. For example, two consecutive functions or operations may be performed simultaneously, or the functions or operations may be performed in reverse sequence.

[0050] Hereinafter, a first conductivity type may refer to P-type doping, and a second conductivity type may refer to N-type doping. Alternatively, in some cases, the first conductivity type may be N-type, and the second conductivity type may be P-type, but the present disclosure not limited thereto.

[0051] FIG. 2 is a plan view illustrating a semiconductor device 1 including one or more MOSPET regions and one or more integrated diode regions according to an embodiment of the present disclosure; FIG. 3 is a cross-sectional view illustrating the semiconductor device 1 taken along line A-A of FIG. 2; FIG. 4 is a cross-sectional view illustrating the semiconductor device taken along line B-B of FIG. 2; FIG. is a plan view illustrating only first high concentration impurity regions 150, sources 130, and wells 120 in the semiconductor device 1 illustrated in FIG. 2; and FIG. 6 is a plan view illustrating only gates 140 in the semiconductor device 1 illustrated in FIG. 2.

[0052] Hereinafter, the semiconductor device 1 including integrated MOSPET and diode regions according to one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0053] Referring to FIGS. 2 to 6, the present disclosure relates generally to the semiconductor device 1 including integrated SiC MOSPET and Schottky bather diode regions. More particularly, the present disclosure relates to the semiconductor device 1 including the MOSPET and diode regions, including silicon carbide (SiC) MOSPET region A1 and an integrated Schottky bather diode (SBD) region A2 that reduces forward voltage drop (Vf), device area, and switching oscillation caused by parasitic inductance (e.g., between the SiC MOSPET and the Schottky bather diode).

[0054] A first region A1 serving as a MOSPET region and a second region A2 serving as a Schottky bather diode region are in the device 1, which will be described later.

[0055] Referring to FIGS. 3 and 4, a substrate 101 may include, for example, a silicon carbide (SiC) wafer heavily doped with a second conductivity type impurity. In more detail, the substrate 101 may be or comprise, for example, a 4H-SiC or 6H-SiC substrate. The second conductivity type impurity in the heavily doped substrate 101 may include, for example, phosphorus.

[0056] A drift region 110 may be on the substrate 101. The drift region 110 may include, for example, a SiC epitaxial layer grown on the SiC single crystal substrate 101 that maintains a specific crystalline orientation with respect to the crystal lattice of the substrate 101. The drift region 110 may be formed by, for example, chemical vapor deposition (CVD), but is not limited thereto, and may be formed by various other processes such as molecular beam epitaxy (MBE), sublimation epitaxy, and liquid phase epitaxy.

[0057] In addition, the drift region 110 may be or comprise a lightly doped second conductivity type impurity region having a lower doping concentration than the substrate 101, and may include, for example, phosphorus as the second conductivity type impurity. The drift region 110 may be in both the first region A1 and the second region A2.

[0058] In the first region A1, a well 120 may be in a surface of the drift region 110 or a junction gate field-effect transistor (MET) region 160 which will be described later. The well 120 may be or comprise a first conductivity type doped impurity region. A channel region may form in the well 120. In addition, a source 130 may be in the well 120. The source 130 may be or comprise a heavily doped second conductivity type impurity region. Here, the source 130 may have a higher doping concentration than the drift region 110.

[0059] In addition, the source 130 may be in contact with a lower portion or a lowermost surface of a gate 140, which will be described later. The source 130 may be in the first region A1. When a MOSPET of the semiconductor device 1 operates, a channel may form in the well 120 to secure a path for movement of carriers (e.g., electrons). Thus, electrons from a source electrode (which will be described later) may move to a drain metal or drain electrode 180 which will be described later, through the source 130 and the well 120, below a gate electrode 143.

[0060] In addition, in the first region A1, the gate 140 may be on the substrate 101 or the drift region 110. The gate 140 may be on the drift region 110 and may at least partially overlap the well 120 and the source 130.

[0061] The gate 140 may include a gate oxide film 141 on the drift region 110 and the gate electrode 143 on the gate oxide film 141. Thus, a lowermost surface of the gate oxide film 141 may be in contact with the well 120 and the source 130. The gate electrode 143 may be or comprise, for example, polysilicon doped with an impurity. In addition, an insulating film 145 may surround or cover the gate electrode 143 and the gate oxide film 141. The insulating film 145 may also cover sidewalls of the gate electrode 143 and the gate oxide layer 141 and may at least partially cover an upper surface of the gate electrode 143. The gate 140 may have a hexagonal shape in a plan or layout view, rather than a rectangular shape, and a detailed description thereof will be described later.

[0062] Next, in the first region A1, a high concentration impurity region 150 may be in the drift region 110 or the MET region 160. The high concentration impurity region 150 may be in the drift region 110 and may be in contact with the well 120 and the source 130. For example, the high concentration impurity region 150 may be or comprise a heavily doped first conductivity type impurity region, and may be in contact with the sidewall of each of the well 120 and the source 130 distal from the gate 140. In addition, an ohmic contact 151 in contact with a source metal or source electrode 170 may be on at least portions of uppermost surfaces of the high concentration impurity region 150 and the source 130. The ohmic contact 151 may comprise, but is not limited to, Ti or TiN.

[0063] In addition, in the first region A1, the MET region 160 may be in the drift region 110. The MET region 160 may be below the gate 140 in the drift region 110. For example, the JFET region 160 may be or comprise a second conductivity type doped impurity region, and preferably has a higher doping concentration than the drift region 110, but a lower doping concentration than the source 130. In addition, the MET region 160 is preferably below the gate 140 and adjacent to the channel region of the well 120. That is, the MET region 160 may be in contact with a sidewall of the well 120 adjacent to the gate 140.

[0064] In addition, the JFET region 160 may surround the well 120 and the high concentration impurity region 150. That is, the JFET region 160 may be deeper than the lowermost surface of the well 120 and the high concentration impurity region 150 in the drift region 110, and may at least partially surround the well 120 and the high concentration impurity region 150. By forming the MET region 160 in this manner, when a current moves from the drain metal 180 to the source metal 170, the current can move through the MET region 160 along a path below the gate 140, as well as a path below the well 120 and the high concentration impurity region 150. The additional current path facilitates or improves current distribution. This results in improving resistance characteristics of the device 1.

[0065] In addition, the source metal or source electrode 170 may be on the substrate 101 or the drift region 110 in the first region A1 and the second region A2. The source metal 170 may be on the drift region 110 and may cover the insulating film 145 and the ohmic contact 151, and may extend to the second region A2. The source metal 170 may include, but is not limited to, A1 or an A1 alloy.

[0066] In addition, the drain metal or drain electrode 180 may be under or on an opposite surface of the substrate 101. The drain metal 180 may be electrically connected to a drain terminal D. The drain metal 180 may include, but is not limited to, Ni or Ag. The drain metal 180 may be in both the first region A1 and the second region A2.

[0067] In addition, a high concentration impurity region 210 may be in the drift region 110 in the second region A2. For convenience of description, the above-described high concentration impurity region 150 is referred to as a first high concentration impurity region 150, and the high concentration impurity region 210 in the second region A2 is referred to as a second high concentration impurity region 210. The second high concentration impurity region 210 may be formed substantially simultaneously with the first high concentration impurity region 150 (e.g., in the same processing steps), but is not limited thereto. Thus, the second high concentration impurity region 210 may be or comprise a heavily doped first conductivity type impurity region. However, it should be noted that the second high concentration impurity region 210 is not an essential component of the present disclosure.

[0068] In addition, an ohmic contact 220 may be on the second high concentration impurity region 210 or the drift region 110 in the second region A2. The ohmic contact 220 may include, but is not limited to, Ti or TiN. It should be also noted that the ohmic contact 220 is not an essential component of the present disclosure. For example, in the case of a merged pin Schottky (MPS) diode, the ohmic contact 220 may be on the second high concentration impurity region 210, but in the case of a junction bather Schottky (JBS) diode, the ohmic contact 220 may not be on the second high concentration impurity region 210.

[0069] In addition, a contact region 230 may be on the drift region 110 in the second region A2 at a position adjacent to or in contact with the ohmic contact 220. The contact region 230 may be or comprise a metal layer, and may include, but is not limited to, Ni and/or Ti. The contact region 230 may improve bonding between the drift region 110 and the source metal 170.

[0070] Hereinafter, the problems of a conventional SiC MOSPET semiconductor device and the structure of the semiconductor device 1 including the integrated MOSPET and diode regions according to the present disclosure for solving the problems will be described in more detail with reference to the accompanying drawings.

[0071] A typical power metal-oxide-semiconductor field-effect transistor (power MOSPET) device has a body diode and uses the body diode as a free-wheeling diode during switching, so the use of a Schottky bather diode is not essential. However, in the case of a SiC MOSPET device, it has higher forward voltage drop (Vf) characteristics than a Si MOSPET device due to its intrinsic high energy band gap and high built-in potential.

[0072] Due to such high forward voltage drop, the SiC MOSPET device consumes a relatively large amount of power during switching, compared to a Si MOSPET of the same voltage rating, and power consumption inevitably increases as the voltage rating increases. Therefore, for applications where power consumption is important, a SiC Schottky bather diode may be connected in parallel with the SiC MOSPET device and is used externally (see FIG. 1A) or co-packaged as a discrete device with the SiC MOSPET device (see FIG. 1B). However, the use of such a discrete Schottky bather diode may result in an increase in manufacturing cost, additional space consumption, and switching oscillation caused by parasitic inductance.

[0073] Referring to FIGS. 2 to 6, in order to solve the above problems, the device 1 according to embodiment(s) of the present disclosure includes the first region A1 serving as the MOSPET region and the second region A2 serving as the integral Schottky bather diode region. However, the integration of the first region A1 and the second region A2 may disadvantageously reduce the channel density because the first region A1 and the second region A2 are in the same device area. This may be solved by arranging the components of the semiconductor device 1 in the MOSPET region and the diode region as follows, which will be described in detail below.

[0074] In the semiconductor device 1, the gate 140 may have a hexagonal shape (e.g., in the plan or layout view). Here, the semiconductor device 1 may include a plurality of hexagonal gates 140, which may be arranged in a honeycomb pattern, for example. With this structure, there may be no loss of space, so space utilization may increase. For example, when a plurality of unit cells C having a hexagonal shape are in contact with each other, they may form n columns.

[0075] All the unit cells C may have substantially the same shape in the plan or layout view and the same cross-sectional shape. In each of the unit cells C, the gate 140 may have, for example, a hexagonal shape (e.g., in the plan or layout view). In addition, the well 120 may be below the gate 140. In addition, the source 130 may be in the well 120 and in contact with the well 120. The source 130 may have, for example, a substantially hexagonal shape (e.g., in the plan or layout view). In addition, the first high concentration impurity region 150 may be in the center of the unit cell region C. The first high concentration impurity region 150 may have, for example, a substantially hexagonal shape (e.g., in the plan or layout view). Finally, the MET region 160 may be below the gate 140. The MET region 160 may have, for example, a substantially hexagonal shape (e.g., in the plan or layout view). However, it should be noted that the examples of the shape of each component in the plan or layout view (except for the gate 140) are not limited by the above examples.

[0076] Here, the second region A2 may not be in a specific column. That is, in an mth column (0<m<n), a plurality of unit cells C having substantially the same shape may repeat along the column direction.

[0077] In addition, the second region A2 may be in an m?1th and/or m+1th column adjacent to the unit cells C in the mth column. For example, the second region A2 and the first region A1 may alternate in the m?1th column and/or m+1th column along the column direction. That is, a column comprising sequential, alternating first regions A1 and second regions A2 may repeat, such that the outer surfaces of each hexagonal second region A2 are adjacent to or surrounded by respective unit cells C or first regions A1. However, the arrangement of the second regions A2 in the m?1th and/or m+1st column is not limited to the above example, and the second regions A2 may be at least partially repeated along the column direction. Alternatively, the first regions A1 may be repeated along the column direction.

[0078] With this structure, the MOSPET region A1 and the integral Schottky bather diode region A2 may reduce the forward voltage drop (Vf), the manufacturing cost, and the product area, and stabilize the switching waveform and reduce oscillation by reducing or eliminating parasitic inductance. In addition, the unit cells C having a hexagonal shape and/or a honeycomb structure may compensate for the area loss resulting from the Schottky bather diode region(s) A2 by an increase in the channel density.

[0079] Here, it is preferable that the area of the Schottky bather diode A2 is equal to less than 25% of the total area of an active region (e.g., of the semiconductor device 1), but the scope of the present disclosure is not limited by the numerical range.

[0080] FIGS. 7 to 17 are cross-sectional views illustrating structures formed during a method of manufacturing a semiconductor device including integrated MOSPET and diode regions according to one or more embodiments of the present disclosure.

[0081] Hereinafter, the method of manufacturing the semiconductor device 1 including the integrated MOSPET and diode regions according to embodiment(s) of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the sequence of the steps of the manufacturing method is not limited to the order described below.

[0082] Referring to FIG. 7, first, a drift region 110 may be formed on a substrate 101. The drift region 110 may be formed by epitaxial growth (e.g., of SiC) on the substrate 101. The drift region 110 may also be formed by, for example, chemical vapor deposition (CVD), but is not limited thereto, and may be formed by other various processes such as molecular beam epitaxy (MBE), sublimation epitaxy, and liquid phase epitaxy.

[0083] Then, referring to FIG. 8, a MET region 160 may be formed in the drift region 110 (e.g., at or through a surface thereof) in a first region A1. The MET region 160 may be formed by ion implantation in which a second conductivity type impurity is implanted through a mask pattern (e.g., a patterned photoresist; not illustrated). As described above, the MET region 160 may be a second conductivity type heavily doped impurity region.

[0084] Then, referring to FIG. 9, a well 120 may be formed in the MET region 160 (e.g., at or through a surface of the MET region 160). The well 120 may be formed by ion implantation in which a first conductivity type impurity is implanted through a mask pattern (e.g., a second patterned photoresist; not illustrated). The well 120 is preferably doped with an impurity at a lower doping concentration than the first high concentration impurity region 150.

[0085] Then, referring to FIG. 10, the first high concentration impurity region 150 may be formed in the MET region 160 (e.g., at or through a surface of the MET region 160), in contact with the well 120 (e.g., a sidewall thereof). The first high concentration impurity region 150 may be a first conductivity type heavily doped impurity region, and may be formed by ion implantation in which a first conductivity type impurity is implanted through a mask pattern (e.g., a third patterned photoresist; not illustrated). When the first high concentration impurity region 150 is formed, a second high concentration impurity region 210 may be formed simultaneously in the drift region 110 in the second region A2 if necessary or desired.

[0086] Then, referring to FIG. 11, a source 130 may be formed. The source 130 may be formed by ion implantation in which a second conductivity type impurity is implanted using a mask pattern (e.g., a fourth patterned photoresist; not illustrated). As described above, the source 130 may be a second conductivity type heavily doped impurity region. The source 130 is preferably formed in the well 120 (e.g., at or through a surface thereof).

[0087] Then, referring to FIG. 12, a gate oxide film 141 may be formed on the drift region 110 or the MET region 160. The gate oxide film 141 may be formed, for example, by blanket-depositing an oxide film or layer (not illustrated) on the well 120, the source 130, the first high concentration impurity region 150, the MET region 160, and the drift region 110 (e.g., by CVD using a source gas such as tetraethyl orthosilicate [TEOS] or silane [SiH.sub.4] in the presence of oxygen) and then etching the oxide film or layer using a mask pattern (e.g., a fifth patterned photoresist; not illustrated).

[0088] Then, referring to FIG. 13, a gate electrode 143 may be formed on the gate oxide film 141. The gate electrode 143 may be formed, for example, by blanket-depositing a doped polysilicon film (e.g., by CVD or physical vapor deposition [PVD]; not illustrated) on the drift region 110 and the gate oxide film 141 and then etching process the doped polysilicon film using a mask pattern (not illustrated). Alternatively, the oxide film or layer and the doped polysilicon film may be blanket-deposited in sequence, then sequentially etched using the same mask pattern.

[0089] Then, referring to FIG. 14, an insulating film 145 surrounding the gate oxide film 141 and the gate electrode 143 may be formed. The insulating film 145 may be formed, for example, by blanket-depositing one or more insulating films such as an oxide film or layer (not illustrated) on the drift region 110, the gate oxide film 141, and the gate electrode 143 and then etching the one or more insulating films process using a mask pattern (e.g., a sixth patterned photoresist; not illustrated).

[0090] Then, referring to FIG. 15, an ohmic contact 151 may be formed in the first region A1. The ohmic contact 151 may be at least partially in contact with uppermost surfaces of the source 130 and the first high concentration impurity region 150, and may be formed, for example, by blanket-depositing a Ti or TiN layer (not illustrated) on the source 130, the first high concentration impurity region 150, and the insulating film 145, and then etching the Ti or TiN metal layer using a mask pattern (e.g., a seventh patterned photoresist; not shown). Here, an ohmic contact 220 may be formed simultaneously in the second region A2, if necessary or desired. The ohmic contact 220 in the second region A2 may be formed on the second high concentration impurity region 210.

[0091] Then, referring to FIG. 16, a contact region 230 may be formed in the second region A2. The contact region 230 may be formed on the drift region 110. The contact region 230 may be formed, for example, by blanket-depositing a Ti or Ni metal layer (not illustrated) on the drift region 110 and then etching the Ti or Ni metal layer using a mask pattern (e.g., an eighth patterned photoresist; not illustrated).

[0092] Finally, referring to FIG. 17, a source metal or source electrode 170 and a drain metal or drain electrode 180 may be formed. The source metal 170 may be or comprise a metal layer such as A1 or an A1 alloy, and the drain metal 180 may be or comprise a metal layer such as Ni or Ag. The source metal 170 may cover the ohmic contacts 151 and 220, the gate 140, and the contact region 230. The drain metal 180 may cover an opposite surface of the substrate 101.

[0093] As described above, in the unit cell C, the gate 140 may have a hexagonal shape. In addition, the well 120 may be below the gate 140. In addition, the source 130 may be in the well 120 and in contact with the well 120. The source 130 may have, for example, a substantially hexagonal shape. In addition, the first high concentration impurity region 150 may be in the center of the unit cell C. The first high concentration impurity region 150 may have, for example, a substantially hexagonal shape. Finally, the JFET region 160 may be below the gate 140. The JFET region 160 may have, for example, a substantially hexagonal shape. As described above, it should be noted that the shape of each component is exemplary for description of the present disclosure.

[0094] The foregoing detailed description may be merely an example of the present disclosure. Also, the inventive concept is explained by describing various embodiments and may be used in various combinations, modifications, and environments. That is, the inventive concept may be amended or modified without departing from the scope of the technical idea and/or knowledge in the art. The foregoing embodiments are for illustrating various modes for implementing the technical idea of the present disclosure, and various modifications may be made therein according to specific application fields and/or uses of the present disclosure. Therefore, the foregoing detailed description of the present disclosure is not intended to limit the inventive concept to the disclosed embodiments.