High-voltage capacitor for integration into electrical power modules and a method for the manufacture of the same

Abstract

A high-voltage capacitor for integration into electrical power modules has a silicon layer into which an arrangement of recesses is introduced on a front face. The front face with the recesses is coated with a dielectric layer or dielectric layer sequence, wherein the recesses are filled with an electrically conductive material. The silicon layer bears a contact metallisation on the front face and the rear face for purposes of making electrical contact with the capacitor. A layer of thermal SiO.sub.2 is formed between the silicon layer and the dielectric layer or layer sequence. The dielectric layer or layer sequence has a layer thickness of ≥1000 nm and is formed from a ferroelectric or anti-ferroelectric material. The proposed high-voltage capacitor features a high integration density with a high capacitance and good heat dissipation properties.

Claims

1. A high-voltage capacitor for integration into electrical power modules, which capacitor has a silicon layer into which an arrangement of recesses is introduced on a front face, wherein the front face, with the recesses, is coated with a dielectric layer or layer sequence, the recesses are filled with an electrically conductive material, and the silicon layer bears a contact metallisation (123a) on the front face and on the rea r face in each case, characterised in that, a layer of thermal SiO.sub.2, is formed between the silicon layer and the dielectric layer or layer sequence said layer of thermal SiO.sub.2 being in contact with the dielectric layer or layer sequence, and the dielectric layer or layer sequence has a layer thickness of ≥1000 nm is formed of a ferroelectric or anti-ferroelectric material, or contains a ferroelectric or anti-ferroelectric material.

2. The high-voltage capacitor in accordance with claim 1, characterised in that a further dielectric layer, in particular of SiO.sub.2 or Si.sub.3N.sub.4, is formed between the dielectric layer or layer sequence and the contact metallisation on the front face.

3. The high-voltage capacitor in accordance with claim 1, characterised in that the electrically conductive material is at least partially polysilicon or a metallic material.

4. The high-voltage capacitor in accordance with claim 1, characterised in that the dielectric layer sequence comprises a plurality of dielectric layers of the ferroelectric or anti-ferroelectric material, with intermediate dielectric layers of one or a plurality of other materials, in particular SiO.sub.2 and/or Si.sub.3N.sub.4.

5. The high-voltage capacitor in accordance with claim 1, characterised in that the recesses are trenches.

6. The high-voltage capacitor in accordance with claim 1, characterised in that the contact metallisation has a thickness by means of which a local self-healing of the capacitor is achieved in the event of leakage currents occurring.

7. The high-voltage capacitor in accordance with claim 1, further comprising, a substrate of an electrical power module which carries the high-voltage capacitor as a damping component or as an intermediate circuit capacitor.

8. A method for the manufacture of a high-voltage capacitor in accordance with claim 1, in which the dielectric layer or layer sequence is produced by conformal deposition.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) In what follows the proposed high-voltage capacitor is explained in more detail with the aid of an example of embodiment, in conjunction with the figures. Here:

(2) FIG. 1 shows a schematic cross-section through a high-voltage capacitor in accordance with an example of embodiment of the present invention; and

(3) FIG. 2 shows a detail from FIG. 1, in which the layered structure of the proposed high-voltage capacitor can be discerned.

PATHS TO EMBODIMENT OF THE INVENTION

(4) In what follows the proposed capacitor for power electronics is described in more detail with the aid of an example of embodiment in which the capacitor is formed in a silicon substrate. To this end FIG. 1 shows a schematic structure of the capacitor, shown in this example in a cross-section through the silicon substrate 1. Parallel trenches 2 are introduced into the front face of this silicon substrate 1; these have a high aspect ratio of ≥10:1 (depth to width). This high aspect ratio is not apparent from the figure for reasons of presentability. The surface of the silicon substrate 1, including the trenches 2, is covered with a thermal SiO.sub.2 layer, which cannot be discerned in FIG. 1. A dielectric layer 3 of a ferroelectric or anti-ferroelectric material with a thickness of ≥1000 nm is applied onto this layer, as is schematically indicated in FIG. 1. For this purpose, barium strontium titanate, or lead zirconium titanate can, for example, be used as materials. The trenches 2 are filled with an electrically conductive material, such as polysilicon, which also extends over the front face of the silicon substrate 1 and forms an upper electrode layer 4. The individual layers can, for example, be deposited by means of MOCVD. Finally, a contact metallisation layer 5 for purposes of making electrical contact with the capacitor is applied to the front and rear faces of the silicon substrate 1. On the rear face, between the said contact metallisation 5 and the silicon substrate 1, there can also be a lower electrode layer 6 of a suitable electrically conductive material.

(5) FIG. 2 shows a detail from the cross-section of FIG. 1, showing the layered structure between the silicon substrate 1 and the upper electrode layer 4 in the high-voltage capacitor of this example of embodiment. From the figure it can be seen that the silicon substrate 1 is coated with a thermal oxide layer 7 (thermal SiO.sub.2), which thus lies between the dielectric layer 3 and the silicon substrate 1. By means of this thermal oxide, interface states at the point of transition from the dielectric layer 3 to the silicon substrate 1, which can lead to defects in the dielectric layer 3, are avoided. This increases the reliability of the capacitor, even with the ferroelectric or anti-ferroelectric layers of high layer thickness that are here present. The dielectric layer 3 of ferroelectric or anti-ferroelectric material has a correspondingly high dielectric constant (>100) and enables a high capacitor reverse voltage. In the present example, a layer 8 of silicon nitride (Si.sub.3N.sub.4) is also applied to this dielectric layer 3, which thus lies between the upper electrode layer 4 and the dielectric layer 3. This additional dielectric layer, preferably applied by means of CVD, which can also be formed, for example, from SiO.sub.2, contributes to a minimising of the leakage current at the interface to the upper electrode.

(6) The proposed capacitor structure achieves a high integration density with a high dielectric strength and high capacitance values, making the proposed capacitor suitable for power electronic applications on a DCB substrate. The following Table 1 shows a comparison of the characteristic values of such a capacitor with published characteristic values of other high-voltage capacitors, which have dielectrics made of SiO.sub.2 or Si.sub.3N.sub.4. It can be seen from the table that the proposed high-voltage capacitor has a very high integration density and quality rating compared to the high-voltage capacitors in silicon technology that have been implemented to date.

(7) TABLE-US-00001 TABLE 1 Breakdown Integration Quality Dielectric voltage density rating SiO.sub.2/Si.sub.3N.sub.4 550 V 2 nF/mm.sup.2 1.1 μC/mm.sup.2 SiO.sub.2/Si.sub.3N.sub.4 1000 V 0.7 nF/mm.sup.2 0.7 μC/mm.sup.2 SiO.sub.2/Si.sub.3N.sub.4 500 V 2.9 nF/mm.sup.2 1.45 μC/mm.sup.2 SiO.sub.2/Si.sub.3N.sub.4 280 V 3.5 nF/mm.sup.2 0.98 μC/mm.sup.2 (Anti-) 1000 V >7 nF/mm.sup.2 >7 μC/mm.sup.2 ferroelectrics

LIST OF REFERENCE SYMBOLS

(8) 1 Silicon substrate 2 Trenches 3 Dielectric layer 4 Upper electrode layer 5 Contact metallisation 6 Lower electrode layer 7 Thermal oxide layer (SiO.sub.2) 8 Silicon nitride layer