SYSTEM ON CHIP INCLUDING A PVT SENSOR AND CORRESPONDING PVT SENSING METHOD

Abstract

A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.

Claims

1. A system-on-chip, comprising: a process-voltage-temperature (PVT) sensor, comprising: a filter circuit configured to receive an input patterned digital signal, propagate the input patterned digital signal in a manner responsive to process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip, and generate an output patterned digital signal; and a digital comparison circuit configured to compare the input patterned digital signal and the output patterned digital signal and generate a warning signal when the comparison finds discrepancies between the input patterned digital signal and the output patterned digital signal.

2. The system-on-chip according to claim 1, wherein the filter circuit comprises: a first flip-flop circuit configured to propagate the input patterned digital signal; and a first delay circuit configured to delay the input patterned digital signal at a data input of the first flip-flop circuit with a first delay dependent on said process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip.

3. The system-on-chip according to claim 2, wherein the filter circuit further comprises: a second flip-flop circuit configured to propagate the input patterned digital signal and to be cadenced by a clock signal; a second delay circuit configured to delay the input patterned digital signal at a data input of the second flip-flop circuit with a second delay dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip; and a third delay circuit configured to delay the clock signal at the clock input of the second flip-flop circuit with a third delay dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip; wherein the third delay of the third circuit is less dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip than the second delay of the second delay circuit.

4. The system-on-chip according to claim 1, wherein the PVT sensor further comprises registers configured to store internal parameters determining a response of the filter circuit to process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip, wherein the internal parameters are configurable.

5. The system-on-chip according to claim 4, wherein the filter circuit comprises: a first flip-flop circuit configured to propagate the patterned digital signal; and a first delay circuit configured to delay the patterned digital signal at a data input of the first flip-flop circuit with a first delay dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip; and wherein the internal parameters include a duration of said first delay.

6. The system-on-chip according to claim 5, wherein the filter circuit further comprises: a second flip-flop circuit configured to propagate the patterned digital signal and to be cadenced by a clock signal; a second delay circuit configured to delay the patterned digital signal at a data input of the second flip-flop circuit with a second delay dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip; and a third delay circuit configured to delay the clock signal at the clock input of the second flip-flop circuit with a third delay dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip, wherein the third delay of the third circuit is less than the second delay of the second delay circuit; and wherein the internal parameters include durations of said first, second and third delays.

7. The system-on-chip according to claim 1, wherein the system-on-chip comprises: peripheral circuits; and an internal bus linking the peripheral circuits together in a respective bus domain; wherein the PVT sensor is incorporated within the bus domain in a physical proximity to the peripheral circuits, and is supplied with a same supply voltage and a same clock signal as the peripheral circuits of the bus domain.

8. The system-on-chip according claim 7, wherein the PVT sensor includes same components as the components of the peripheral circuits in the physical proximity to the PVT sensor.

9. The system-on-chip according to claim 7, wherein the PVT sensor includes a bus interface configured to receive and to emit communications on the internal bus.

10. The system-on-chip according to claim 9, wherein the PVT sensor includes registers configured to store internal parameters determining a response of the filter circuit dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip, wherein the internal parameters are configurable; and wherein the system-on-chip includes a master unit configured to execute software operations comprising communicating configuration commands to the PVT sensor via the internal bus, the configuration commands being configured to set the internal parameters.

11. The system-on-chip according to claim 9, wherein the PVT sensor is configured to communicate the warning signal to a decisional unit via the internal bus.

12. A method for sensing process-voltage-temperature (PVT) variations in a system-on-chip, comprising: generating an input patterned digital signal; propagating the input patterned digital signal by a filter circuit in a manner responsive to process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip to generate an output patterned digital signal; digitally comparing the input patterned digital signal and the output patterned digital signal; and generating a warning signal in response to detection of discrepancies between the input patterned digital signal and the output patterned digital signal.

13. The method according to claim 11, wherein propagating the input patterned digital signal comprises: passing the input patterned digital signal through a first flip-flop circuit; and applying a first delay on the input patterned digital signal at a data input of the first flip-flop circuit; wherein the first delay is dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip.

14. The method according to claim 13, wherein propagating the input patterned digital signal comprises: passing the input patterned digital signal through a second flip-flop circuit cadenced by a clock signal; applying a second delay on the input patterned digital signal at the data input of the second flip-flop circuit; and applying a third delay on the clock signal at the clock input of the second flip-flop circuit; wherein the second delay is dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip; wherein the third delay is less dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip than the second delay.

15. The method according to claim 12, further comprising storing internal parameters determining the response of the filter circuit to process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip, wherein the internal parameters are configurable.

16. The method according to claim 15, wherein propagating the input patterned digital signal comprises: passing the input patterned digital signal through a first flip-flop circuit; and applying a first delay on the input patterned digital signal at a data input of the first flip-flop circuit; wherein the first delay is dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip; and wherein the internal parameters include a duration of the first delay.

17. The method according to claim 16, wherein propagating the input patterned digital signal comprises: passing the input patterned digital signal through a second flip-flop circuit cadenced by a clock signal; applying a second delay on the input patterned digital signal at the data input of the second flip-flop circuit; and applying a third delay on the clock signal at the clock input of the second flip-flop circuit; wherein the second delay is dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip; wherein the third delay is less dependent on process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip; and wherein the internal parameters include durations of the first, second and third delays.

18. The method according to claim 12, wherein sensing process-voltage-temperature (PVT) variations is performed in a physical proximity to peripheral circuits linked together by an internal bus in a respective bus domain of the system-on-chip, and performed with a same supply voltage and a same clock signal as the peripheral circuits of the bus domain.

19. The method according to claim 18, wherein sensing process-voltage-temperature (PVT) variations is performed with same components as the components of the peripheral circuits in the physical proximity to the sensing.

20. The method according to claim 18, further comprising storing internal parameters determining the response of the filter circuit to process variations in semiconductor material, variations in operating supply voltage for the system-on-chip and variations in operating temperature of the system-on-chip, wherein the internal parameters are configurable; and receiving and emitting communications on the internal bus via a bus interface including communication of configuration commands configuring the internal parameters, emitted from a master unit of the system-on-chip configured to execute software operations.

21. The method according to any of claim 20, comprising communicating the warning signal to a decisional unit of the system-on-chip via the internal bus.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Other advantages and specifications of the invention will appear at the review of the detailed description of embodiments, in no way limiting, and in relation with annexed drawings, amongst which:

[0042] FIG. 1 illustrates a block diagram of a method for sensing process-voltage-temperature (PVT) variations in a system-on-chip;

[0043] FIG. 2A illustrates an example embodiment of the system-on-chip SOC including a process-voltage-temperature (PVT) sensor;

[0044] FIGS. 2B, 2C, 2D and 2E illustrate time diagrams of signals related to the filter circuit and comparator depicted in FIG. 2A;

[0045] FIG. 3A illustrates another example embodiment of the system-on-chip SOC including a process-voltage-temperature (PVT) sensor;

[0046] FIGS. 3B, 3C, 3D and 3E illustrate time diagrams of signals related to the filter circuit and comparator depicted in FIG. 3A;

[0047] FIG. 4 illustrates an example embodiment in a more high-level point of view of the system-on-chip SOC including a process-voltage-temperature (PVT) sensor; and

[0048] FIG. 5 illustrates a schematic global example of the system on chip SOC including a process-voltage-temperature (PVT) sensor.

DETAILED DESCRIPTION

[0049] FIG. 1 illustrates a block diagram of a method 100 for sensing process-voltage-temperature (PVT) variations in a system-on-chip SOC. The method 100 comprises initiating a patterned digital signal 101, propagating the patterned digital signal 103 by a filter circuit FLT and digitally comparing 105 the initiated patterned digital signal PDSi and the propagated patterned digital signal PDSo. The filter circuit is configured so that the propagation of the patterned digital signal PDSo is responsive to (i.e., “dependent of”, or “impacted by”) variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip. The digital comparison 105 comprises generating a warning signal 107 in case of discrepancies between the compared patterned digital signals.

[0050] FIG. 2A illustrates an example embodiment of the system-on-chip SOC including a process-voltage-temperature (PVT) sensor SNS configured to perform the method described in relation with FIG. 1.

[0051] The PVT sensor SNS comprises a filter circuit FLT configured to initiate a patterned digital signal PDS and to propagate the patterned digital signal in a manner responsive to variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip SOC. The PVT sensor SNS includes a digital comparison circuit CMP configured to compare the initiated patterned digital signal PDSi and the propagated patterned digital signal PDSo through the filter circuit FLT, and to generate a warning signal SV, HV in case of discrepancies between the compared patterned digital signals.

[0052] In this example embodiment, the PVT sensor SNS comprises, in order to initiate the patterned digital signal PDS, a pattern generator PGN configured to generate the patterned digital signal PDS. In this example, the pattern generator includes a feedback inverter circuit coupled from the output Q1 to the input D1 of a first D-type flip-flop DF1. The first D-type flip-flop DF1 is cadenced by a clock signal clk and accordingly generates series of alternated zeros “0” and ones “1” toggling at each clock cycle and forming the digital pattern.

[0053] Conventionally, a D-type flip-flop is a synchronous latch configured to capture the value of the “D” (data) input at a definite portion of the clock cycle, such as the rising edge of the clock, the captured value becoming the “Q” output.

[0054] In an alternative example embodiment (shown at FIG. 4), the PVT sensor SNS may comprise, in order to initiate the patterned digital signal PDS, a dedicated input configured to receive the patterned digital signal PDS, the patterned digital signal PDS being generated by an external device and transmitted on the dedicated input.

[0055] The first D-type flip-flop DF1 is also included in a first flip-flop circuit FFC1 configured to detect a setup violation SV. The first flip-flop circuit comprises a second D-type flip-flop DF2 cadenced by the clock signal clk, and having an input D2 connected to the output Q1 of the first flip-flop DF1, and an output Q1 outputting the propagated patterned digital signal PDSo.

[0056] In addition, the first flip-flop circuit FFC1 includes a first delay circuit DELL connected in the feedback loop of the pattern generator PGN, and configured to delay the patterned digital signal at the data input D1 of the first D-type flip-flop DF1.

[0057] The first delay circuit DELI is illustrated upstream (before) to the inverter in the feedback loop of the pattern generator PGN, but could equally be placed downstream (after) from the inverter in the feedback loop of the pattern generator PGN.

[0058] The first delay circuit DEL1, connected in the data path D1, Q1, D2, Q2 of the filter circuit FLT, is configured responsive to variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip SOC.

[0059] The digital comparison circuit CMP comprises, for instance, an exclusive-or “XOR” gate receiving the initiated patterned digital signal PDSi (on D2) and the propagated patterned digital signal PDSo (on Q2) in order to output a signal SV corresponding to their comparison (equal or different). By convention, the XOR gate's output can be inverted in order to provide a high level signal “at 1” when the warning signal is triggered, and a low level signal “at 0” when it's not.

[0060] FIGS. 2B, 2C, 2D and 2E illustrate time diagrams of signals related to the filter circuit FLT and comparator CMP depicted in FIG. 2A, in case of a nominal condition's behavior “No Error” on FIG. 2B, in case of a setup violation behavior “Setup Error” on FIG. 2C, in case of a hold violation behavior “Hold Error” on FIG. 2D, and in case of both a setup violation and a hold violation behavior “Setup and Hold Error” on FIG. 2E. The signals related to a respective node of the circuit SNS depicted in FIG. 2A are named with the same reference as the respective node.

[0061] We refer now to FIG. 2B “No Error”.

[0062] The clock signal clk has a constant period T of clock cycles, and at each rising edges of the clock signal clk the D-flip-flop DF1 outputs the signal Q1 at the digital level the data input D1 had at the moment of the rising edge.

[0063] The output signal Q1 is delayed by a duration DEL1 and inverted (considered inverted with no delay) to provide the data input signal D1.

[0064] In nominal operating conditions, the output Q2 basically corresponds to the output Q1 shifted by one clock cycle. The output Q1 (input D2) and the output Q2 are thus always opposed, such as the warning signal SV is always at 0.

[0065] We refer now to FIG. 2C “Setup Error”.

[0066] FIG. 2C depicts the case when the system on chip SOC is tampered or in conditions of use lowering its speed. In this case, an additional non-nominal delay +Δ is positively added to the duration of the first delay DEL1, because of the first delay circuit DEL1 configured to be sensitive to this modification of operating condition.

[0067] Thus, if this additional delay +Δ puts back the next edge of the data input signal D1 after the next rising edge of the clock signal clk, at this next clock signal's rising edge, the level of the data input D1 is remaining at its previous level. Accordingly, the output Q1 does not switch at this clock signal's rising edge and the previous level of Q1 remains during one additional clock cycle.

[0068] The second D-type flip-flop circuit DF2 is however cadenced by the clock signal clk and accordingly switches its state to the level provided by Q1.

[0069] In consequence, the Q1 signal and the Q2 signal have identical level during a full clock cycle, and opposite levels during another full clock cycle, alternatively.

[0070] Thus, the output SV of the XOR comparator circuit is triggered periodically to “1”, during alternated full clock cycles, i.e., the periods of time when the Q1 signal and the Q2 signal have identical levels.

[0071] This permits to communicate that the system has been slowed down to an amount corresponding to a setup violation of the system on chip SOC.

[0072] The duration of the first delay DELI can advantageously be specifically configured to provide a margin for generating the warning signal SV. For example, since the warning signal SV is generated as soon as the total duration of the delay DEL1 +Δ is larger than a clock cycle period T, then the nominal duration of the first delay DEL1 can be set lower than the period T by an amount (T-DEL1) providing the tolerance margin for an additional non-nominal delay +Δ before generating the warning signal SV.

[0073] We now refer back to FIG. 2A.

[0074] The filter circuit FLT additionally includes a second flip-flop circuit FFC2 including a third D-type flip-flop DF3 configured to be cadenced by a delayed clock signal clkd.

[0075] The filter circuit FLT comprises a second delay circuit DEL2 configured to introduce a second delay on the patterned digital signal PDS propagated at the output Q2 of the second flip-flop DF2, and a third delay circuit DEL3 configured to introduce a third delay on the clock signal clk, generating the delayed clock signal clkd.

[0076] The second delay circuit DEL2 is configured responsive to variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip SOC, while the third delay circuit DEL3 is configured less responsive than the second delay circuit DEL2 to variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip SOC.

[0077] For instance, the second delay circuit DEL2 can comprise a digital delay cell, while the third delay circuit DEL3 can comprise a digital buffer which is typically is less sensible to PVT variation than a digital delay cell. For instance, the delay cell is based (by construction) on an internal slope (characteristic of the cell) making it more sensible to the PVT variation.

[0078] The second comparator circuit CMP2, for instance comprising an inverted XOR gate, is configured to receive the input D3 of the third flip-flop DF3 (i.e., the delayed patterned digital signal propagated by the second flip-flop DF2 on its output Q2) and the output Q3 of the third flip-flop circuit DF3.

[0079] Advantageously, the duration of the second delay DEL2 is larger than the duration of the third delay DEL3.

[0080] We refer now to FIG. 2B “No Error”.

[0081] In the depicted example, the duration of the second delay DEL2 is set approximatively equal to the duration of the third delay DEL3, but the second delay DEL2 is, in the general case, larger than the third delay DEL3.

[0082] In consequence, an edge in the output Q2 of the second flip-flop DF2 is delayed, at the input D3 of the third flip-flop DF3, after the next clock cycle of the delayed clock clkd.

[0083] In nominal conditions, the output Q3 of the third flip-flop DF3 accordingly takes the previous value of the output Q2 of the second flip-flop DF2 (i.e., the value before the edge in consideration).

[0084] When the duration of the second delay DEL2 is approximately equal to the duration of the third delay DEL3, the signal D3 and Q3 are always at opposite levels. Thus, the warning signal HV is constant at the level “0”, expressing no hold error.

[0085] When the duration of the second delay DEL2 is slightly larger than the duration of the third delay DEL3, the signal D3 and Q3 are mainly at opposite levels, excepted during a short duration of these signal being equals during the time difference between the edge of the delayed clock cycle (delayed by the third delay) and the edge of the data signal (delayed by the second delay).

[0086] Thus, the warning signal HV is mainly at the level “0”, with short pulses at level “1”, communicating no hold error.

[0087] We refer now to FIG. 2D “Hold Error”.

[0088] FIG. 2D depicts the case when the system on chip SOC is tampered or in conditions of use increasing its speed, an additional non-nominal delay −Δ is negatively added to the duration of the second delay DEL2 while the third delay is considered having not varied, because of the second delay circuit DEL2 configured to be more sensitive to this modification of operating condition than the third delay circuit DEL3.

[0089] Thus, if this additional negative delay −Δ is large enough to bring forward a considered edge of the delayed data signal D3 (at the input of the third flip-flop DF3) before the next rising edge of the delayed clock signal clkd.

[0090] In consequence, an edge in the output Q2 of the second flip-flop DF2 is delayed, at the input D3 of the third flip-flop DF3, before the next clock cycle of the delayed clock clkd.

[0091] In these tampered conditions increasing speed, the output Q3 of the third flip-flop DF3 accordingly takes the next value of the output Q2 of the second flip-flop DF2 (i.e., the value after the edge in consideration).

[0092] Accordingly, in these tampered conditions, the signals D3 and Q3 are mainly at the same levels during the full clock cycle clkd subsequent to the considered rising edge, excepted during a short duration of these signal being opposite during the time difference between the edge of the delayed clock cycle (delayed by the third delay) and the edge of the data signal (delayed by the second delay and the additional negative delay −Δ).

[0093] Thus, the warning signal HV is mainly at the level “1”, with short pulses at level “0” periodically at each delayed clock cycle clkd, communicating a “Hold Error”.

[0094] Furthermore, the difference in durations of the second delay DEL2 and the third delay DEL3 can advantageously be specifically configured to provide a margin for generating the warning signal HV. Indeed, since the warning signal HV is generated as soon as the total duration of the delay DEL2-Δ is smaller than the duration of the third delay DEL3, then the nominal duration of the second delay DEL2 can be set larger than the third delay DEL3 by an amount (DEL2-DEL3) providing the tolerance margin for a negative additional non-nominal delay −Δ before generating the warning signal HV.

[0095] It is recalled that it has been considered in this example that the third delay DEL3 does not vary, in the absolute. However, in practice, the third delay DEL3 should actually vary, less than the second delay DEL2, and this variation should be taken into account for establishing the tolerance margin.

[0096] FIG. 2E additionally depicts the case when the system on chip SOC is tampered with a complexity permitting to both inject a Setup Error in the datapath and a Hold Error in the clockpath.

[0097] The resulting warning signals SV and HV are resulting from a combination of the two cases described before in relation with FIG. 2C and FIG. 2D, in a manner easily deductible from these descriptions and the architecture circuit described in relation with FIG. 2A.

[0098] In summary, in that case, the setup violation warning signal SV is triggered periodically to “1”, during alternated full clock cycles, while the hold violation warning signal HV is mainly at the level “1”, with short pulses at level “0”, periodically at each couple of two successive delayed clock cycle clkd.

[0099] FIG. 3A illustrates another example embodiment of the system-on-chip SOC including a process-voltage-temperature (PVT) sensor SNS configured to perform the method described in relation with FIG. 1.

[0100] The PVT sensor SNS comprises, in order to initiate the patterned digital signal, a pattern generator PGN configured to generate the patterned digital signal PDS. Here again, the pattern generator PGN includes a feedback inverter circuit coupled from the output Qg to the input Dg of a pattern generator flip-flop circuit FFCg. The pattern generator flip-flop circuit FFCg is cadenced by a clock signal clk and accordingly generates series of alternated zeros “0” and ones “1” toggling at each clock cycle and forming the digital pattern.

[0101] The PVT sensor SNS comprises a filter circuit FLT including a reference flip-flop circuit FFCr receiving the patterned digital signal on its input Dr and propagating the patterned digital signal on its output Qr triggered by the clock signal clk.

[0102] The reference flip-flop circuit FFCr is acting as a synchronizer delaying the pattern of one clock cycle, permitting to have the same behavior as the FFC1 and FFC2 output in case of no error.

[0103] The filter circuit FLT includes a first delay circuit DEL1 configured to introduce a first delay DEL1 on the patterned digital signal, in a manner responsive to variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip SOC.

[0104] A first flip-flop circuit FFC1 receives the delayed patterned digital signal on its input D1 and propagates the patterned digital signal on its output Q1 triggered by the clock signal clk.

[0105] The filter circuit FLT includes a second delay circuit DEL2 configured to introduce a second delay DEL2 on the patterned digital signal, in a manner responsive to variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip SOC.

[0106] The filter circuit FLT includes a third delay circuit DEL3 configured to introduce a third delay DEL3 on the clock signal clk, in a manner less responsive than the second delay circuit DEL2 to variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip SOC.

[0107] A second flip-flop circuit FFC2 receives the delayed patterned digital signal on its input D2 and propagates the patterned digital signal on its output Q2 triggered by the delayed clock signal.

[0108] The comparator circuit CMP includes a first comparator, comprising at least an XOR gate, configured to compare the output signal Qr of the reference flip-flop circuit FFCr with the output signal Q1 of the first flip-flop circuit FFC1.

[0109] The comparator circuit CMP includes a second comparator, comprising at least an XOR gate, configured to compare the output signal Qr of the reference flip-flop circuit FFCr with the output signal Q2 of the second flip-flop circuit FFC1.

[0110] The comparator circuit CMP according acts in a similar manner than described in relation with FIGS. 2B, 2C, 2D and 2E in order to provide a first warning signal SV with the first comparator communicating a setup violation, and a second warning signal HV with the second comparator communicating a hold violation.

[0111] In summary, with reference to FIGS. 3B, 3C, 3D and 3E, respectively corresponding to nominal condition “No Error”, slowed tampered conditions “Setup Error”, fastened tampered conditions “Hold Error”, and combination of both “Setup and Hold Error”.

[0112] In any of these conditions, the reference flip-flop circuit FFCr acts like a shift register on the patterned digital signal PDS provided on the output Qg of the pattern generator flip-flop circuit FFCg. In other terms, the reference flip-flop circuit FFCr outputs Qr the previous value of its input Qg, at each rising edge of the clock cycle clk.

[0113] In nominal condition, FIG. 3B “No Error”, the first delay DELI moves back the edges of the digital patterned signal Qg before the next rising edge of the clock signal clk. Accordingly, the first flip-flop circuit FFC1 outputs Qr the previous value of the patterned digital signal Qg, at each rising edge of the clock signal clk. Thus, the first flip-flop circuit FFC1 acts identically to the reference flip-flop circuit FFCr and the output SV of the first comparator is always “0”.

[0114] In nominal condition, the second delay DEL2 is larger than the third delay DEL3, and thus the second delay DEL2 moves back the edges of the digital patterned signal Qg after the next rising edge of the delayed clock signal clkd. Accordingly, the second flip-flop circuit FFC2 outputs Qr the previous value of the patterned digital signal Qg, at each rising edge of the delayed clock signal clkd. Thus, the second flip-flop circuit FFC2 acts identically to the reference flip-flop circuit FFCr, but being cadenced by the delayed clock cycles clkd, and the output HV of the second comparator is mainly “0” together with short pulses at “1” periodically at each clock cycle during the duration of the third delay DEL3.

[0115] In tampered conditions slowing down the system SOC, FIG. 3C “Setup Error”, the first delay DELI undergoes an additional positive delay +Δ moving back the edges of the digital patterned signal Qg after the next rising edge of the clock signal clk. Accordingly, the first flip-flop circuit FFC1 outputs Qr the next value of the patterned digital signal Qg, at each rising edge of the clock signal clk. Thus, the first flip-flop circuit FFC1 acts in opposition to the reference flip-flop circuit FFCr and the output SV of the first comparator is always “1”.

[0116] In tampered condition increasing the speed of the system SOC, FIG. 3D “Hold Error”, the second delay DEL2 undergoes an additional negative delay −Δ making it shorter than the third delay DEL3. Thus, the second delay DEL2-Δ moves back the edges of the digital patterned signal Qg before the next rising edge of the delayed clock signal clkd. Accordingly, the second flip-flop circuit FFC2 outputs Qr the next value of the patterned digital signal Qg, at each rising edge of the delayed clock signal clkd. Thus, the second flip-flop circuit FFC2 acts in opposition to the reference flip-flop circuit FFCr, but being cadenced by the delayed clock cycles clkd, and the output HV of the second comparator is mainly “1” together with short pulses at “0” periodically at each clock cycle during the duration of the difference between the third delay DEL3 and the second delay DEL2-Δ.

[0117] In combination of both tampered conditions, FIG. 3E “Setup and Hold Error”, the both results HV and SV are combined, i.e., the output SV of the first comparator is always “1”, and the output HV of the second comparator is mainly “1” together with short pulses at “0” periodically at each clock cycle during the duration of the difference between the third delay DEL3 and the second delay DEL2-Δ.

[0118] For the record, the digital delay cells of the first and second delay circuits DEL1, DEL2, mentioned hereinbefore and after, may for example include a series of an odd number of inverter circuits, in order to accumulate their intrinsic propagation delays. All or several of the outputs of the inverters can be inputted to a multiplexer in order to control the duration of the delay by selecting the corresponding input of the multiplexer.

[0119] FIG. 4 illustrates an example embodiment in a more high-level point of view of the system-on-chip SOC including a process-voltage-temperature (PVT) sensor SNS, such as described in relation with FIGS. 2A-2B-2C-2D-2E, and FIGS. 3A-3B-3C-3D-3E.

[0120] The PVT sensor SNS thus includes the filter circuit FLT configured to propagate the patterned digital signal, responsive to variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip SOC, and a digital comparison circuit CMP configured to generate a warning signal WS in case of discrepancies between the initiated patterned digital signal and the propagated patterned digital signal.

[0121] The PVT sensor includes an initiating stage for initiating the patterned digital signal, comprising an internal pattern signal generator PGN, for instance as described before in relation with FIGS. 2A to 3E, an external input EXT_PGN configured to receive an externally generated patterned digital signal and a multiplexer MUX configured to select the patterned digital signal from the internal source or the external source. A gate circuit GT can be provided at the output of the multiplexer MUX to able or disable the transmission of the patterned digital signal to the filter.

[0122] In addition, the PVT sensor SNS comprises a controlling logic unit, for instance a finite state machine FSM, and includes registers REG configured to store internal parameters PVT_config, CMP_config of the filter circuit FLT.

[0123] The internal parameters PVT_config, CMP_config are configurable (i.e. adapted to be modified) and determine the response of the filter circuit SNS to variations in semiconductor material Smc, operating supply voltage Vdd and operating temperature Tmp of the system-on-chip.

[0124] For instance, the internal parameters include a parameter CMP_config configuring the triggering response of comparator circuit CMP; and include the delay duration of the respective delay circuits PVT_config, for instance in relation with FIGS. 2A to 3E, the duration of delays introduced by the first delay circuit DEL1, the second delay circuit DEL2, and the third delay circuit DEL3.

[0125] The controlling logic unit (e.g., finite state machine) FSM, is provided to control the different elements of the PVT sensor, according to control signals received for example from an user or a master device of the system of chip.

[0126] For instance, the controlling logic unit (e.g., finite state machine) FSM controls the multiplexer MUX with a selection signal sel; controls the pattern generator circuit PGN with a configuration signal Patt_gen_config; controls the gate circuit GT with start and stop enabling and disabling signals; transmits the internal parameters PVT_config, CMP_config respectively to the filter circuit FLT and to the comparator circuit CMP, and receives the warning signal WS.

[0127] Additionally, the PVT sensor SNS includes a bus interface INTFC configured to receive and to emit communications on an internal bus BUS of the system on chip SOC. The internal bus BUS is for instance an AHB-type (“Advanced High-performance Bus”) internal bus, APB-type (“Advanced Peripheral Bus”) internal bus, or other types of internal buses.

[0128] For instance, the PVT sensor SNS is configured to communicate the warning signal WS (setup violation SV or hold violation HV) to a decisional unit Core #1, Core #N (FIG. 5) via the internal bus BUS.

[0129] FIG. 5 illustrates a schematic global example of the system on chip SOC including a process-voltage-temperature (PVT) sensor SNS, such as described in relation with FIGS. 2A-2B-2C-2D-2E, FIGS. 3A-3B-3C-3D-3E, and FIG. 4.

[0130] The system on chip includes in particular at least one master unit Core #1, Core #N, at least one AHB-type internal bus AHB1 and some peripherals CRYPTO, GPIO, . . . , CRC linked to the AHB-type internal bus AHB1, and at least one APB-type internal bus APB bus, and some peripherals IP #2, . . . , IP #6 linked to the APB-type internal bus APB bus.

[0131] The internal buses AHB1, APB bus are linking the corresponding peripheral circuits together in a respective bus domain AHB1, APB_1, (APB_n). Each bus domain AHB1, APB_1, (APB_n) may correspond to region of a logical part of the integrated system on chip SOC.

[0132] The other element included in the system of chip SOC depicted in FIG. 5, such as “BUS Matrix #1”, “Flash memory”, “Flash interface”, “AHB2APB bridge”, “GPDMA1”, “I-cache (8 KB)”, “MAIL BOX”, . . . are conventional example elements known by the person skilled in the art according to their drawing, and are not detailed here since they are not particularly contributing to the aspects related to the PVT sensor SNS.

[0133] The PVT sensors SNS are incorporated within the bus domains AHB1 and APB_1 in a physical proximity to the respective peripheral circuits CRYPTO, GPIO, . . . , CRC, and IP #2, . . . , IP #6.

[0134] Hence, the PVT sensors SNS are supplied with the same supply voltage and the same clock signal as the peripheral circuits of their respective bus domains AHB1, APB_1.

[0135] For example, the PVT sensors SNS include the same components as the components of the peripheral circuits CRYPTO, GPIO, . . . , CRC, and IP #2, . . . , IP #6 which are in the physical proximity to the respective PVT sensors, for instance the same electronics components such as transistors and logical gates.

[0136] This permits firstly for the PVT sensors to be sensitive to a tampering of operating condition affecting the semiconductor material of the peripheral circuits, as well as locally applied modifications of operating condition affecting the supply voltage and/or temperature of the peripheral circuits. And, secondly, with an architecture using the same components, the PVT sensors are accurately representative of the actual effects of the operating conditions over the peripheral circuits.

[0137] In another hand, the PVT sensors SNS including a bus interface INTFC configured to receive and to emit communications on the internal bus BUS, such as described in relation with FIG. 4, are advantageously capable of being operated like general-purpose peripheral circuits linked on the buses.

[0138] Thus, for example the master units Core #1, Core #N configured to execute software operations may communicate configuration commands to the PVT sensors SNS via the internal buses AHB1, APB_bus. The configuration commands are for instance configured to set (i.e. “to change”) the internal parameters PVT_config, CMP_config of the PVT sensor SNS.

[0139] As mentioned before in relation with FIG. 4, the PVT sensor SNS may be configured to communicate back the warning signal WS to a decisional unit, via the internal bus BUS. The decisional unit may execute countermeasure, such as shutting down the system of chip SOC in case of setup violation SV or hold violation HV warning signals. The decisional unit may be typically included in the master units Core #1, Core #N.

[0140] In resume, it has been described embodiments of a system on chip SOC comprising one or more PVT sensors SNS configured to detect an abnormal change in temperature and/or a supply voltage and/or semiconductor behavior of the system on chip SOC, using a reference signal (patterned digital signal) compared to a delayed version of the reference signal or to version propagated with a delayed clock. The elements that introduce the delays are sensitive to changes in process, supply voltage and temperature (PVT).

[0141] By properly comparing the reference signal with its delayed versions, it is possible to determine if variations in operating condition respect a normal operating condition or is abnormal, and therefore is indicative of an intrusion attempt by an unauthorized user, or indicative of unsafe external conditions of use.

[0142] If the PVT sensor determines an abnormal change in operating condition, then the system on chip SOC may be configured to activate one or more protection measures of the system on chip, depending on the specific application.

[0143] As a result, it is apparent that the present disclosure increases the level of security and safety of the system on chip SOC.