NORMALLY-OFF MODE POLARIZATION SUPER JUNCTION GaN-BASED FIELD EFFECT TRANSISTOR AND ELECTRICAL EQUIPMENT

Abstract

This normally-off mode polarization super junction GaN-based field effect transistor has an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12 (0<x<1), an island-like undoped GaN layer 13, a p-type GaN layer 14, a p-type In.sub.yGa.sub.1-yN layer 15 (0<y<1), a gate electrode 16 on the p-type In.sub.yGa.sub.1-yN layer 15 and a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1-xN layer 12. When the polarization charge amount of the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 and the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13 is denoted as N.sub.PZ and the thickness of the Al.sub.xGa.sub.1-xN layer 12 is denoted as d, N.sub.PZ d?2.64?10.sup.14 [cm.sup.?2 nm] is satisfied.

Claims

1-5. (canceled)

6. A normally-off mode polarization super junction GaN-based field effect transistor, comprising: a first undoped GaN layer, an Al.sub.xGa.sub.1-xN layer (0<x<1) on the first undoped GaN layer, a second undoped GaN layer having an island-like shape on the AlxGa1-xN layer, a p-type GaN layer on the second undoped GaN layer, a p-type InyGa1-yN layer (0<y<1) on the p-type GaN layer, a gate electrode electrically connected to the p-type InyGa1-yN layer, a source electrode on the Al.sub.xGa.sub.1-xN layer; and a drain electrode on the Al.sub.xGa.sub.1-xN layer, the p-type GaN layer existing on the whole surface of the second undoped GaN layer or on only one side of the surface of the second undoped GaN layer on the side of the source electrode, the p-type InyGa1-yN layer existing on only one side of the surface of the p-type GaN layer on the side of the source electrode if the p-type GaN layer exists on the whole surface of the second undoped GaN layer or existing on the whole surface or a part of the surface of the p-type GaN layer if the p-type GaN layer exists on only one side of the surface of the second undoped GaN layer on the side of the source electrode, NPZ d?2.64?1014 [cm?2 nm] being satisfied when the polarization charge amount at the hetero-interface between the AlxGa1-xN layer and the first undoped GaN layer and the hetero-interface between the AlxGa1-xN layer and the second undoped GaN layer is denoted as NPZ and the thickness of the AlxGa1-xN layer is denoted as d, the In composition y and the thickness t of the p-type InyGa1-yN layer being selected to satisfy y?t?0.20?5 [nm].

7. The normally-off mode polarization super junction GaN-based field effect transistor according to claim 6 wherein the sheet resistance of the epi substrate in which the first undoped GaN layer, the AlxGa1-xN layer, the second undoped GaN layer, the p-type GaN layer and the p-type InyGa1-yN layer are stacked on the whole surface of a substrate is not smaller than 20 k?/?.

8. The normally-off mode polarization super junction GaN-based field effect transistor according to claim 7 wherein the sheet resistance of the epi substrate is not smaller than 45 k?/?.

9. Electrical equipment, comprising: at least a transistor, the transistor being a normally-off mode polarization super junction GaN-based field effect transistor, comprising: a first undoped GaN layer, an AlxGa1-xN layer (0<x<1) on the first undoped GaN layer, a second undoped GaN layer having an island-like shape on the AlxGa1-xN layer, a p-type GaN layer on the second undoped GaN layer, a p-type InyGa1-yN layer (0<y<1) on the p-type GaN layer, a gate electrode electrically connected to the p-type InyGa1-yN layer, a source electrode on the AlxGa1-xN layer; and a drain electrode on the AlxGa1-xN layer, the p-type GaN layer existing on the whole surface of the second undoped GaN layer or on only one side of the surface of the second undoped GaN layer on the side of the source electrode, the p-type InyGa1-yN layer existing on only one side of the surface of the p-type GaN layer on the side of the source electrode if the p-type GaN layer exists on the whole surface of the second undoped GaN layer or existing on the whole surface or a part of the surface of the p-type GaN layer if the p-type GaN layer exists on only one side of the surface of the second undoped GaN layer on the side of the source electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG. 1 A cross-sectional view showing a normally-off mode polarization super junction GaN-based FET according to a first embodiment of the invention.

[0044] FIG. 2 A schematic view showing the drain current-drain voltage characteristics of the FET 1 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0045] FIG. 3 A schematic view showing the drain current-drain voltage characteristics of the FET 2 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0046] FIG. 4 A schematic view showing the drain current-gate voltage characteristics of the FET 1 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0047] FIG. 5 A schematic view showing the drain current-gate voltage characteristics of the FET 2 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0048] FIG. 6 A schematic view showing the drain current-drain voltage characteristics of the FET 1 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0049] FIG. 7 A schematic view showing the drain current-drain voltage characteristics of the FET 2 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0050] FIG. 8 A schematic view showing the drain current-gate voltage characteristics of the FETs 3, 4, 5 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0051] FIG. 9 A schematic view showing the threshold voltage V.sub.th plotted against the thickness d of the Al.sub.xGa.sub.1-xN layer (x=0.21) of the FETs 1, 2, 3, 4, 5 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0052] FIG. 10 A schematic view showing the sheet resistance of the epi substrate plotted against the thickness d of the Al.sub.xGa.sub.1-xN layer (x=0.21) of the samples 1, 2, 3 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0053] FIG. 11 A schematic view showing the relation between the Al composition x of the Al.sub.xGa.sub.1-xN layer and the polarization charge amount of the FETs 1, 2, 3, 4, 5 prepared to consider the normally-off mode polarization super junction GaN-based FET according to the first embodiment of the invention.

[0054] FIG. 12 A cross-sectional view showing a normally-off mode polarization super junction GaN-based FET according to a second embodiment of the invention.

MODES FOR CARRYING OUT THE INVENTION

[0055] Modes for carrying out the invention (hereinafter referred as embodiments) will now be explained below.

The First Embodiment

[The Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0056] As shown in FIG. 1, in the normally-off mode polarization super junction GaN-based FET according to the first embodiment, an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12 and an undoped GaN layer 13 are stacked in order on a substrate 10 via a buffer layer (not illustrated). The substrate 10 is preferably a substrate on which GaN-based semiconductor grows in C-plane orientation such as, for example, a C-plane sapphire substrate, a Si substrate, a SiC substrate and the like. The buffer layer is made of, for example, polycrystalline or amorphous GaN, AlN, AlGaN, further AlGaN/GaN superlattice and the like. The Al.sub.xGa.sub.1-xN layer 12 is typically undoped, but may be n-type or p-type Al.sub.xGa.sub.1-xN layer doped with donors (n-type impurities) or acceptors (p-type impurities). The undoped GaN layer 13 has an island-like shape. The Al.sub.xGa.sub.1-xN layer 12 is exposed around the undoped GaN layer 13. A p-type GaN layer 14 is stacked on the whole surface of the undoped GaN layer 13. The thickness of a part of the p-type GaN layer 14 on the side of a drain electrode 18 which will be described later is smaller than the thickness of a part of the p-type GaN layer 14 on the side of a source electrode 17 which will be described later. The part of the p-type GaN layer 14 having the smaller thickness corresponds to the polarization super junction region (psj region). A p-type In.sub.yGa.sub.1-yN layer 15 is stacked on the whole surface of the part of the p-type GaN layer 14 having the larger thickness. The p-type GaN layer 14 is doped with magnesium (Mg) as p-type impurities. The p-type In.sub.yGa.sub.1-yN layer 15 is also doped with Mg. The In composition y and the thickness t of the p-type In.sub.yGa.sub.1-yN layer 15 is selected as necessary and the In composition y is typically selected to be not larger than 0.20. The In composition y and the thickness t are typically selected to satisfy y?t?0.20?5 [nm] generally. For example, if y=0.10, t is selected to be about t=10 nm or smaller than this.

[0057] A gate electrode 16 is provided on the p-type In.sub.yGa.sub.1-yN layer 15. The gate electrode 16 is made of metals having large work function, for example, typically nickel (Ni) so as to bring it ohmic contact with the p-type In.sub.yGa.sub.1-yN layer 15. The gate electrode 16 may be made of a layered film made of a Ni film and another metal film stacked thereon. The source electrode 17 is provided on the Al.sub.xGa.sub.1-xN layer 12 at a part on the side of the p-type In.sub.yGa.sub.1-yN layer 15 with respect to the island-like layered structure made of the undoped GaN layer 13, the p-type GaN layer 14 and the p-type In.sub.yGa.sub.1-yN layer 15 and the drain electrode 18 is provided on the Al.sub.xGa.sub.1-xN layer 12 at a part on the opposite side with respect to the island-like layered structure. The source electrode 17 and the drain electrode 17 are made of metals having small work function, typically, for example, titanium (Ti) so as to bring it ohmic contact with the 2DEG formed in the undoped GaN layer 11 in the vicinity part of the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12 as described later. The source electrode 17 and the drain electrode 17 may be made of a layered film made of a Ti film and aluminum (Al) film, nickel (Ni) film, gold (Au) film and the like stacked thereon.

[0058] In the normally-off mode polarization super junction GaN-based FET, a part of the p-type GaN layer 14 having the smaller thickness and the undoped GaN layer 13, the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 which are just below the part form the polarization super junction region (intrinsic polarization super junction region). The p-type In.sub.yGa.sub.1-yN layer 15, a part of the p-type GaN layer 14 having the larger thickness and the undoped GaN layer 13, the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 which are just below the p-type GaN layer 14 form a gate electrode contact region.

[0059] In the normally-off mode polarization super junction GaN-based FET, due to piezo polarization and spontaneous polarization, positive fixed charge is induced in the Al.sub.xGa.sub.1-xN layer 12 in the vicinity part of the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12 on the side of the substrate 10, and negative fixed charge is induced in the Al.sub.xGa.sub.1-xN layer 12 in the vicinity part of the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13 on the opposite side of the substrate 10. As a result, in the normally-off mode polarization super junction GaN-based FET, at a non-operating time (thermal equilibrium state), a 2DHG 21 is formed in the undoped GaN layer 13 in the vicinity part of the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13 and a 2DEG 22 is formed in the undoped GaN layer 11 in the vicinity part of the hetero-interface between the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12.

[0060] In the normally-off mode polarization super junction GaN-based FET, at a non-operating time (thermal equilibrium state), no 2DEG 22 is formed in the part just below the gate electrode 16. That is, the gate threshold voltage V.sub.th>0. In order to form the 2DEG 22 in the part just below the gate electrode 16, it is necessary to apply the positive gate voltage V.sub.g which is larger than V.sub.th to the gate electrode 16.

[0061] In the normally-off mode polarization super junction GaN-based FET, if the polarization charge amount at the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 and the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13 is denoted as N.sub.PZ and the thickness of the Al.sub.xGa.sub.1-xN layer 12 is denoted as d,

N.sub.PZd?2.64?10.sup.14[cm.sup.?2 nm]

is satisfied. The sheet resistance of the epi substrate in which the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13, the p-type GaN layer 14 and the p-type In.sub.yGa.sub.1-yN layer 15 are stacked on the whole surface of the substrate 10 is preferably not smaller than 20 k?/?, more prefably not smaller than 45 k?/?. The In composition y and the thickness t of the p-type In.sub.yGa.sub.1-yN layer 15 are selected as necessary. The In composition y is typically selected to be not larger than 0.20. The In composition y and the thickness t are typically selected to satisfy y?t?0.20?5 [nm] generally. For example, if y=0.10, t is selected to be about t=10 nm or smaller than this.

[Method for Manufacturing the Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0062] First, for example, by the conventionally known MOCVD (metal organic chemical vapor deposition) method using TMG (trimethyl gallium) as Ga source, TMA (trimethyl aluminium) as Al source, NH.sub.3 (ammonia) as nitrogen source, N.sub.2 gas and H.sub.2 gas as carrier gas, a buffer layer, the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13, the p-type GaN layer 14 and the p-type In.sub.yGa.sub.1-yN layer 15 are epitaxially grown in order on the substrate 10. The growth temperature of the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13 and the p-type GaN layer 14 is, for example, about 1100? C. The growth temperature of the p-type In.sub.yGa.sub.1-yN layer 15 is for example about 950? C. which is lower than the growth temperature of the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13 and the p-type GaN layer 14 by about 150? C. As the substrate 10, a sapphire substrate (for example, a C-plane sapphire substrate), a Si substrate, a SiC substrate and the like can be used. As the buffer layer, a GaN layer, an AlN layer, an AlGaN/GaN superlattice layer and the like can be used. When, for example, the GaN layer is used as the buffer layer, it is grown in low temperature of, for example, about 530? C. As the p-type dopant for growing the p-type GaN layer 14, bis-cyclopentadienyl magnesium (Cp.sub.2 Mg) is used. As the carrier gas for growing the p-type GaN layer 14, hydrogen (H.sub.2) and nitrogen (N.sub.2) are used. As the carrier gas for growing the p-type In.sub.yGa.sub.1-yN layer 15, typically 100% N.sub.2 is used.

[0063] Then, a mask such as a resist pattern having a shape corresponding to the device forming region is formed on the p-type In.sub.yGa.sub.1-yN layer 15. Thereafter, the p-type In.sub.yGa.sub.1-yN layer 15, the p-type GaN layer 14, the undoped GaN layer 13, the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 are sequentially etched to the depth midway in the thickness direction of the undoped GaN layer 11 using the mask to carry out patterning into the predetermined shape. As a result, device isolation is carried out. Thereafter, the mask is removed.

[0064] Then, a mask such as a resist pattern having a planar shape corresponding to the p-type In.sub.yGa.sub.1-yN layer 15 shown in FIG. 1 is formed on the p-type In.sub.yGa.sub.1-yN layer 15. Thereafter, the p-type In.sub.yGa.sub.1-yN layer 15 and the p-type GaN layer 14 are sequentially etched to the depth midway in the thickness direction of the p-type GaN layer 14 using the mask to perform patterning into the predetermined shape. Thereafter, the mask is removed.

[0065] Then, a mask such as a resist pattern having a planar shape corresponding to the undoped GaN layer 13 shown in FIG. 1 is formed to cover the p-type In.sub.yGa.sub.1-yN layer 15 and the p-type GaN layer 14. Thereafter, the undoped GaN layer 13 is etched using the mask until the Al.sub.xGa.sub.1-xN layer 12 is exposed to carry out patterning into the predetermined shape. Thereafter, the mask is removed.

[0066] Then, the source electrode 17 and the drain electrode 18 are formed on the Al.sub.xGa.sub.1-xN layer 12. Thereafter, the gate electrode 16 is formed on the p-type In.sub.yGa.sub.1-yN layer 15.

[0067] In this way, the target normally-off mode polarization super junction GaN-based FET shown in FIG. 1 is manufactured.

[0068] The normally-off mode polarization super junction GaN-based FET was considered. The result is described.

[0069] First, samples were prepared for consideration. That is, first, a C-plane sapphire substrate was used as the substrate 10 and epitaxially grown in order thereon by the MOCVD method were a GaN low temperature buffer layer having a thickness of 30 nm, the undoped GaN layer 11 having a thickness of 3000 nm, the Al.sub.xGa.sub.1-xN layer 12 having a thickness of 20 nm and x=0.21, the undoped GaN layer 13 having a thickness of 30 nm, the p-type GaN layer 14 having a thickness of 20 nm and Mg concentration [Mg]=5?10.sup.19 cm.sup.?3 and the p-type In.sub.yGa.sub.1-yN layer 15 having a thickness of 50 nm, y=0.20 and Mg concentration [Mg]=1?10.sup.20 cm.sup.?3. The growth temperature of the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13 and the p-type GaN layer 14 was set to 1100? C. The growth temperature of the p-type In.sub.yGa.sub.1-yN layer 15 was set to 950? C. As carrier gas during growth, 100% N.sub.2 was used. The epi substrate thus obtained is used as a sample 1. Only the thickness of the Al.sub.xGa.sub.1-xN layer 12 was changed to 15 nm and the similar epitaxial growth was carried out on the C-plane sapphire substrate. The epi substrate thus obtained is used as a sample 2.

[0070] The sheet resistance of the samples 1, 2 was measured by eddy current method. As a result, the sheet resistance (average value) of the samples 1, 2 were 45300?/? and 77500?/?, respectively.

[0071] In addition to the samples 1, 2, only the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12, which are the base layers of the sample 1, were grown on the C-plane sapphire substrate. The epi substrate thus obtained is used as a sample 3. The sheet resistance of the sample 3 was measured by eddy current method. As a result, the sheet resistance (average value) was 578?/?. Incomparably large sheet resistance of the samples 1, 2 compared with the sample 3 means that in the samples 1, 2, the energy band was greatly lifted up by the p-type In.sub.yGa.sub.1-yN layer 15/the p-type GaN layer 14/the undoped GaN layer 13 stacked on the AlGaN/GaN base layer (the undoped GaN layer 11 and the Al.sub.xGa.sub.1-xN layer 12) to greatly decrease the 2DEG concentration and the 2DEG was almost depleted.

[0072] A polarization super junction GaN-based FET was prepared based on the manufacturing method described above using the samples 1, 2.

[0073] First, etching for device isolation was carried out to the depth of about 200 nm from the surface of the samples 1, 2 by ICP (induction coupled plasma)-RIE (reactive ion etching) using chlorine (Cl)-based gas.

[0074] Then, the gate electrode contact region was masked and the p-type GaN layer 14 was etched to the depth midway in the thickness direction until the remained thickness of the p-type GaN layer 14 reaches 10 nm. Thereafter, the gate electrode contact region and the psj region were masked and finally the undoped GaN layer 13 was etched to expose the Al.sub.xGa.sub.1-xN layer 12.

[0075] Then, the surface of the region except the region in which the source electrode 17 and the drain electrode 18 are formed was masked by an SiO.sub.2 film and a Ti/Al/Ni/Au layered film was formed on the source electrode forming part and the drain electrode forming part by the vacuum evaporation method to form the source electrode 17 and the drain electrode 18. Thereafter, ohmic alloy treatment of 800? C. and 60 seconds was carried out in N.sub.2.

[0076] Then, the surface of the region except the region in which the gate electrode 16 is formed was masked by an SiO.sub.2 film and a Ti/Ni/Au layered film was formed on the p-type In.sub.yGa.sub.1-yN layer 15 by the vacuum evaporation method to form the gate electrode 16. Thereafter, ohmic alloy treatment was carried out by carrying out a rapid thermal annealing (RTA) of 500? C. and 100 seconds in N.sub.2.

[0077] Thereafter, using a polyimide mask Au was deposited by electroplating to a thickness of about 2 ?m on the source electrode 17 and the drain electrode 18.

[0078] The voltage resistance of the polarization super junction GaN-based FET depends on the length of the psj region. Here, the psj length was set to 20 ?m.

[0079] The FET prepared using the sample 1 is referred as the FET 1 and the FET prepared using the sample 2 is referred as the FET 2.

[0080] Transistor characteristics of the FET 1 and the FET 2 were measured.

(Drain Current (I.sub.d)Drain Voltage (V.sub.d) Characteristics)

[0081] FIG. 2 and FIG. 3 show the I.sub.d-V.sub.d characteristics of the FET 1 and the FET 2, respectively. The gate width (W.sub.g) of the FET 1 and the FET 2 was about 190 mm. The gate voltage V.sub.g of 0 V to +4 V was applied. It is shown that I.sub.d=0 A for V.sub.g=0 V in the FET 1 and I.sub.d=0 A for V.sub.g=+1 V in the FET 2. This shows that the FET 1 and the FET 2 are normally-off mode FETs. I.sub.d of the FET 1 is larger than I.sub.d of the FET 2 because the thickness of the Al.sub.xGa.sub.1-xN layer 12 of the FET 1 is 20 nm, which is larger than the thickness of the Al.sub.xGa.sub.1-xN layer 12 (15 nm) of the FET 1, and therefore the 2DEG concentration of the psj region is large, which results in small channel resistance.

(Drain Current (I.sub.d)Gate Voltage (V.sub.g) Characteristics)

[0082] In order to evaluate the threshold voltage V.sub.th, the I.sub.d-V.sub.g characteristics of the FET 1 and the FET 2 were measured. The results are shown in FIG. 4 and FIG. 5. Vertical axes of FIG. 4 and FIG. 5 are the logarithmic axis. Although V.sub.g was changed from ?2 V to +4 V, V.sub.g is shown only to +2 V in FIG. 4 and FIG. 5. The maximum value of I.sub.d was set to 1 A due to the reason of measurement system used. In FIG. 2 and FIG. 3, the saturation currents were 20 A, 15 A, respectively. On the other hand, in FIG. 4 and FIG. 5, V.sub.g showing the value of I.sub.d of 1/100 of the saturation current. If this V.sub.g is denoted as V.sub.th, V.sub.th of the FET 1 is about +0.3 V and V.sub.th of the FET 2 is +1.0 V. Here, V.sub.th was defined as V.sub.g when I.sub.d is 1/100 of the maximum rating drain current because the circuit system can be substantially protected by the normally-off mode FET when the gate signal was lost.

(Voltage Resistance Characteristics)

[0083] In order to evaluate the voltage resistance of the FET 1 and the FET 2, I.sub.d was measured by applying V.sub.d to 1200 V at the maximum when V.sub.g=?2 V was set in the FET 1 and V.sub.g=0 V was set in the FET 2. FIG. 6 and FIG. 7 show the result of measurement of I.sub.d-V.sub.d characteristics of the FET 1 and the FET 2, respectively. As shown in FIG. 6 and FIG. 7, voltage resistance of the FET 1 and the FET 2 is very high and leakage current was about 1 ?A when V.sub.d=1200 V.

(Relation Between the Thickness of the Al.sub.xGa.sub.1-xN Layer 12 and V.sub.th)

[0084] The growth of the p-type In.sub.yGa.sub.1-yN layer on the GaN layer is restricted by the difference of lattice constants and the solubility of Mg dopants. Therefore, when an excellent polarization super junction GaN-based FET is manufactured, the limits of the In composition y and the Mg concentration are about 0.2 (about 20%) and 1?10.sup.20 cm.sup.?3, respectively. Here, when the condition of the p-type In.sub.yGa.sub.1-yN layer was fixed, considered was the thickness of the Al.sub.xGa.sub.1-xN layer which has the most significant influence on V.sub.th. The Al composition x of the Al.sub.xGa.sub.1-xN layer was set to 0.21(21%).

[0085] Newly prepared were FETs having the thickness of the Al.sub.xGa.sub.1-xN layer having three levels of 25 nm, 27 nm and 30 nm and having the same structure as the FET 1 and the FET 2 other than this. Here, W.sub.g=1 mm was used. The FET having the thickness of the Al.sub.xGa.sub.1-xN layer 12 of 25 nm is referred as the FET 3. The FET having the thickness of the Al.sub.xGa.sub.1-xN layer 12 of 27 nm is referred as the FET 4. The FET having the thickness of the Al.sub.xGa.sub.1-xN layer 12 of 30 nm is referred as the FET 5.

[0086] The I.sub.d-V.sub.d characteristics of the FET 3, the FET 4 and the FET 5 were measured. The result is shown in FIG. 8. As shown in FIG. 8, V.sub.th shifted deeply (to the negative side) in the order of the FET 3, the FET 4 and the FET 5 having the thickness of the Al.sub.xGa.sub.1-xN layer 12 sequentially increasing.

[0087] FIG. 9 shows V.sub.th at 1/100 of the saturation current value in FIG. 8 of the FET 3, the FET 4 and the FET 5 plotted against the thickness of the Al.sub.xGa.sub.1-xN layer 12. In FIG. 9, V.sub.th of the FET 1 and the FET 2 is also plotted. It is understood from FIG. 9 that when the thickness of the Al.sub.xGa.sub.1-xN layer 12 is not larger than 22 nm, V.sub.th>0. The sheet resistance of the epi substrate in which the thickness of the Al.sub.xGa.sub.1-xN layer 12 is 25 nm was examined. The sheet resistance measured by eddy current method of the epi substrate on which the FET 3 in which the thickness of the Al.sub.xGa.sub.1-xN layer 12 is 25 nm was formed(referred as a sample 3) was 3.879 k?/? (average value). FIG. 10 shows plotting of the sheet resistance of the sample 1, the sample 2 and the sample 3. It is understood from FIG. 10 that the sheet resistance of the epi substrate in which the thickness of the Al.sub.xGa.sub.1-xN layer 12 is 22 nm and V.sub.th is just 0 V was about 20 k?/?. Therefore, condition of realizing normally-off mode is that the epi substrate has the sheet resistance not smaller than this. From FIG. 10, the sheet resistance of the sample 1 is 45 k?/?. Therefore, if the sheet resistance is not smaller than 45 k?/?, it is possible to realize normally-off mode more surely.

(Condition of the Al.sub.xGa.sub.1-xN Layer 12 for Realizing Normally-Off Mode)

[0088] It is understood from the above result that if the thickness of the Al.sub.xGa.sub.1-xN layer 12 having x=0.21 (21%) is not larger than about 22 nm, the polarization super junction GaN-based FET becomes normally-off. However, it is considered that the structure for realizing V.sub.th>0 is not limited to the above structure.

[0089] Therefore, based on the above knowledge, condition for realizing normally-off mode of the polarization super junction GaN-based FET is considered again.

[0090] The Al.sub.xGa.sub.1-xN layer 12 is considered again.

[0091] V.sub.th of a normal AlGaN/GaN HEMT is expressed by the following equation.

[Eq 1]

[0092] [00001]$\begin{array}{cc}{V}_{\mathrm{th}}={?}_B-\frac{{\mathrm{qN}}_{\mathrm{PZ}}d}{{?}_s}-\frac{?E_c}{q}& \left(1\right)\end{array}$

Here, ?.sub.B is Schottky barrier height, q is electron charge, ?.sub.s is dielectric constant, N.sub.PZ is the polarization charge amount, d is the thickness of the AlGaN layer and ?E.sub.c is the barrier height of the conduction band of AlGaN/GaN. The polarization charge amount N.sub.PZ relates to the Al composition x of the AlGaN layer.

[0093] V.sub.th=0 V, in brief, is condition that the 2DEG below the gate electrode depletes at V.sub.g=0 V.

[0094] With respect to the electron concentration of the AlGaN/GaN HEMT which is the base of the polarization super junction GaN-based FET, supposing electron mobility is ?1000 cm.sup.2/Vs, by calculating backward from the sheet resistance of 575?/? obtained by the experimental value of the sheet resistance described above, the 2DEG concentration is about 1.08?10.sup.13 cm.sup.?2. The 2DEG concentration corresponds to V.sub.th of ?4 V of the normal HEMT, which is a very deep negative value. Therefore, in the normally-off mode polarization super junction GaN-based FET, while the normal AlGaN/GaN HEMT structure has a negative V.sub.th, ?.sub.B of the equation (1) is lifted up by adding the stacking structure of the p-type In.sub.yGa.sub.1-yN layer 15/the p-type GaN layer 14/the undoped GaN layer 13 to the AlGaN/GaN HEMT structure.

[0095] Paying attention to the second term of the equation (1), since V.sub.th=0 V was obtained experimentally for the Al.sub.xGa.sub.1-xN layer 12 having x=0.21 (21%) and d=22 nm, the limitation condition of V.sub.th?0 is

N.sub.PZd?N.sub.PZ(x=0.21)?22[nm](2)

Here, N.sub.PZ (x=0.21) means N.sub.PZ for x=0.21.

[0096] FIG. 11 shows the relation between the polarization charge amount N.sub.PZ of the Al.sub.xGa.sub.1-xN/GaN HEMT structure and the Al composition x of the Al.sub.xGa.sub.1-xN layer 12 (reprinted from FIG. 9 of non-patent literature 3 after touched in partly). From FIG. 11, N.sub.PZ (x=0.21) is

1.2?10.sup.13[cm.sup.?2](3)

[0097] Therefore, from the equation (2) and the equation (3) condition of the base Al.sub.xGa.sub.1-xN/GaN is as follows.

N.sub.PZd?N.sub.PZ(x=0.21)?22[nm]=26.4?10.sup.13[cm.sup.?2 nm]

That is,

N.sub.PZd?2.64?10.sup.14[cm.sup.?2 nm](4)

[0098] That is, the equation (4) can be used as stacking condition of the base Al.sub.xGa.sub.1-xN/GaN without limiting the Al composition x to 0.21.

[0099] As described above, according to the first embodiment, it is possible to easily realize a normally-off mode polarization super junction GaN-based FET by the layer structure of the undoped GaN layer 11, the Al.sub.xGa.sub.1-xN layer 12, the undoped GaN layer 13, the p-type GaN layer 14 and the p-type In.sub.yGa.sub.1-yN layer 15 and the limitation of condition such as N.sub.PZ d?2.64?10.sup.14 [cm.sup.?2 nm], without using complicated circuits such as a cascode circuit or modified cascode circuit using low voltage resistance normally-off mode Si MOS transistors such as FIG. 57A, FIG. 57B, FIG. 57C and FIG. 57D of patent literature 1 or FIGS. 32A-E of patent literature 2 and further without using complicated processes such as forming a deep groove in the Al.sub.xGa.sub.1-xN layer 12 and burying the gate electrode in the groove as shown in FIG. 31 of patent literature 2.

The Second Embodiment

[The Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0100] As shown in FIG. 12, the normally-off mode polarization super junction GaN-based FET according to the second embodiment is different from the normally-off mode polarization super junction GaN-based FET according to the first embodiment in that the p-type GaN layer 14 does not exist in the polarization super junction region similar to patent literature 1. Other than the above is the same as the normally-off mode polarization super junction GaN-based FET according to the first embodiment.

[Method for Manufacturing the Normally-Off Mode Polarization Super Junction GaN-Based FET]

[0101] The method for manufacturing the normally-off mode polarization super junction GaN-based FET is the same as the method for manufacturing the normally-off mode polarization super junction GaN-based FET according to the first embodiment except that the p-type GaN layer 14 is not finally formed on the undoped GaN layer 13 in the polarization super junction region.

[0102] According to the second embodiment, the same advantage as the first embodiment can be obtained.

[0103] Heretofore, embodiments of the present invention have been explained specifically. However, the present invention is not limited to these embodiments, but contemplates various changes and modifications based on the technical idea of the present invention.

[0104] For example, numerical numbers, structures, shapes, materials and the like presented in the aforementioned embodiments are only examples, and the different numerical numbers, structures, shapes, materials and the like may be used as needed.

EXPLANATION OF REFERENCE NUMERALS

[0105] 10 Substrate [0106] 11 Undoped GaN layer [0107] 12 Al.sub.xGa.sub.1-xN layer [0108] 13 Undoped GaN layer [0109] 14 p-type GaN layer [0110] 15 p-type In.sub.yGa.sub.1-yN layer [0111] 16 Gate electrode [0112] 17 Source electrode [0113] 18 Drain electrode [0114] 19 2DHG [0115] 20 2DEG