Memory device and computing method using the same

Abstract

A memory device is provided. The memory device includes a memory array of a plurality of memory elements, a plurality of word lines or word line pairs, a plurality of bit line pairs, and a plurality of common source lines. Each of the memory elements includes two memory cells. The memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.

Claims

1. A memory device, comprising: a memory array of a plurality of memory elements, each of the memory elements comprising two memory cells; a plurality of word lines or a plurality of word line pairs connected to rows of the memory array; a plurality of bit line pairs connected to columns of the memory array; and a plurality of common source lines connected to the columns of the memory array; wherein the memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.

2. The memory device according to claim 1, wherein the two memory cells of each of the memory elements that is not arranged at a diagonal of the memory array perform a logic XNOR operation.

3. The memory device according to claim 1, wherein each of the memory cells has a tunable threshold voltage or a tunable resistance.

4. The memory device according to claim 1, wherein each of the memory cells comprises a transistor.

5. The memory device according to claim 1, wherein each of the memory cells comprises a transistor and a resistor.

6. The memory device according to claim 1, wherein each of the memory elements comprise two transistors of same type or two transistors of complementary type.

7. The memory device according to claim 1, wherein each of the memory cells is a floating gate cell, a charge trapping cells, or a FeFET cell.

8. The memory device according to claim 1, wherein each of the memory cells is a ReRAM cell, a CBRAM cell, a PCM cell, or a MRAM cell.

9. The memory device according to claim 1, wherein one of the two memory cells of each of the memory elements is coupled to the corresponding word line or a word line of the corresponding word line pair, a bit line of the corresponding bit line pair, and the corresponding common source line, and the other one of the two memory cells of each of the memory elements is coupled to the corresponding word line or the other word line of the corresponding word line pair, the other bit line of the corresponding bit line pair, and the corresponding common source line.

10. A computing method, wherein the computing method calculates an energy value based on a plurality of state signals and a plurality of coefficients, wherein the computing method uses a memory device, the memory device comprises a memory array of a plurality of memory elements, and each of the memory elements comprises two memory cells, and wherein the computing method comprises: setting up the state signals in the memory array, comprising: conducting a complementary read operation for individually selecting one of the two memory cells of each of the memory elements for receiving two corresponding state signals; and inputting the state signals into the selected memory cells of the memory elements, wherein the selected memory cells generates a plurality of output currents; and calculating the energy value corresponding to the state signals based on a sum value of the output currents.

11. The computing method according to claim 10, wherein the complementary read operation comprises flipping a corresponding state signal if a trigger condition is met.

12. The computing method according to claim 11, wherein the trigger condition is represented by:
R?[0,1]>U, wherein R is a given random value, and U is a threshold value.

13. The computing method according to claim 12, wherein U is 0.5.

14. The computing method according to claim 10, further comprising: before said setting up the state signals, mapping the coefficients to the memory array.

15. The computing method according to claim 14, wherein said mapping the coefficients is achieved by tuning threshold voltages or resistances of the two memory cells of each of the memory elements.

16. The computing method according to claim 10, further comprising: after said calculating the energy value corresponding to the state signals, updating the state signals according a transition probability of the energy value.

17. The computing method according to claim 16, wherein said setting up the state signals, said calculating the energy value corresponding to the state signals, and said updating the state signals are repeated until a predetermined finish condition is met, and the computing method further comprises: after end of repetition, observing the state signals.

18. The computing method according to claim 10, applying quantum annealing algorithm employing Ising model without an external field term.

19. The computing method according to claim 10, wherein the state signals correspond to spins of sites selected from +1 and ?1, and the coefficients are interaction coefficients between the sites.

20. The computing method according to claim 10, wherein the two memory cells of each of the memory elements that is not arranged at a diagonal of the memory array perform a logic XNOR operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A-1B illustrate Ising model.

(2) FIG. 2 illustrates annealing algorithms.

(3) FIG. 3 illustrates a memory device according to the disclosure.

(4) FIGS. 4-9 illustrate various exemplary memory elements which may be used in a memory device according to the disclosure.

(5) FIGS. 10A-10F illustrate various operations for one kind of exemplary memory elements according to the disclosure.

(6) FIG. 11 illustrates a complementary read operation according to the disclosure.

(7) FIG. 12 illustrates a computing method according to the disclosure.

(8) FIG. 13 illustrates an application of a computing method according to the disclosure.

(9) FIG. 14 illustrates an advantage of a computing method according to the disclosure.

(10) In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

DETAILED DESCRIPTION

(11) Various embodiments will be described more fully hereinafter with reference to accompanying drawings. The description and the drawings are provided for illustrative only, and not intended to result in a limitation. For clarity, the elements may not be drawn to scale. In addition, some elements and/or reference numerals may be omitted from some drawings. It is contemplated that the elements and features of one embodiment can be beneficially incorporated in another embodiment without further recitation.

(12) Referring to FIGS. 1A-1B, Ising model is illustrated. Ising model can describe the energy of a magnetic material with particular spins. FIG. 1A shows a simplest Ising model. This model comprises two sites having state signals ?.sub.1 and ?.sub.2, respectively. The state signals ?.sub.1 and ?.sub.2 correspond to spins of sites independently selected from +1 (i.e., spin in a positive direction, typically represented by an upward arrow) and ?1 (i.e., spin in a negative direction, typically represented by a downward arrow). For each site, the effect of external magnetic field interacting with the site is represented by a self coefficient h.sub.1 or h.sub.2 representing. In addition, the interaction between the sites is represented by an interaction coefficient J.sub.12. As such, the energy H of the configuration may be represented by formula (1).
H=h.sub.1?.sub.1+h.sub.2?.sub.2+J.sub.12?.sub.1?.sub.2(1)

(13) According to formula (1), energy H may be computed for different configurations of the state signals ?.sub.1 and ?.sub.2 (i.e., ?.sub.1=?1 and ?.sub.2=?1, ?.sub.1=?1 and ?.sub.2=+1, ?.sub.1=+1 and ?.sub.2=+1, and ?.sub.1=+1 and ?.sub.2=?1). For example, given h.sub.1=0.1, h.sub.2=?0.2, and J.sub.12=?0.3, the minimum energy H.sub.min will be obtained when both of ?.sub.1 and ?.sub.2 are +1, as shown in FIG. 1B. At this time, the Ising model system has an optimal solution. In other words, if an optimization problem corresponds to these conditions, its solution is the configuration in which ?.sub.1=?1 and ?.sub.2=+1.

(14) FIG. 2 illustrates annealing algorithms. There are N state signals ?.sub.1, ?.sub.2 . . . ?.sub.N in each of configurations 200, 202, 204, and 206. In a path corresponding to simulated annealing algorithm, a temporary solution is the configuration 200 having a local minimum energy, with thermal fluctuations, the state signals are updated to the configuration 202, and finally to the configuration 204 having the minimum energy H.sub.min in all configurations. In a path corresponding to quantum annealing algorithm, a temporary solution is the configuration 206 having a local minimum energy, and with quantum tunneling, the state signals are updated to the configuration 204 having the minimum energy H.sub.min in all configurations.

(15) The disclosure provides a memory device, which can be used for computation of the algorithm. The memory device comprises a memory array of a plurality of memory elements, a plurality of word lines or a plurality of word line pairs, a plurality of bit line pairs, and a plurality of common source lines. Each of the memory elements comprises two memory cells. The word lines or the word line pairs are connected to rows of the memory array. The bit line pairs are connected to columns of the memory array. The common source lines are connected to the columns of the memory array. The memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.

(16) FIG. 3 illustrates an exemplary memory according to the disclosure. The memory device comprises a memory array of a plurality of memory elements M, a plurality of word line pairs WL1p . . . WLnp, a plurality of bit line pairs BL1p . . . BLnp and a plurality of common source lines CSL. The word line pairs WL1p . . . WLnp are connected to rows of the memory array. The word line pairs WL1p . . . WLnp comprise first word lines WL1a . . . WLna and second word lines WL1b . . . WLnb, wherein the word line pair WL1p comprise the paired first and second word lines WL1a and WL1b, the word line pair WL2p comprise the paired first and second word lines WL2a and WL2b, and so on. The word line pairs WL1p . . . WLnp are configured for receiving state signals ?.sub.1 . . . ?.sub.N, respectively. The bit line pairs BL1p . . . BLnp are connected to columns of the memory array. The bit line pairs BL1p . . . BLnp comprise first bit lines BL1a . . . BLna and second bit lines BL1b . . . BLnb, wherein the bit line pair BL1p comprise the paired first and second bit lines BL1a and BL1b, the bit line pair BL2p comprise the paired first and second bit lines BL2a and BL2b, and so on. The bit line pairs BL1p . . . BLnp are configured for receiving state signals ?.sub.1 . . . ?.sub.N, respectively. The common source lines CSL are connected to the columns of the memory array.

(17) Referring to FIG. 4, an exemplary memory element M for the memory array shown in FIG. 3 is illustrated. Each of the memory elements M comprises two memory cells Ma and Mb. One of the two memory cells Ma and Mb is coupled to a word line of the corresponding word line pair WLp, a bit line of the corresponding bit line pair BLp, and the corresponding common source line CSL, and the other one of the two memory cells Ma and Mb is coupled to the other word line of the corresponding word line pair WLp, the other bit line of the corresponding bit line pair BLp, and the corresponding common source line CSL. For example, the memory cell Ma is coupled to the first word line WLa, the first bit line BLa, and the corresponding common source line CSL, and the memory cell Mb is coupled to the second word line WLb, the second bit line BLb, and the corresponding common source line CSL. In FIG. 4, the memory element M is illustrated as a 2T floating gate device. Each of the memory cells Ma and Mb comprises a transistor, and the two transistors are of same type, such as n-type. Each of the memory cells Ma and Mb may have a tunable threshold voltage. Each of the memory cells Ma and Mb may be a floating gate cell, a charge trapping cells, a FeFET (ferroelectric field effect transistor) cell, or the like.

(18) It is appreciated that various kinds of memory elements may be used in the memory array according to the disclosure with suitable modifications to the corresponding lines and layout. According to some embodiments, each of the memory cells may have a tunable threshold voltage or a tunable resistance. According to some embodiments, each of the memory cells may comprise a transistor or comprise a transistor and a resistor. According to some embodiments, each of the memory elements M may comprise two transistors of same type or two transistors of complementary type. According to some embodiments, each of the memory cells may be a floating gate cell, a charge trapping cells, a FeFET cell, a ReRAM (resistive random access memory) cell, a CBRAM (conductive bridge random access memory) cell, a PCM (phase change memory) cell, or a MRAM (magnetoresistive random access memory) cell, but not limited thereto.

(19) FIGS. 5-9 illustrate some other exemplary memory elements which may be used in a memory device according to the disclosure. In FIG. 5, the memory element M is illustrated to have an inverter-like structure. Each of the memory cells Ma and Mb comprises a transistor. The two transistors are of complementary type. The two memory cells Ma and Mb are coupled to the same word line WL. In other words, one of the two memory cells Ma is coupled to the corresponding word line WL, and the other one of the two memory cells Mb is coupled to the corresponding word line WL. It can be contemplated that the memory device will comprise a plurality of word lines rather than the word line pairs described above connected to the rows of the memory array. Each of the memory cells Ma and Mb may have a tunable threshold voltage. Each of the memory cells Ma and Mb may be a floating gate cell, a charge trapping cells, a FeFET cell, or the like.

(20) In FIG. 6, the memory element M is illustrated as a 2T2R device. Each of the memory cells Ma and Mb comprises a transistor and a resistor. The two transistors are of same type. The resistor is arranged between the transistor and the corresponding first or second bit line BLa or BLb. Each of the memory cells Ma and Mb may have a tunable resistance. Each of the memory cells Ma and Mb may be ReRAM cell, a CBRAM cell, a PCM cell, a MRAM cell, or the like.

(21) In FIG. 7, the memory element M is illustrated as a 2T2R device. Each of the memory cells Ma and Mb comprises a transistor and a resistor. The two transistors are of same type. The resistor is arranged between the transistor and the common source line CSL. Each of the memory cells Ma and Mb may have a tunable resistance. Each of the memory cells Ma and Mb may be ReRAM cell, a CBRAM cell, a PCM cell, a MRAM cell, or the like.

(22) In FIG. 8, the memory element M is illustrated as a 2T2R device. Each of the memory cells Ma and Mb comprises a transistor and a resistor. The two transistors are of complementary type. The two memory cells Ma and Mb are coupled to the same word line WL. The resistor is arranged between the transistor and the corresponding first or second bit line BLa or BLb. Each of the memory cells Ma and Mb may have a tunable resistance. Each of the memory cells Ma and Mb may be ReRAM cell, a CBRAM cell, a PCM cell, a MRAM cell, or the like.

(23) In FIG. 9, the memory element M is illustrated as a 2T2R device. Each of the memory cells Ma and Mb comprises a transistor and a resistor. The two transistors are of complementary type. The two memory cells Ma and Mb are coupled to the same word line WL. The resistor is arranged between the transistor and the common source line CSL. Each of the memory cells Ma and Mb may have a tunable resistance. Each of the memory cells Ma and Mb may be ReRAM cell, a CBRAM cell, a PCM cell, a MRAM cell, or the like.

(24) Now referring to FIGS. 10A-10F as well as FIG. 3 and FIG. 4, the operations of the memory elements M will be provided more fully hereinafter with the exemplary structure as shown in FIGS. 3 and 4.

(25) According to the disclosure, the memory device can be configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients. The two memory cells Ma and Mb of each of the memory elements M are configured for performing an individual selection such that one of the memory cells Ma or Mb of each of the memory elements M receives two corresponding state signals from the corresponding word line pair WLp and the corresponding bit line pair BLp and generates an output current into a corresponding common source line CSL for calculating the energy value.

(26) According to some embodiments, the memory elements M that are not arranged at a diagonal of the memory array may be used to compute the interaction term of the energy. Exemplary interaction coefficient J.sub.12, J.sub.13, J.sub.1N, J.sub.21, J.sub.23, J.sub.2N, J.sub.31, J.sub.32, J.sub.3N, J.sub.N1, J.sub.N2, and J.sub.N3 are shown in FIG. 3 at corresponding memory elements M. In such conditions, the two memory cells Ma and Mb of each of the memory elements M that is not arranged at a diagonal of the memory array may perform a logic XNOR operation, which may be represented by formula 2.
?.sub.iXNOR?.sub.j=(??.sub.i)XNOR(??.sub.j)(2)

(27) Specifically, as shown in FIG. 10A, when the state signal ?.sub.i is ?1, a zero voltage is applied to the first word line WLa, and a word line voltage V.sub.WL is applied to the second word line WLb. When the state signal ?.sub.j is ?1, a zero voltage is applied to the first bit line BLa, and a bit line voltage V.sub.BL is applied to the second bit line BLb. In such a condition, a current is output from the memory cell Mb, as indicated by the arrow shown in FIG. 10A. As shown in FIG. 10B, when the state signal ?.sub.i is ?1, a zero voltage is applied to the first word line WLa, and a word line voltage V.sub.WL is applied to the second word line WLb. When the state signal ?.sub.j is +1, a bit line voltage V.sub.BL is applied to the first bit line BLa, and a zero voltage is applied to the second bit line BLb. In such a condition, no current is output from the memory element M. As shown in FIG. 10C, when the state signal ?.sub.i is +1, a word line voltage V.sub.WL is applied to the first word line WLa, and a zero voltage is applied to the second word line WLb. When the state signal ?.sub.j is ?1, a zero voltage is applied to the first bit line BLa, and a bit line voltage VBA is applied to the second bit line BLb. In such a condition, no current is output from the memory element M. As shown in FIG. 10D, when the state signal ?.sub.i is +1, a word line voltage V.sub.WL is applied to the first word line WLa, and a zero voltage is applied to the second word line WLb. When the state signal ?.sub.j is +1, a bit line voltage VBA is applied to the first bit line BLa, and a zero voltage is applied to the second bit line BLb. In such a condition, a current is output from the memory cell Ma, as indicated by the arrow shown in FIG. 10D. The output current when both of ?.sub.i and a are ?1 will equal to the output current when both of ?.sub.i and ?.sub.j are +1. The same output current IA may be represented by formula (3).

(28) $\begin{array}{cc}{I}_{\mathrm{Jij}}?J_{\mathrm{ij}}.Math.\left({?}_i\mathrm{XNOR}{?}_j\right)=J_{\mathrm{ij}}.Math.\frac{1}{2}\left({?}_i{?}_j+1\right)& \left(3\right)\end{array}$

(29) In some embodiments, the idle memory elements M that are arranged at a diagonal of the memory array may be used to compute the external field term of the energy. Exemplary self coefficient h.sub.1, h.sub.2, h.sub.3, and h.sub.N are shown in FIG. 3 at corresponding memory elements M. In such conditions, the two memory cells Ma and Mb of each of the memory elements M that is arranged at a diagonal of the memory array may perform a logic AND operation.

(30) Specifically, as shown in FIG. 10E, when the state signal ?.sub.i is ?1, a zero voltage is applied to the first word line WLa, and a word line voltage V.sub.WL is applied to the second word line WLb. When the state signal ?.sub.j is ?1, a zero voltage is applied to the first bit line BLa, and a bit line voltage V.sub.BL is applied to the second bit line BLb. However, the memory cell Mb has been masked by a high threshold voltage previously. As such, no current is output from the memory element M. As shown in FIG. 10F, when the state signal ?.sub.i is +1, a word line voltage V.sub.WL is applied to the first word line WLa, and a zero voltage is applied to the second word line WLb. When the state signal ?.sub.j is +1, a bit line voltage V.sub.BL is applied to the first bit line BLa, and a zero voltage is applied to the second bit line BLb. In such a condition, a current is output from the memory cell Ma, as indicated by the arrow shown in FIG. 10F. The output current I.sub.h may be represented by formula (4).

(31) $\begin{array}{cc}{I}_h?h_i.Math.\left({?}_i\mathrm{AND}{?}_i\right)=h_i.Math.\frac{1}{2}\left({?}_i+1\right)& \left(4\right)\end{array}$

(32) In a memory element M as shown in FIG. 5, when the state signal ?.sub.i is +1, a word line voltage V.sub.WL is applied to the word line, and further to gate of the two transistors. When the state signal ?.sub.i is ?1, a word line voltage ?V.sub.WL is applied to the word line, and further to gate of the two transistors. When the state signal ?.sub.j is +1, a bit line voltage V.sub.BL and a zero voltage are applied to the first and second bit lines BLa and BLb, and further to the drains of the transistors of the memory cells Ma and Mb, respectively. When the state signal ?.sub.j is ?1, a zero voltage and a bit line voltage V.sub.BL are applied to the first and second bit lines BLa and BLb, and further to the drains of the transistors of the memory cells Ma and Mb, respectively.

(33) As described above, each of the memory elements M can couple the two state signal ?.sub.i and ?.sub.j from the corresponding word line pair WLp and bit line pair BLp, and provides a coupling result based on the encoding strategy of, for example, threshold voltage. It is beneficial to use the memory array for computation since the energies of spins can be calculated in a parallel manner.

(34) As shown in FIG. 11, occasionally, one of the memory cells in the memory elements M, such as the memory cell Ma, is damaged. The individual selection for selecting one of the two memory cells to receive the two corresponding state signals for calculating the energy value can ensure that, at least in some cycles, the computation is conducted using the normal memory cell Mb, and thus will not be affected by the damaged memory cell Ma. As such, a larger standard deviation of the tunable threshold voltage or resistance can be tolerated in the memory device for the computation. The flipping between the two conditions as shown in FIG. 11 is somewhat analogous to the vibration of an atom on a lattice site. The details of such an operation will be provided more fully in following paragraphs with respect to the computing method.

(35) The disclosure also provides a computing method. The computing method calculating an energy value based on a plurality of state signals and a plurality of coefficients. The computing method uses a memory device. The memory device comprises a memory array of a plurality of memory elements. Each of the memory elements comprises two memory cells. The computing method comprises: setting up the state signals in the memory array, comprising: conducting a complementary read operation for individually selecting one of the two memory cells of each of the memory elements for receiving two corresponding state signals; and inputting the state signals into the selected memory cells of the memory elements, wherein the selected memory cells generates a plurality of output currents; and calculating the energy value corresponding to the state signals based on a sum value of the output currents.

(36) FIG. 12 illustrates the flow chart of an exemplary computing method according to the disclosure.

(37) In step S1, the coefficients are mapped to the memory array. According to some embodiments, the computation may be focused on the interaction term of the energy. As such, the coefficients are interaction coefficients between sites. Exemplary interaction coefficient J.sub.12, J.sub.13, J.sub.1N, J.sub.21, J.sub.23, J.sub.2N, J.sub.31, J.sub.32, J.sub.3N, J.sub.N1, J.sub.N2, and J.sub.N3 are shown in FIG. 3 at corresponding memory elements M. As shown in FIG. 3, the computation may be conducted by the memory elements that are not arranged at a diagonal of the memory array. For example, the two memory cells of each of the memory elements that is not arranged at a diagonal of the memory array may perform a logic XNOR operation. In some embodiments, the computation may further comprise the external field term of the energy. The coefficients to be mapped comprise interaction coefficients and the self coefficients. Exemplary self coefficient h.sub.1, h.sub.2, h.sub.3, and h.sub.N are shown in FIG. 3 at corresponding memory elements M. As shown in FIG. 3, the computation of external field term may be conducted by the memory elements that are arranged at a diagonal of the memory array, and the memory cells thereof may perform a logic AND operation. The step S1 may be achieved by tuning threshold voltages or resistances of the two memory cells of each of the memory elements.

(38) In step S2, the state signals are set up in the memory array. For example, a m.sup.th configuration of the state signals may be set up into the memory array, wherein m is a positive integer. The state signals may correspond to spins of the sites selected from +1 and ?1. The step S2 comprises: conducting a complementary read operation for individually selecting one of the two memory cells of each of the memory elements for receiving two corresponding state signals; and inputting the state signals into the selected memory cells of the memory elements, wherein the selected memory cells generates a plurality of output currents. According to some embodiments, the complementary read operation may comprise flipping a corresponding state signal, as shown in FIG. 11, if a trigger condition is met. Generally, the flipping will not affect the calculation result of a memory element. However, if one of the memory cells in the memory element is damaged, the flipping is beneficial for preventing a wrong coupling result. The trigger condition may be represented by formula (5).
R?[0,1]>U(5)
In formula (5), R is a given random value, and U is a threshold value. In some embodiments, U may be 0.5.

(39) In step S3, the energy value corresponding to the state signals is calculated based on a sum value of the output currents. More specifically, the energy value corresponding to the m.sup.th configuration of the state signals may be calculated. When the sum value of the output current is the output current of a string, such as the output current L.sub.1, L.sub.2, L.sub.3, or L.sub.4 as shown in FIG. 3, the energy value corresponds to a local minimum energy. When the sum value of the output current is the output current of the whole memory array, i.e., the total of output currents of all strings, the energy value corresponds to a global minimum energy.

(40) In step S4, the state signals are updated according a transition probability of the energy value. More specifically, if the transition probability is larger than a predefined value, a new (m+1).sup.th configuration of the state signals will replace the original m.sup.th configuration of the state signals. In some embodiments, the transition probability P may be represented by formula (6).

(41) $\begin{array}{cc}P=\mathrm{Sigmoid}\left(\frac{2\left(-\mathrm{Li}-\mathrm{qi}\right)}{T}\right)& \left(6\right)\end{array}$
In formula (6), L.sub.i is local spin energy, and q.sub.i and T are hyper-parameters.

(42) The steps S2-S4 may be repeated until a predetermined finish condition is met. After end of repetition, step S5 may be conducted. In step S5, the state signals may be observed. In other words, the final configuration of the state signals, which corresponds to the optimal solution, may be observed.

(43) The computing method according to the disclosure may applying quantum annealing algorithm employing Ising model. In particular, the computing method according to the disclosure may applying quantum annealing algorithm employing Ising model without an external field term. For example, the computing method according to the disclosure may be applied in a combinatorial clustering problem of machine learning as shown in FIG. 13 represented by formula (7).
H=?.sub.i,j=1.sup.Nd(x.sub.i,x.sub.j)s.sub.is.sub.j(7)
In formula (7), d is the distance. When d is large, state signals s.sub.i and s.sub.j tend to adopt opposite spins. When d is small, state signals s.sub.i and s.sub.j tend to adopt the same spin.

(44) The computing method according to the disclosure allows for higher tolerance on the variation of threshold voltage in cases that the threshold voltage is tuned for setting the coefficients, such as the cases using the memory elements as shown in FIGS. 4-5. The threshold voltage typically has a distribution pattern with a standard deviation. Referring to FIG. 14, compared to a comparative example CE without the complementary read operation, an example E using the complementary read operation of the disclosure can increase the acceptable variation of threshold voltage by up to 60%. Similarly, the computing method according to the disclosure allows for higher tolerance on the variation of resistance in cases that the resistance is tuned for setting the coefficients, such as the cases using the memory elements as shown in FIGS. 6-9.

(45) Based on the above, the disclosure provides a memory device and a computing method using the same as improved implementations for algorithms.

(46) It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.