Quantum processing circuitry cooling systems and methods

Abstract

Quantum processing circuitry cooling systems are provided. The systems can include: a first chamber maintained at a first pressure; a second chamber maintained at a second pressure, wherein the first and second pressures are independent from one another; a cooler within the first chamber and operable to act as a cooling source for the cooling system; and quantum processing circuitry within the second chamber, the quantum processing circuitry being thermally coupled to the cooler. Cooling systems are also provided that can include: a cooler configured to generate and/or store cryofluid; a device thermally coupled to the cooler; and a plurality of thermal couplings between the cooler and the device, at least one of the thermal couplings being a first conduit system configured to convey cryofluid between the cooler and the device, wherein the first conduit system includes a first heat exchanger within the cooler and is configured to receive the cryofluid from the device, cool the cryofluid using the heat exchanger and provide cooler cryofluid to the device. Methods for cooling quantum processing circuitry are also provided. The methods can include providing cooling to quantum processing circuitry from a cooling source in a chamber having an independent pressure from the pressure about the quantum processing circuitry.

Claims

1. A quantum processing circuitry cooling system, the system comprising: a first chamber maintained at a first pressure; a second chamber maintained at a second pressure, wherein the first and second pressures are independent from one another; a cooler within the first chamber and operable to act as a cooling source for the cooling system; and quantum processing circuitry within the second chamber, the processing circuitry being thermally coupled to the cooler; and an input/output operably coupled to the quantum processing circuitry and being separately thermally coupled to the cooler.

2. The quantum processing circuitry cooling system of claim 1 further comprising cryo electronics operably coupled to the quantum processing circuitry and being separately thermally coupled to the cooler.

3. The quantum processing circuitry cooling system of claim 1 wherein the thermal coupling between the cooler and quantum processing circuitry comprises a cryofluid.

4. The quantum processing circuitry cooling system of claim 3 further comprising a heat exchanger within the second chamber and configured to receive the cryofluid.

5. The quantum processing circuitry cooling system of claim 4 wherein the heat exchanger is thermally linked to the quantum processing circuitry.

6. The quantum processing circuitry cooling system of claim 5 further comprising a gas handling system operably engaged between the heat exchanger and the cooler.

7. The quantum processing circuitry cooling system of claim 6 wherein the gas handling system can include one or more of a pump, compressor, and/or a tank.

8. The quantum processing circuitry cooling system of claim 1 wherein the cooler is configured to provide cryofluid, and further comprising at least one solid conduction thermal link and at least one cryofluid conduit, wherein both the link and conduit extend to the second chamber.

9. The quantum processing circuitry cooling system of claim 1 wherein the cooler is configured to provide at least two forms of cryofluid to the second chamber.

10. A method for cooling quantum processing circuitry, the method comprising providing cooling to quantum processing circuitry from a cooling source in a chamber having an independent pressure from the pressure about the quantum processing circuitry; and providing cooling to one or both input/output and/or cryo electronics.

11. The method of claim 10 further comprising providing the cooling with one or both of cryofluid and/or conductive links.

12. The method of claim 10 further comprising providing at least two types of cryofluid to cool the quantum processing circuitry.

13. The method of claim 10 further comprising providing the cooling with one or both of cryofluid and/or conductive links, wherein at least one of the links provides warmer temperatures than the cryofluid.

14. The method of claim 13 further comprising generating one liquid cryofluid in the cooler.

15. The method of claim 14 further comprising cooling another liquid cryofluid in the cooler.

Description

DRAWINGS

(1) Embodiments of the disclosure are described below with reference to the following accompanying drawings.

(2) FIG. 1A is a depiction of quantum processing circuity.

(3) FIG. 1B is a box diagram of a current quantum processing circuitry system.

(4) FIG. 2 is a box diagram of a processing circuitry cooling system according to an embodiment of the disclosure.

(5) FIG. 3 is a box diagram of another processing circuitry cooling system according to another embodiment of the disclosure.

(6) FIG. 4A is a box diagram of another processing circuitry cooling system according to another embodiment of the disclosure.

(7) FIG. 4B is a box diagram of another processing circuitry cooling system according to another embodiment of the disclosure.

(8) FIG. 5 is a box diagram of a gas handling system according to an embodiment of the disclosure.

(9) FIG. 6 is a box diagram of another processing circuitry cooling system according to another embodiment of the disclosure.

(10) FIG. 7 is a box diagram of another processing circuitry cooling system according to another embodiment of the disclosure.

(11) FIG. 8 is a box diagram of another processing circuitry cooling system according to another embodiment of the disclosure.

(12) FIG. 9 is a box diagram of another processing circuitry cooling system according to another embodiment of the disclosure.

DESCRIPTION

(13) This disclosure is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws to promote the progress of science and useful arts (Article 1, Section 8).

(14) The present disclosure will be described with reference to FIGS. 1A-9.

(15) Physically locating the cooler components described above within the quantum computer is a challenge. More so, with current cryogenic architectures, all these components must be physically located as close to the cryocooler as necessary to maximize cooling power. FIG. 1A shows how densely these components are arranged around the cryocooler located in center of the quantum computer.

(16) FIG. 1B is a simplified block diagram of a current quantum computing architecture showing example of quantum processing circuitry (cryogenic electronics or cryoE, I/O, and chip) are located as close to the cooler as possible.

(17) The cooler can represent a mechanical cryocooler; a closed-cycle mechanical refrigerator that provides lower operating costs compared to open-cycle cryogenic systems that must be continuously replenished with expensive cryogenic fluids. Mechanical cryocoolers, including Gifford-McMahon and/or Pulse Tube, provide a discrete number of cooling stages. Typically, there are two stages: the 1.sup.st stage provides increased cooling power at an intermediate temperature (30K) and the 2.sup.nd stage provides the lowest temperature (4K), albeit with decreased cooling power. Each stage can include a mounting flange, to which components that need to be cryogenically cooled can be mounted. Heat can be removed from components of interest via solid conduction. Because the cooling power available to cool a component of interest is inversely related to the distance from the cryocooler, current cryogenic system architectures typically build around the cryocooler. Specifically, as shown, the cryocooler is placed in the center of the system and components to be cooled are positioned as close to the cryocooler as possible.

(18) For example, as show in FIG. 1B, components of quantum processing circuitry, such as the quantum chip, cryogenic electronics (CryoE), and I/O that connect the chip and electronics to room temperature control and measurement systems are 1) physically located as close as possible to the cooler and 2) at temperatures only provided at discrete cooling stages provided by the cooler. Such architectures, where all components must fit within a single vacuum chamber, are limited by available surface area and cooling power which presents a significant challenge to scaling up to millions of qubits necessary for quantum computers to be truly useful.

(19) Referring to FIG. 2, a block diagram of a quantum processing circuitry cooling system according to an embodiment of the disclosure is shown. System 10 can include a first chamber 2 maintained at a first pressure 6. Chamber 2 can house a cooler 8 that is operational to provide cooling and/or act as a cooling source. Cooler 8 can be configured as a condenser for condensing cryo fluid and/or a cooling source for providing conductive cooling. Electronics and/or gas handling components 14 can be operatively coupled to cooler 8.

(20) A second chamber 4 can be maintained at a second pressure 7. As shown the first and second pressures can be independent of one another. Quantum processing circuitry 12 is provided within the second chamber 4 and operatively coupled for cooling via a link 5 to cooler 8. Link 5 can be a single or multiple links. Link 5 can provide cooling power via conduction and/or cryofluid. Link 5 can provide cooling power to within chamber 4 and/or other portions or components of quantum processing circuitry 12 including, but not limited to input/output, cryo-processing circuitry (cryo electronics). Additionally, the systems of the present disclosure can include their own processing circuitry 16 configured to control associated pumps, valves, temperature sensors of the system, and/or control devices.

(21) FIG. 3 is a block diagram of another embodiment of the quantum processing circuitry cooling system. In this embodiment, the constraints of physical distance from the cryocooler are removed, enabling the individual quantum processing circuitry components (I/O, chip, and cryo electronics) to be positioned at locations distant from the cooler and in different vacuum chambers. As shown, each component may be independently cooled with a dedicated thermal link to the cooler, with individual cooling power control devices that can operate at different temperatures, providing for an optimization of available cooling power.

(22) The thermal links can represent a conduit through which a quantum processing circuitry (I/O, chip, and/or cryo electronics) can be in thermal communication with a cooling source. The thermal links can be configured using components of high thermal conductivity, including copper or aluminum, where cooling power is provided via solid conduction. As an example, the cooling power control devices are provided by controlling the geometry (cross sectional area and/or length) of the thermal links to control available cooling power that will then dictate resulting temperature of each component.

(23) The thermal links may also represent cryogenic fluid conduits through which one or more cryogenic fluids can be delivered from a cryogenic fluid source, such as a cooler where a cryocooler is positioned within a bucket where cooled cryogenic fluid is collected and stored, to the component of interest. In this case, the cooling power control device can be used to vary the flow of cryogenic fluid to the component and thereby control the resultant temperature of the quantum computing component. In one embodiment, the cooling power control device can be a mechanical valve that can be controlled to open/close or proportionally opened to vary the flow of cryogenic fluid through the conduits. In another embodiment, the cooling power control device can be achieved by varying the pressure of the cooler (see for example, US Patent Application Publication No. US 2021/0005366 to Doherty et al., the entirety of which is incorporated by reference herein). In another embodiment, the cooling power control device can be achieved by varying the cross-sectional area and length of the cryogenic fluid to control the pressure drop and thereby flow of cryogenic fluid through the conduit. In another embodiment, the cooling power control device can be comprised of a fluid conduit with a heater element that can be controlled to induce a vapor lock within the cryogenic fluid conduit to control flow (see for example, U.S. Pat. No. 11,047,779 to Doherty et al., the entirety of which is incorporated by reference herein).

(24) FIG. 4A depicts a block diagram of another system of the present disclosure that details components used when a fluid conduit is used as the thermal link. The cooler represents a source of cryogenic fluid in one vacuum housing. The system includes a heat exchanger and quantum processing circuitry in another vacuum housing. Cryogenic fluid flows from the cooler to the heat exchanger through a gas handling system, and back to the cooler. The heat exchanger and quantum processing circuitry are in thermal communication through a thermal link such that the temperature of the quantum processing circuitry can be the temperature of the cryogenic fluid upon entry into the heat exchanger. The thermal link can be solid conduction and/or a fluid conduit.

(25) FIG. 4B depicts a block diagram of another system scaled to cool multiple quantum processing circuitry configurations. Accordingly, where >10 W of cooling power at 4K, for example, is required to cryogenically cool quantum processing circuitry with thousands or even millions of qubits, embodiments of the present systems and/or methods can provide multiple (e.g., three) cryocoolers used to create and store liquid helium. This liquid helium can be delivered through cryogenic fluid conduits to three quantum processing circuitry configurations, shown here in a parallel orientation. Heat exchangers can be provided within each vacuum chamber housing the quantum processing circuitry with a thermal mounting flange to mount the quantum processing circuitry (electronics, processing chips, and/or I/O). As shown, each quantum processing circuitry configuration can have independent vacuum housing, however, they could be combined in a single vacuum housing in other embodiments. A gas handling system is provided to control the flow of liquid helium out of each quantum computer and circulate it back to the cooler. As shown, the gas handling system includes many pumps required to control the pressure and flow rate of the liquid helium through each chamber. The cooler and gas handling systems can be independent modules located far from the quantum processing circuitry in an effort to minimize coupling of vibrations or electrical noise into the quantum computer environment. FIG. 4B shows a central processing circuitry used to control the cooler, quantum processing circuitry, and/or gas handling systems. This processing circuitry could include a user interface, computer, and access to data storage necessary to monitor and control the system.

(26) FIG. 5 shows a gas-handling system (GHS), which can be configured to operate as part of a cooling system of the present disclosure and control the flow of cryogenic fluid into and out of the chamber housing the quantum computer component. Typical fluids include those that liquefy at cryogenic temperatures, for example helium and nitrogen. The gas handling system can contain a vacuum pump, such as a scroll or roots blower pump, to reduce the vapor pressure and thereby reduce the temperature of the cryogenic fluid via evaporative liquid. It may also include a compressor that compresses gas from the vacuum pump exhaust to some increased pressure (typically >1 atm). A tank or buffer volume can be provided to be included in the GHS that is sufficiently large to store all the gas required by the system to reach and maintain cryogenic temperatures. Also included in the GHS are control components, including for example pressure transducers, mass flow meters, variable flow valves, and control HW & SW to control the flow into and out of the GHS; each of which can be controlled by processing circuitry 16 of the system.

(27) The systems can include thermal links that can provide thermal communication between a cooler and quantum computer component. FIG. 6 depicts a cooler system comprising a cryocooler oriented in a bucket that is surrounded by a vacuum housing. Warm cryogenic fluid from the gas handling system is fed into the bucket. The cryocooler cools the fluid and ultimately condenses the gas into a liquid that is stored at the bottom of the bucket. Cryogenic fluid can be provided from this source and delivered to quantum processing circuitry through a cryogenic fluid conduit to cool the quantum processing circuitry via a cryogenic fluid thermal link. The bucket can include flanges that are in thermal communication with the 1.sup.st and 2.sup.nd stage of the cryocooler via thermal links. The flanges provide locations for mounting solid conduction thermal links to the quantum processing circuitry to be in thermal communication with the cooler via solid conduction thermal links (see for example, US Patent Application Publication No. US 2020/0109764 to Motley et al, the entirety of which is incorporated by reference herein).

(28) FIG. 6 also shows a pressure barrier which separates the vacuum housing of the quantum processing circuitry from the vacuum housing of the cooler. The pressure barrier represents a physical barrier separating two spaces that enables thermal communication between components located in each space (see for example, US Patent Application Publication No. US 2019/0170620 to Reijnders et al., the entirety of which is incorporated by reference herein). Thermal communication across the pressure barrier can comprise a cryogenic fluid thermal link and/or a solid conduction thermal link.

(29) FIG. 7 shows a specific example of the proposed cryogenic system architecture for cooling a dilution unit in quantum processing circuitry that can be a superconducting qubit based quantum computer systems. A dilution unit is a device that utilizes dilution of two isotopes of helium (3He and 4He) to reach temperatures <10 mK. As shown in FIG. 7, the proposed architecture utilizes two separate cryogenic fluid loops. The first contains only 4He. The second contains a 3He/4He mixture. The Gas Handling system contains components for controlling the pressure and flow rate of each cryogenic fluid loop. A cooler is used to cool each cryogenic fluid loop, creating a source of 4K 4He and a separate source of 4K 3He/4He mixture.

(30) Referring next to FIG. 8 a block diagram cooling system 80 can include a cooler configured to condense a cryofluid in a bucket 82. The entirety of the cooler can be a separate vacuum housing. As described, this cooler can have flanges 84 and 86. Each of these flanges can be operably coupled for cooling to heat exchanger 89 which is in operable fluid communication with spent cryofluid (higher temperature cryofluid). Accordingly, each of the flanges can be used to provide a specific temperature to the heat exchanger and bring cryofluid passing that coupled portion to a predetermined temperature. Accordingly, using valves, cryofluid may be taken from the heat exchanger proximate the coupled portion to provide cryofluid of that specific temperature. For example, cryofluid removed at 92 will have the temperature of the flange 84 via link 91; cryofluid removed at 94 will have the temperature of flange 86 via link 93; and cryofluid removed at 96 will have the temperature of liquid cryofluid 88.

(31) Accordingly, the systems can include a plurality of thermal couplings between cooler 80 and a device to be cooled, which may or may not include quantum processing circuitry with at least one of the thermal couplings being a first conduit system configured to convey cryofluid between the cooler and the device. The first conduit system can include a first heat exchanger within the cooler and configured to receive the cryofluid from the device, cool the cryofluid using the heat exchanger, and provide cooler cryofluid to the device.

(32) FIG. 9 shows another example cooler configuration. Here, a cryocooler can be placed around a bucket whereby the bucket is sealed as to contain an input gas. 300K 4He is fed into the bucket space, provided from a 4He gas handling system. The cryocooler condenses the 4He which collects in the bottom of the bucket at 4K. The bucket also contains a sealed 3He/4He conduit, for example a copper tube, that has an input and output end at the top and bottom of the bucket respectively. The 3He/4He conduit is sealed from the 4He in the bucket such that the 3He/4He mixture does not mix with the 4He fluid inside the bucket. 300K 3He/4He gas is fed into the 3He/4He conduit, from the 3He/4He gas handling system. Because the 3He/4He conduit is in the bucket, surrounded by cooling 4He gas, the 3He/4He mixture inside the 3He/4He conduit cools and condenses. In other embodiments, the 3He/4He conduit can be wrapped around the cryocooler within the bucket or thermally lagged to the cryocooler as to increase cooling power to the 3He/4He conduit.

(33) In FIG. 9 the 4He Gas handling can contain a vacuum pump, which reduces the vapor pressure in the 4K 4He loop, resulting in evaporative cooling and a drop in temperature to 1.5K. The 1.5K He4 cryogenic fluid is used to cool the 4K 3He/4He cryogenic fluid to 1.5K via a heat exchanger. The 1.5K 4He loop leaves the heat exchanger and ultimately goes through the 4He gas handling system, potentially passing through other heat exchangers to cool other components. Also leaving the heat exchanger, is the 1.5K 3He/4He cryogenic fluid that is fed as input to the dilution unit. In the dilution unit, the 3He/4He mixture goes through a still, multiple heat exchangers, and a mixing chamber. Temperature flanges are provided on the dilution unit to serve as locations for thermally lagging components. Typically, a 1K, 100 mK, and 10 mK flange are provided. The qubit processor or chip (quantum processing circuitry) can be mounted on the dilution unit mixing chamber, where the lowest temperature (<10 mK) is achieved. The 3He/4He fluid leaves the dilution unit and goes to the 3He/4He gas handling system. Each gas handling system (4He and 3He/4He recirculates the cryogenic fluids back to the cooler for closed-loop operation.

(34) In other embodiments, a heat exchanger can be used to control the temperature of any quantum processing circuitry. For example, the quantum chip may be in thermal communication while an electronic amplifier is in thermal communication with another. The temperature of each heat exchanger can be precisely controlled by regulating the flow of cryogenic fluid to each heat exchanger. This enables an optimization of available cooling power and the ability to operate components at whatever temperature is required.

(35) In other embodiments, additional cryogenic fluid loops can exist. In other embodiments, other heat exchangers may exist. One cryogenic fluid path can be fed per heat exchanger and/or multiple heat exchangers can be installed on a single cryogenic fluid path.

(36) In other embodiments, multiple vacuum housings may exist. Quantum processing circuitry configurations can exist in one vacuum space and/or be located in other vacuum spaces separated by pressure barriers. In other embodiments, the cooler may contain one or many cryocoolers.

(37) In another embodiment, multiple coolers can be utilized as cooling sources. For example, a cooler can be used to create a source of 4He and another cooler can be used to supply a source of 3He/4He. Each cooler can provide cooling to one or more quantum processing circuitry configurations in one or more vacuum housings.

(38) In accordance with the systems provided herein, methods for cooling processing circuitry are provided that can include providing cooling to processing circuitry from a cooling source in a chamber having an independent pressure from the pressure about the processing circuitry.

(39) The cooling can be provided with one or both of cryofluid and/or conductive links, and/or to one or both input/output and/or cryo electronics. The cooling can be provided with at least two types of cryofluid to cool the processing circuitry, for example.

(40) In compliance with the statute, embodiments of the invention have been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the entire invention is not limited to the specific features and/or embodiments shown and/or described, since the disclosed embodiments comprise forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.