Abstract
A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic. A SRL latch is formed of three NMOS and PMOS structures having a first latch with a first NMOS structure adjacent a first PMOS structure, a second latch with a second NMOS structure adjacent a second PMOS structure wherein the first and second NMOS structures are adjacent one another, and a third latch with a third NMOS structure adjacent a third PMOS structure wherein the second and third PMOS structures are adjacent one another, wherein the latch is adapted to have alternating logic with a state assignment of 010 and 101. A Single Event Upset Triple Modular Redundancy (TMR) tolerant circuit generates complementary output values 010 and 101 with layouts that are adjacent.
Claims
1. A Single Event Upset Triple Modular Redundancy (TMR) tolerant circuit logic structure formed of three NMOS and PMOS structures having a first circuit with a first NMOS structure adjacent a first PMOS structure to form a first logic section which includes a first 3-input voter circuit and a first flip-flop circuit, a second circuit with a second NMOS structure adjacent a second PMOS structure to form a second logic section which includes a second 3-input voter circuit and a second flip-flop circuit wherein the first and second NMOS structures are adjacent to one another, and a third circuit with a third NMOS structure adjacent to a third PMOS structure to form a third logic section which includes a third 3-input voter circuit and a third flip-flop circuit wherein the second and third PMOS structures are adjacent one another, wherein the Single Event Upset TMR tolerant circuit logic structure is adapted to have alternating logic outputs 010 and 101 with voter circuits in each logic circuit voting on 010 and 101 as correct values to correct errors, further wherein outputs of the first and third logic sections are the same and the output of the second logic is the logical complement of the outputs of the first and third logic sections.
2. The Single Event Upset TMR tolerant circuit logic structure according to claim 1 wherein adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in a combinational logic of the 3-input voter circuit.
3. The Single Event Upset TMR tolerant circuit logic structure according to claim 1 wherein adjacent NMOS regions or adjacent PMOS regions contain gates that generate and propagate logic inversions in a combinational logic of the 3-input voter circuit where all gates are SEU hard by design.
4. The Single Event Upset TMR tolerant circuit logic structure according to claim 1 selectively realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic to realize combinational logic of the 3-input voter circuit.
5. The Single Event Upset TMR tolerant circuit logic structure according to claim 1 wherein the latch provides SEU tolerance.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1 shows a SERT Latch Circuit of the prior art.
(2) FIG. 2 shows a State Table for the SERT circuit of FIG. 1.
(3) FIG. 3 shows a schematic representing Triple Modular Redundancy of the prior art.
(4) FIG. 4 shows a schematic representing SRL Design of the prior art.
(5) FIG. 5 shows a first representative SRL Latch Circuit of the prior art.
(6) FIG. 6 shows a State Table for the SRL Latch Circuit of FIG. 5.
(7) FIG. 7 shows a State Table for the SRL Latch Circuit of FIG. 8.
(8) FIG. 8 shows a second representative SRL Latch Circuit Design of the prior art.
(9) FIG. 9 shows a schematic illustrating Combinational Logic with more detail for the circuit of FIG. 4.
(10) FIG. 10 shows Typical CMOS Structure.
(11) FIG. 11 shows a schematic of a graphical non layout view of SRL Latch Logic.
(12) FIG. 12 shows a schematic graphical layout structure of SRL Latch Logic.
(13) FIG. 13 show a schematic graphical layout structure of SRL Latch Logic of FIG. 12 with added separation to protect against SEU affecting two state variables.
(14) FIG. 14 shows a schematic with combinational logic with SRL layout together.
(15) FIG. 15 shows a simple 3-variable Karnaugh Map for function F.
(16) FIG. 16 shows a K-Map for a minimal sum-of-products solution for the K-Map of FIG. 15.
(17) FIG. 17 shows a K-Map which is the complement of FIG. 15.
(18) FIG. 18 shows a K-Map and Complex CMOS Gate design equation for function F.
(19) FIG. 19 shows a K-Map and Complex CMOS design equation for function F′
(20) FIG. 20 shows a partial circuit diagram for a Complex CMOS depiction for the realization of F and F′ respectively.
(21) FIG. 21 shows a circuit schematic of a multiplexor solution to realize function F.
(22) FIG. 22 shows a schematic representation of adjacent regions of NMOS transistors that implement F and G.
DESCRIPTION OF THE EMBODIMENTS
(23) CMOS standard cell layout typically consists of an area composed of NMOS transistors and another area composed of PMOS devices. The NMOS devices are coupled to VSS such that the NMOS transistors generate logic 0 values throughout the circuit, and PMOS devices are coupled to VDD such that the PMOS transistors generate logic 1 values. The boundary between the NMOS and PMOS devices has guard bar coupling the N well substrate to VSS and the P well substrate to VDD. FIG. 10 depicts the typical CMOS circuit structure. A PMOS device area 100 is formed adjacent an NMOS device area 102. A VDD bus 104 is formed adjacent the PMOS circuit 100. A VSS bus 106 is formed adjacent the NMOS circuit 102. Preferably, the VDD and VSS busses are formed of metal. The VDD and VSS busses also act as guard bar in the region between the PMOS circuit 100 and the NMOS circuit and depict the well/substrate tie downs and can be tied hard to VDD/VSS with continuous metal busses or more softly with intermittent contacts to VDD/VSS.
(24) The SRL latch of FIG. 11 comprises three state variables y1, y2, y3. FIG. 11 depicts a graphical but not realistic layout view of the SRL latch. Each of the three state variable includes a PMOS region 1102, 1104 and 1106 and also an NMOS region 1108, 1110 and 1112. A VDD bus 1114 is adjacent the PMOS region 1102 away from the NMOS region 1108. A VDD bus 1116 is adjacent the PMOS region 1104 away from the NMOS region 1110. A VDD bus 1118 is adjacent the PMOS region 1106 away from the NMOS region 1112. A VSS bus 1120 is adjacent the NMOS region 1108 away from the PMOS region 1102. A VSS bus 1122 is adjacent the NMOS region 1110 away from the PMOS region 1104. A VSS bus 1124 is adjacent the NMOS region 1112 away from the PMOS region 1106. A guard bar is formed of a VDD bus 1126 adjacent the PMOS region 1102, and a VSS bus 1128 adjacent and between the VDD bus 1126 and the NMOS region 1108. A guard bar is formed of a VDD bus 1130 adjacent the PMOS region 1104, and a VSS bus 1132 adjacent and between the VDD bus 1139 and the NMOS region 1110. A guard bar is formed of a VDD bus 1134 adjacent the PMOS region 1106, and a VSS bus 1136 adjacent and between the VDD bus 1134 and the NMOS region 1112.
(25) FIG. 12 depicts a better layout view of the SRL latch where one can share VSS and VDD between adjacent state variables of the SRL latch. Note, the guard bar denoting the well substrate edges is not shown in succeeding Figures to avoid obscuring the invention in extra details. The drawing shows three NMOS regions 1202, 1204 and 1206 and three PMOS regions 1208, 1210 and 1212. A first VDD bus 1214 is adjacent the PMOS region 1208. A second VDD bus 1216 is adjacent the other two PMOS regions 1210 and 1212. A first VSS bus 1218 is adjacent the NMOS region 1206. A second VSS bus 1220 is adjacent the other two NMOS regions 1202 and 1204.
(26) However, there is a potential problem with this layout to realize an SRL latch. If the stable states (y1 y2 y3) in U.S. Pat. No. 8,081,010 for the SRL latch are 000 and 111, then in FIG. 12 the NMOS devices of Y1 and Y2 are adjacent and the PMOS devices of Y2 and Y3 are adjacent. As noted in the Background discussion, a single particle strike SEU can affect NMOS devices to produce a false 0, but not a false 1; likewise, an SEU can affect PMOS devices to produce a false 1, but not a false 0. Therefore, if the latch is in state 111, a single SEU can affect Y1 and Y2 to both produce false 0's forcing the circuit into state 001; internal feedback will force the circuit to state 000 and the latch has upset. Likewise, if the circuit is in state 000, a single SEU through the PMOS regions of Y2 and Y3 can force the circuit to state 011; internal feedback will force the circuit to state 111 producing an upset.
(27) In previous designs based on U.S. Pat. No. 8,081,010, to remedy this problem, it is better to introduce a separation between adjacent NMOS devices in Y1 and Y2 and between adjacent PMOS devices in Y2 and Y3 as shown in FIG. 13. The extra area includes the addition of one VSS and one VDD bus plus the separation distance. The element numbering of the common elements is the same in FIG. 13 as for FIG. 12. Note that the second VSS bus 1216 is split into two VDD buses 1216′ and 1216″. Likewise the second VSS bus 1220 is split into two VSS buses 1220′ and 1220″. A first gap 1222 is formed between the split second VSS buses 1216′ and 1216″. A second gap 1224 is formed between the split second VDD buses 1220′ and 1220″. The distance of the separation is a function of the doping profiles of a specific process. Higher doping concentrations will cause the electron hole pairs generated by the upsetting particle to be recombined more quickly (ie. reduce the lifetime of the generated charge).
(28) If one uses the state assignment with states (y1 y2 y3) as 010 and 101, the layout requirements change dramatically. The layout of FIG. 12 can be used. This layout is SEU fault tolerant. Consider the layout depicted in FIG. 12 and the circuit is in state 010. In state 010, Y1 produces a 0 and Y2 produces a 1. If an SEU affects the adjacent NMOS circuits of Y1 and Y2 then only false 0′s can result; however, Y1 is already 0 and therefore unaffected by the SEU. Only Y2 could be affected and forced to a 0 in which case the circuit temporarily assumes state 000. When the SEU dissipates, the circuit is forced back to 010 and the SEU is tolerated. If the circuit is in state 101 and the same SEU strike situation occurs, the circuit will temporarily assume state 001 where Y1 is affected but Y2 is not; again, after the SEU dissipates, the circuit will return to state 101 and the SEU is tolerated.
(29) Consider the case where an SEU affects the adjacent PMOS areas of Y2 and Y3 in FIG. 12 and the circuit is in state 010. Only false 1's can occur in a PMOS region and only Y3 is forced to a wrong value 1; Y2 remains 1 and the circuit assumes state 011. Y2 is unaffected since PMOS devices only fail to produce a false logic 1. After the SEU is dissipated, the circuit will return to 010 and the SEU is tolerated. If the circuit is in state 101, only Y2 can be affected and the circuit assumes state 111. After the SEU is dissipated, Y2 will return to 0 and the circuit assume state 101 and the SEU is tolerated.
(30) Normally combinational logic drives the SRL latch. The SRL latch has three inputs which are driven by the respective combinational logic, Sections A, B and C. FIG. 14 depicts a preferred embodiment in which the layout can be configured according to the teachings of FIG. 12. In particular, the combinational logic is formed of three NMOS regions 1402, 1404 and 1406 and three PMOS regions 1408, 1410 and 1412. A first VDD bus 1414 is adjacent the PMOS region 1408. A second VDD bus 1416 is adjacent the other two PMOS regions 1410 and 1412. A first VSS bus 1418 is adjacent the NMOS region 1406. A second VSS bus 1420 is adjacent the other two NMOS regions 1402 and 1404. The SRL Latch section is of three NMOS regions 1442, 1444 and 1446 and three PMOS regions 1448, 1450 and 1452. A first VDD bus 1454 is adjacent the PMOS region 1448. A second VDD bus 1456 is adjacent the other two PMOS regions 1450 and 1452. A first VSS bus 1458 is adjacent the NMOS region 1446. A second VSS bus 1460 is adjacent the other two NMOS regions 1442 and 1444. The two PMOS regions 1408 and 1448 can be formed of two separate wells but more preferably are formed in a single PMOS well. Similarly, the remaining regions shown horizontally adjacent in the drawing of FIG. 14 can be formed of two wells or a single well. Metal buses 1414 and 1454 can be one metal bus as can 1416 and 1456, 1420 and 1460, and also 1418, and 1458, respectively.
(31) Three independent (no shared logic) combinational logic circuits are used to drive each SRL state variable (SRL inputs). Section B will produce the logical complement signal of Sections A and C. State variable y2 is the logical complement of y1 and y3 (SRL Design 2 above) such that the driven states are 101 or 010. Since it is independent if an SEU strikes either CLi or Yi or both, all Sections (A, B and C) are SEU tolerant in the same manner the SRL latch described above is SEU tolerant.
(32) Combinational Logic Design Considerations
(33) Care must be given to the design of the combinational logic. A first reaction is to design two identical circuits except place an inverter at the output of one of the circuits to generate F and F′. Consider CL1 and CL2 which are supposed to generate complementary outputs with the NMOS regions adjacent as depicted in FIG. 14. Further assume that CL2 is identical to CL1 except there is an inverter at the output of CL2. Let CL1 CL2=1 0. Logic internal to CL1 and CL2 will have the same values which produce an output=1 with CL2 producing a 0 due to the output inverter. If an SEU strikes both NMOS circuits, a false 0 will be generated internal to both circuits yielding an output 01 instead of the correct 10 or the correctable 00, which will result in a failure.
(34) Let the two NMOS regions 200 and 202 in FIG. 22 depict NMOS transistor regions of adjacent regions that implement an uncomplemented function F and a complemented function G which is F′. Definition 1: A Transient 1 (0) Unidirectional Fault region exists when the electronics in the region can only produce a false 1 (0) value.
(35) A region consisting only of PMOS transistors would be a Transient 1 Unidirectional Fault and a region consisting of only NMOS transistors would be a Transient 0 Unidirectional Fault when the fault is an SEU.
(36) Adjacent NMOS regions of logic functions F and G tolerate Transient 1 or 0 Unidirectional faults if G=F′ and F and G contain no logic inversions or if logic inversions are present the electronics creating such inversions are SEU tolerant such that a false 1 cannot occur. Since Transient 1 or 0 Unidirectional Faults are SEUs, let the following discussion use SEU faults as these transient faults.
(37) Consider the situation where an SEU impacts both F and G in FIG. 22. If F and G have the same value 1 anywhere in the region which the SEU can impact, then both F and G can both be upset. This includes the situation where F=1 and G=0, but there is inverted logic within G which presents a 1 to internal circuits; upon an upset within G that forces a 1 to a 0 which gets inverted to transition G to a false 1. If F and G are realized with no inverters, including logic inversion in gates such as NAND and NOR, and further if F and G are complements, then a single SEU cannot upset both F and G. With alternating logic, FG will be 01 or 10; an SEU will force a state of 00 if the correct state FG=01. Likewise, if the correct state is 10, an SEU can cause an output of 00. Therefore, an SEU will force the output from 01 (10) to 00 but never 10 (01). For example, if F G=0 1, then only G can be upset to a 1, but F is unaffected; if FG=1 0, then only F is affected. The following SRL latch will correct the single fault and the SEU fault is tolerated.
(38) Finally, if logic inversions are present (for example in a NAND), and the circuitry that performs the inversion is SEU hard (i.e. a false 1 cannot occur), then the circuitry is SEU tolerant since there are no false 1's possible.
(39) It should be clear that the same applies for adjacent PMOS regions. Further since an SEU is a Transient 1 or 0 Unidirectional fault, applies to SEU fault tolerance. Further the structure shown in FIG. 14 is SEU tolerant when alternating logic is utilized and the NMOS or PMOS regions are adjacent as depicted in FIG. 14.
(40) There are at least five logic structures which will produce combinational logic that meet the conditions of the above and produce outputs without internal logic inversion. 1. AND-OR and OR-AND logic circuits which realize circuits with AND and OR gates, not NAND or NOR gates or any other logic form with inverters. 2. Pass Transistor Logic 3. Complex CMOS gates 4. Multiplexor gate logic 5. Logic gates that perform logic inversions are designed through proper electronics to be SEU hard, not allowing a false 1 to occur in NMOS circuits or a false 0 to occur in PMOS circuits.
(41) These five logic structures can be formed without logic inversion and hence meet the conditions above.
(42) Consider the simple Karnaugh map (K-Map) shown in FIG. 15.
(43) The typical way to realize function F to produce a minimal sum-of-products is to cover the prime implicants as shown in FIG. 16. F=y1′y3′+y1y2′ which can be realized with AND OR logic.
(44) F′ is realized in FIG. 17, which is the complement of F formed in FIG. 15. F′ can be realized as F′=y1y2+y1′y3 and F′ can be realized with AND OR logic the same as the circuit of FIG. 16 was produced.
(45) This result can also be obtained using Pass Transistor Logic, F=X′(Z′)+X(Y). If it is desired to pass only a 0 or a 1 instead of a variable, the Pass Transistor Logic equation becomes F=y1′y3′(1)+y1y2′(1)+y1′y3(0)+y1y2(0). The complemented function F′=y1′y3′(0)+y1y2′(0)+y1′y3(1)+y1y2(1).
(46) An alternate embodiment is to implement the combinational logic as a Complex CMOS gate. Following is such an implementation of the design of K-Map in FIG. 15. The Complex CMOS gate design equation for F is shown in FIG. 18. Similarly, the Complex CMOS gate design equation for F′ is shown in FIG. 19.
(47) The Complex CMOS electronic depiction is shown in FIG. 20. The number of transistors in FIG. 18 can be reduced.
(48) The connection diagram is not shown as it is understood that external variables (coming from a set of SRL latches) yi, i={1,2,3} are connected. The upper 8 transistors 2002, 2004, 2006, 2008, 2010, 2012, 2014 and 2016 are PMOS devices; the lower 8 transistors 2018, 2020, 2022, 2024, 2026, 2028, 2030 and 2032 are NMOS devices. The transistors 2002, 2004, 2006, 2008, 2018, 2020, 2022 and 2024 are coupled to form F according to the state of their respective inputs. The transistors 2010, 2012, 2014, 2016, 2026, 2028, 2030 and 2032 are coupled to form F′ according to the state of their respective inputs.
(49) The desired action for SEU tolerance for the Complex Gate in FIG. 20 is described next. Consider the case where F=1, and F′=0. F=1 means there is a path from VDD through PMOS devices to the output F; the NMOS paths of F are OFF. In a similar manner, there is a path through the NMOS devices in the F′ network passing a 0 to F′; the PMOS paths of F′ are OFF.
(50) Let these two designs be structured as depicted in FIG. 14 with the NMOS devices adjacent as Y1 and Y2; PMOS regions that are adjacent are for Y2 and Y3. The question to be addressed is whether a single SEU passing through the NMOS regions of both F and F′ create the possibility for F F′ to transition from producing correct 1 0 value to incorrect 0 1 value; that is both F F′ change state as a result of a single SEU.”
(51) Let F F′=1 0. The SEU passing through the NMOS region of F can induce a false 0 (NMOS devices produce false 0's, not false 1's.) However, since F′ is producing a correct 0, an SEU passing through the NMOS region of F′ cannot force a false 1 output. Therefore, an SEU passing through the NMOS regions of F and F′ will yield a 0 0 output, but not a 0 1 value. The same result occurs for the case where F F′=0 1; a single SEU would only change the F′ output from a 1 to 0, but not affect the output of F.
(52) If the PMOS regions were adjacent as depicted in FIG. 14 instead of the NMOS regions, the result would be similar except that instead of producing a false 0 value on F or F′, a false 1 value on either F or F′ would result, but not both.
(53) The structure depicted in FIG. 14 will function such that SEU's are tolerated in the manner described because only one of two adjacent “slices” would ever temporarily produce a false value. The SRL latch will correct one input in error.
(54) FIG. 20 also depicts the pass logic realization of this function with the same number of transistors and interconnect when 0's and 1's are passed. Therefore, pass logic circuits are SEU tolerant.
(55) The MUX solution for this circuit is shown in FIG. 21. The inputs 0 and 1 can be VSS and VDD inputs respectively.
(56) A similar multiplexor solution exists for F′; actually, the same circuit except all the 0 and 1 inputs are inverted. Each MUX can be implemented as NMOS transistors or PMOS transistors or a combination of both NMOS and PMOS transistors which would produce higher quality 0 and 1 voltage levels. Regardless, the NMOS or PMOS transistor regions can be abutted to produce the desired adjacent alternating logic circuits and be SEU tolerant.
(57) Finally addressing the last means (item 5) to produce SEU tolerant circuits, transistors can be made large enough to be immune to an SEU, therefore circuits constructed with proper sized transistors are SEU tolerant. Therefore, if a logic inversion is needed and the designer is willing to accept a larger circuit to create SEU tolerance in the logic inversion circuitry, then the presence of such a circuit is permitted.
(58) Definition 2: A Whitaker-Maki (WM) SEU tolerant structure consists of 1. Three combinational structures that possess a layout structure consisting of combinational logic and storage elements as depicted in FIG. 14; 2. Alternating logic is employed where the three structures pass states 010 and 101; 3. Combinational logic with adjacent NMOS (or PMOS) regions of logic functions F and G under two conditions: a. F=G′ and F and G contain no logic inversions in the combinational logic or b. The conditions of (a) are true except there are logic inversion gates all of which are SEU hard by design. 4. The storage cells (latches or flip-flops) are self restoring and correct single input failures. The preferred embodiment of a WM SEU tolerant structure implements the combinational logic with one of a Complex CMOS gate, pass transistor, or Multiplexor realization where there are no logic inversions; if a logic inversion is desired, then the circuitry that implements the logic inversion must be SEU hard. The self restoring cells should be SRL latches with the state assignment 010 and 101 with a layout structure depicted in FIG. 12.
(59) The combinational logic in FIG. 14 depicts the layout configuration to interface combinational logic and the SRL latch. This can be a viable approach in general but there is latitude in placing components of combinational logic as long as the conditions of the WM SEU tolerant structure are met. For example, logic components that compose Section A, B and C can be shifted around as long as adjacent NMOS regions (or PMOS regions) of CLi and CLj, where i and j are components of alternating logic meet condition 3. Therefore, there is flexibility for the designer in an actual layout.
(60) Applications Of Proposed Discovery
(61) Let CLi and Yi denote combinational logic and SRL cells in FIG. 14 respectively. Implementing a synthesis library using FIG. 14 can be accomplished by having combinational logic cells and SRL state variable cells configured as shown in FIG. 14. All cells would have the same height dimension with power, ground and well ties that match.
(62) Let Dmin represented the minimum distance sensitive nodes can be placed. An SEU strike at a distance greater than Dmin does not upset nodes. If one used a layout similar to FIG. 13, the distance between CLi cells and Yi cells would have to meet the Dmin constraint. In comparison, legacy Triple Modular Redundancy (TMR) must obey the Dmin layout constraint producing much less density than the SRL approach outlined herein.
(63) The WM structure concept can be generalized to realize any logic structure that does not include SRL latches. A pure combinational logic circuit meeting the conditions of Definition 2 (minus the latches) is SEU tolerant.
(64) Any logic circuit with combinational logic that meets the conditions of the WM structure with single input error correction and self restoring latches (flip flops) is SEU tolerant, even if a self restoring function is different than found in the use of an SRL latch. For example, a TMR circuit could be created that meet the conditions of a WM structure. In TMR, there are three sections of logic; let them be called S2, S2 and S3 and assume they meet the combinational logic conditions of the WM structure. To employ an alternating logic scheme, S1 S2 S3 must produce codes 010 and 101 as the fault free states. This means S2 must produce the logical complement of S1 and S3 without internal inversion. In TMR, the self-restoring and single input error correction aspect is achieved with voters; embedded voters would be required to “vote” using values 010 and 101 as correct states; further the layouts for the latches and voters must meet the WM conditions. The resulting TMR circuit would have excellent density characteristics compared to legacy TMR SEU tolerant circuits, but still would require more transistors than preferred WM approach with SRL latches described herein.
