Power signal transmission structure and design method thereof
10470299 ยท 2019-11-05
Assignee
Inventors
Cpc classification
H05K2201/093
ELECTRICITY
H05K2201/09427
ELECTRICITY
H05K2201/09409
ELECTRICITY
H05K2201/09709
ELECTRICITY
H05K1/0265
ELECTRICITY
H05K2201/0979
ELECTRICITY
H05K1/0263
ELECTRICITY
H05K2201/09609
ELECTRICITY
H05K1/116
ELECTRICITY
H05K2201/09309
ELECTRICITY
International classification
H05K1/09
ELECTRICITY
H01L23/48
ELECTRICITY
H05K3/12
ELECTRICITY
H05K1/16
ELECTRICITY
H01L23/498
ELECTRICITY
H05K1/11
ELECTRICITY
Abstract
A power signal transmission structure and a design method are provided. The power supply signal transmission structure is adapted for a circuit board having a first surface and a second surface opposite to the first surface, and the power signal transmission structure includes a first power electrode, a second power electrode, and a plurality of vias. The first power electrode is disposed on the first surface and has a plurality of power pad regions for receiving a power signal. The second power electrode is disposed on the second surface. The vias penetrate the circuit board to electrically connect the first power electrode and the second power electrode. The vias are arranged in accordance with the current direction of the power signal to balance the current received by the vias.
Claims
1. A power signal transmission structure, adapted for a circuit board having a first surface and a second surface opposite to the first surface, the power signal transmission structure comprising: a first power electrode, disposed on the first surface and having a plurality of power pad regions for receiving a power signal; a second power electrode, disposed on the second surface; and a plurality of vias, penetrating the circuit board to electrically connect the first power electrode and the second power electrode, the vias arranged based on a current direction of the power signal to balance the current received by the vias; and a plurality of first conductor isolation rings individually surrounding the vias closest to the respective power pad regions, and the plurality of first conductor isolation rings located between the respective vias surrounded by the plurality of first conductor isolation rings and the respective power pad regions, wherein the vias comprise a plurality of first vias and a plurality of second vias, the first vias are arranged in arcs with openings toward central points of the respective power pad regions, the first vias are disposed among the second vias with respect to a direction perpendicular to the current direction, and the second vias and the first vias form a W shape.
2. The power signal transmission structure as claimed in claim 1, further comprising: a plurality of third vias, penetrating the circuit board to electrically connect the first power electrode and the second power electrode, located within the arcs formed by the first vias, and aligned to the central points of the respective power pad regions; and a plurality of second conductor isolation rings, individually surrounding the third vias closest to the respective power pad regions and located between the respective third vias surrounded by the second conductor isolation rings and the respective power pad regions.
3. The power signal transmission structure as claimed in claim 2, wherein each of the first conductor isolation rings and each of the second conductor isolation rings are hollow patterns.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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DESCRIPTION OF THE EMBODIMENTS
(10) Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
(11)
(12) The first power electrode 110 is disposed on the first surface 11 of the circuit board 10 and electrically connected to a device 20 (e.g., a resistor in the faun of a surface mounted device (SMD), a resistor or inductor, or a pin of a power integrated circuit (IC)) in a power circuit to receive a power signal SPOW provided by the power circuit. The second power electrode 130 is disposed on the second surface 12 of the circuit board 10 to electrically connect the integrated circuit 30. The vias 120 penetrate the circuit board 10 to electrically connect the first power electrode 110 and the second power electrode 130.
(13)
(14) The vias VA are arranged based on a current direction Di of the power signal SPOW. In other words, from the view of the current direction Di of the power signal SPOW, the further the vias VA are away from the power pad regions 101, the less two adjacent vias VA are overlapped in the horizontal direction. Accordingly, the vias VA all receive a current of the power signal SPOW. In other words, an actual current path PTi passes through the respective vias VA to balance the current received by the vias VA. More specifically, the vias VA include a plurality of first vias VA1 and a plurality of second vias VA2. The first vias VA1 are arranged to form at least one arc with an opening toward central points CPA of the respective power pad regions 101. Furthermore, the first vias VA1 are arranged among the second vias VA2 with respect to a direction Dv perpendicular to the current direction Di, and the second vias VA2 and the first via VA1 form at least one W shape. The most distant vias VA in the W shape are aligned to the central points CPA of the respective power pad regions 101 while the closest vias VA of in the W shape are located by the outer sides of each of the power pad regions 101, perpendicular to the current direction Di.
(15) In the embodiment, straight line distances (i.e., shortest distances) between the vias VA and the respective power pad regions 101 are different. However, in other embodiments, the straight line distances between the vias VA and the respective power pad regions 101 may be set to be the same. In other words, the horizontal positions of the vias VA may be adjusted correspondingly. The positions may be determined based on the numbers of the vias VA and the area of the first power electrode 110. The embodiments of the invention do not intend to impose a limitation on this regard.
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(17) In the embodiment, the first conductor isolation rings CI1 are disposed on the vias VA in the first column on the right. However, in other embodiments, the first conductor isolation rings CI1 may be disposed on the vias VA in the first two columns on the right, depending on the actual current path PTi. In other words, when the current flowing into the vias VA is excessively high (i.e., higher than a current threshold), the first conductor isolation rings CI1 are disposed to surround the vias VA, so as to reduce the current flowing into the vias VA. In addition, the current threshold may be related to the maximum current value of the power signal SPOW and/or the number of the vias VA.
(18) Moreover, a surrounding ratio of the first conductor isolation rings CI1 to the vias VA may be proportional to the intensity of the current flowing into the vias VA. However, the first conductor isolation rings CI1 do not completely surround the vias VA. Alternatively, the intensity of the current flowing into the vias VA may be compared with the current threshold to determine the surrounding ratio of the first conductor isolation rings CI1 to the vias VA.
(19) Moreover, in the embodiments of the invention, the first conductor isolation rings CI1 may be hollow patterns, or the first conductor isolation rings CI1 may be high-resistance conductors or insulators, depending on the circuit design. The embodiments of the invention do not intend to impose a limitation on this regard.
(20)
(21) The third vias VA3 are located in the at least one arc formed by the first vias VA1, and are aligned to the central points CPA of the respective power pad regions 101 along the current direction Di. In other words, the horizontal positions of the third vias VA3 are the same as the central point CPA of the corresponding power pad region 101. The second conductor isolation rings CI2 individually surround the respective third vias VA3 closest to the respective power pad regions 101, i.e., surrounding the rightmost third vias VA3, and are located between the surrounded third vias VA3 and the respective power pad regions 101.
(22) In addition, a surrounding ratio of the second conductor isolation rings CI2 to the third vias VA3 may be proportional to the intensity of the current flowing into the third vias VA3. However, the second conductor isolation rings CI2 do not completely surround the third vias VA3. Alternatively, the intensity of the current flowing into the third vias VA3 may be compared with the current threshold (e.g., the embodiment shown in
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(24) In the embodiment, the vias VA4 are arranged in a plurality of arrays AR1 to AR4, and the power pad regions 101 are disposed between the arrays AR1 and AR4 along the current direction Di. In other words, the arrays AR1 and AR4 and the power pad regions 101 have different positions in the vertical direction. The first conductor isolation rings CI3 surround some of the vias VA4 based on the current direction Di of the power signal SPOW. In other words, the first conductor isolation rings CI3 individually surround the vias VA4 closest to the respective power pad regions (e.g., the first conductor isolation rings CI3 are disposed at the rightmost vias VA4). Moreover, the first conductor isolation rings CI3 are located between the respective vias VA4 that are surrounded and the respective power pad regions 101. Accordingly, the actual current path PTi may flow through the respective vias VA4 to balance the current received by the vias VA4.
(25) In the embodiments of the invention, a surrounding ratio of the first conductor isolation rings CI3 to the vias VA4 may be proportional to the intensity of the current flowing into the vias VA4. However, the first conductor isolation rings CI3 do not completely surround the vias VA4. Alternatively, the intensity of the current flowing into the vias VA4 may be compared with the current threshold (e.g., the embodiment shown in
(26) In the embodiments of the invention, the first conductor isolation rings CI3 may be hollow patterns, or the first conductor isolation rings CI3 may be high-resistance conductors or insulators, depending on the circuit design. The embodiments of the invention do not intend to impose a limitation on this regard.
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(28) The vias VA5 are arranged in a staggered array AST. The right side (corresponding to a first side) of the staggered array AST faces the power pad regions 101; the upper side and the lower side (corresponding to a second side and a third side) of the staggered array AST are more distant from the power pad regions 101; the left side of the staggered array AST is the most distant from the power pad regions 101. The first conductor isolation rings CI4 surround some of the vias VA5 based on the current direction Di of the power signal SPOW. In other words, the first conductor isolation rings CI4 surround the vias VA5 at the right side, the upper side, and the lower side of the staggered array AST. Accordingly, the actual current path PTi may flow through the respective vias VA5 to balance the current received by the vias VA5.
(29) In the embodiments of the invention, a surrounding ratio of the first conductor isolation rings CI4 to the vias VA5 may be proportional to the intensity of the current flowing into the vias VA5. However, the first conductor isolation rings CI4 do not completely surround the vias VA5. Alternatively, the intensity of the current flowing into the vias VA5 may be compared with the current threshold (e.g., the embodiment shown in
(30) In the embodiments of the invention, the first conductor isolation rings CI4 may be hollow patterns, or the first conductor isolation rings CI4 may be high-resistance conductors or insulators, depending on the circuit design. The embodiments of the invention do not intend to impose a limitation on this regard.
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(33) The order of Step S810, Step S820 and Step S830 is described above only for an illustrative purpose, and the embodiments of the invention shall not be limited thereto. Moreover, details of Step S810, Step S820 and Step S830 may be referred to the embodiments of
(34) In the embodiments described above, terms such as upper side, lower side, left side, right side, vertical, and horizontal are defined based on the orientations of the drawings and are only provided to facilitate the understanding of people having ordinary skill in the art to the drawings. Such terms shall not be construed as limitations of the embodiments of the invention. In other words, upper side, lower side, left side and right side are interchangeable without departing from the spirit of the invention, and vertical and horizontal are also interchangeable without departing from the spirit of the invention.
(35) In view of the foregoing, in the power signal transmission structure and the design method of the power signal transmission structure according to the embodiments of the invention, the vias and/or the conductor isolation rings are disposed according to the current direction of the power signal, so as to balance the current received by the respective vias. Thus the respective vias are able to receive the current, and the current sharing by multiple vias is thus facilitated.
(36) It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.