Non-switched capacitor circuits for delta-sigma ADCs

Abstract

Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

Claims

1. A differential integrator circuit operating in sampling and integration phases, comprising: a positive input voltage; a negative input voltage; an op amp having an inverting input, a non-inverting input, an inverting output, and a non-inverting output; a first sampling capacitor; a first integration capacitor; and a first non-switched capacitor, wherein: the first integration capacitor is coupled between the inverting input and the non-inverting output of the op amp, the first non-switched capacitor is coupled between the negative input voltage and the inverting input of the op amp, during the sampling phase, the positive input voltage is coupled to the first sampling capacitor, and during the integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

2. The differential integrator circuit in claim 1 further comprising: a second sampling capacitor; a second integration capacitor; and a second non-switched capacitor, wherein: the second integration capacitor is coupled between the non-inverting input and the inverting output of the op amp, the second non-switched capacitor is coupled between the positive input voltage and the non-inverting input of the op amp, during the sampling phase, the negative input voltage is coupled to the second sampling capacitor, and during the integration phase, a charge sampled across the second sampling capacitor is transferred to the second integration capacitor.

3. The differential integrator circuit in claim 2 further comprising: a discrete-time integrator circuit having first and second outputs, wherein the first output is in electrical communication with the positive input voltage and the second output is in electrical communication with the negative input voltage.

4. The differential integrator circuit in claim 3 wherein the discrete-time integrator circuit is a delayless integrator.

5. The differential integrator circuit in claim 3 further comprising: an analog-to-digital converter (ADC); and a digital-to-analog converter (DAC), wherein: the ADC is coupled to the inverting output and the non-inverting output of the op amp, and an output of the ADC is coupled to an input of the DAC.

6. The differential integrator circuit in claim 5 wherein the ADC is a flash ADC.

7. The differential integrator circuit in claim 5 wherein the DAC is a switched-capacitor type.

8. The differential integrator circuit in claim 5 wherein the DAC is coupled to an input of the discrete-time integrator circuit.

9. A delta-sigma analog-to-digital converter comprising: a first integrator circuit operating in sampling and integration phases, the first integrator circuit comprising: a positive integrator input voltage; a negative integrator input voltage; an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output; a first sampling capacitor; a first integration capacitor; and a first non-switched capacitor; an analog-to-digital converter having an ADC input coupled to the inverting output and the non-inverting output of the op amp; and a digital-to-analog converter having a DAC input coupled to an ADC output of the analog-to-digital converter, wherein: the first integration capacitor is coupled between the inverting input and the non-inverting output of the op amp, the first non-switched capacitor is coupled between the negative integrator input voltage and the inverting input of the op amp, during the sampling phase, the positive integrator input voltage is coupled to the first sampling capacitor, and during the integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

10. The delta-sigma analog-to-digital converter of claim 9 further comprising: a second integrator circuit having a first output and a second output, wherein the first output is in electrical communication with the positive integrator input voltage and the second output is in electrical communication with the negative integrator input voltage.

11. The delta-sigma analog-to-digital converter of claim 10 wherein the second integrator is a discrete-time integrator.

12. The delta-sigma analog-to-digital converter of claim 10 wherein the second integrator is a continuous-time integrator.

13. The delta-sigma analog-to-digital converter of claim 9 further comprising: a discrete-time integrator circuit having a first output and a second output; and a continuous-time integrator, wherein: the first output of the discrete-time integrator circuit is in electrical communication with the positive integrator input voltage and the second output of the discrete-time integrator circuit is in electrical communication with the negative integrator input voltage, a positive output of the continuous-time integrator is in electrical communication with a positive input of the discrete-time integrator circuit, and a negative output of the continuous-time integrator is in electrical communication with a negative input of the discrete-time integrator circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a fuller understanding of the nature and advantages of the present concepts, reference is made to the following detailed description of preferred embodiments and in connection with the accompanying drawings. In the drawings, like reference characters generally refer to like features (e.g., functionally-similar and/or structurally-similar elements).

(2) FIG. 1 is a schematic illustration of a first order discrete-time delta-sigma converter 20 according to the prior art.

(3) FIG. 2 is a schematic illustration of an approximate linear model of the first order discrete-time delta-sigma converter illustrated in FIG. 1, according to the prior art.

(4) FIG. 3 is a schematic illustration of a linear model of a second-order delta-sigma ADC according to the prior art.

(5) FIG. 4 is a schematic illustration of a second order delta-sigma ADC with an additional feedback path for loop stability, according to the prior art.

(6) FIG. 5 is a schematic illustration of a second order delta-sigma ADC with an additional feedforward path for loop stability, according to the prior art.

(7) FIG. 6 is a schematic illustration of a switched-capacitor integrator according to the prior art.

(8) FIG. 7 is a schematic illustration of a fully-differential switched-capacitor integrator according to the prior art.

(9) FIG. 8 is a schematic illustration of a fully-differential switched-capacitor integrator with a zero in the transfer function according to the prior art.

(10) FIG. 9 is a schematic illustration of a fully-differential switched-capacitor delayed integrator with a transfer function that includes a zero within the unit circle in the complex plane, according to one or more embodiments of the invention.

(11) FIG. 10 is a schematic illustration of a circuit that includes a cascade of a fully-differential switched-capacitor delayless integrator and a fully-differential switched-capacitor delayed integrator, according to one or more embodiments of the invention.

(12) FIG. 11 illustrates a second order delta-sigma ADC according to one or more embodiments of the invention.

(13) FIG. 12 shows a third order delta-sigma ADC according to one or more embodiments of the invention.

(14) FIG. 13 shows a continuous-time and discrete-time hybrid third order delta-sigma ADC according to one or more embodiments of the invention.

DETAILED DESCRIPTION

(15) High order delta-sigma A/D converters are desirable because they provide high SNR at a low OSR, but they must be stabilized by at least one zero in the transfer function. Prior art delta-sigma converters employ feedback or feedforward topologies to provide the zeros. However, they incur a penalty in additional circuitry such as additional D/A converters or another operational amplifier. In view of the foregoing, various inventive embodiments disclosed herein generally relate to delta-sigma converter circuits that provide feed-forward for loop stability without adding substantial complexity to the circuit.

(16) Following below are more detailed descriptions of various concepts related to, and embodiments of, inventive apparatus relating to non-switched capacitor circuits for delta-sigma ADCS. It should be appreciated that various concepts introduced above and discussed in greater detail below may be implemented in numerous ways, as the disclosed concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

(17) FIG. 1 is a schematic illustration of a first order discrete-time delta-sigma converter 20 according to the prior art. The converter 20 includes an analog subtractor 21, a discrete time integrator 22, an A/D converter 23, and a D/A converter 24. Typically, both the A/D converter and the D/A converter have only 1 to 5 bits of resolution. The signal X represents the analog input voltage, and the signal Y represents the digital output. The discrete-time integrator 22 has the following transfer function:

(18) $\begin{array}{cc}H\left(z\right)=\frac{z^{-1}}{1-z^{-1}}& \left(1\right)\end{array}$

(19) Since the A/D converter and the D/A converter are nonlinear elements, the precise mathematical modeling of the delta-sigma converter 20 is extremely complicated. FIG. 2 is a schematic illustration of an approximate linear model of the first order discrete-time delta-sigma converter 20 according to the prior art. The approximate linear model is often utilized to gain intuition on the operation of delta-sigma converters. In the linear model, the ADC 23 and DAC 24 pair is modeled as a direct path with quantization noise Q added. Mathematically, it can be shown from FIG. 2 that the digital output Y is given by:
Y=z.sup.1X+(1z.sup.1)Q(2)
which indicates that the digital output is the sum of the delayed input plus first-order differentiated quantization noise. The quantization noise is referred to as having been first-order noise-shaped by the first-order differentiation. The noise shaping suppresses low-frequency quantization noise by the differentiation. By digitally low-pass filtering the digital output, the in-band quantization noise in the output signal Y is reduced as compared to standard (non-noise shaped) quantization. In non-noise shaped quantization, the in-band quantization noise Q.sub.b is shown to be

(20) $\begin{array}{cc}{Q}_b=\frac{Q_t}{{\left(\mathrm{OSR}\right)}^{\frac{1}{2}}}& \left(3\right)\end{array}$
where Q.sub.t is the total quantization noise before low pass filtering, and OSR is the oversampling ratio given by:

(21) $\begin{array}{cc}\mathrm{OSR}=\frac{f_s}{2f_b}& \left(4\right)\end{array}$
where f.sub.s is the sampling frequency and f.sub.b is the signal bandwidth. Thus, 2 oversampling provides {square root over (2)} or 3 dB reduction of in-band quantization noise. 256 oversampling provides 24 dB reduction in in-band quantization noise. It can be shown that the first order noise-shaped quantization yields in-band quantization noise of

(22) $\begin{array}{cc}{Q}_b=\frac{Q_t}{{\left(\mathrm{OSR}\right)}^{\frac{3}{2}}}& \left(5\right)\end{array}$

(23) Thus, 2 and 256 oversampling yields 9 dB and 72 dB reduction of in-band quantization noise, respectively, which is much more effective in providing high SNR compared with the non-noise shaped quantizer.

(24) In typical embodiments of delta-sigma ADCS, the discrete-time integrator 22 has a transfer function

(25) $\begin{array}{cc}H\left(z\right)=\frac{{\mathrm{kz}}^{-1}}{1-z^{-1}}& \left(6\right)\end{array}$
where the value k is not unity, but determined by a ratio between a sampling capacitor and an integration capacitor in the switched-capacitor integrator as illustrated below.

(26) Mathematically, it can be shown that the digital output Y is:

(27) $\begin{array}{cc}Y=H\left(z\right)X+G\left(z\right)Q\mathrm{where}& \left(7\right)\\ H\left(z\right)=\frac{{\mathrm{kz}}^{-1}}{1+\left(k-1\right)z^{-1}}\mathrm{and}& \left(8\right)\\ G\left(z\right)=\frac{1-z^{-1}}{1+\left(k-1\right)z^{-1}}& \left(9\right)\end{array}$

(28) The transfer function H(z) from the input to the output has a low-pass characteristic. Therefore, in the signal band which is limited to low frequency, the input signal is not substantially attenuated, and the digital output is an accurate representation of the analog input. The transfer function G(z) from the quantization noise to the output has a high-pass characteristic; thus the quantization noise is reduced (first-order shaped) in the signal band.

(29) Obviously, higher-order noise shaping can reduce the in-band quantization noise even further. FIG. 3 is a schematic illustration of a second-order delta-sigma ADC 30 according to the prior art. In FIG. 3, the second-order delta-sigma ADC includes two integrators 22 and 25. While the second order delta-sigma ADC theoretically provides higher order noise shaping and lower in-band quantization noise, the issue is the loop stability. It can be shown that the two discrete-time integrators connected in series contribute a phase delay of at least 2, thus the loop becomes unstable. The delay through the quantizer 300 (the ADC 23 and DAC 24 pair) adds more phase delay and exacerbates the stability. One way to ensure stability in higher order delta-sigma ADCS is to insert feedforward or feedback paths that reduce the phase shift around the loop's cross-over frequency. For example, the delta-sigma ADC 40 in FIG. 4 employees an additional feedback path 400 to the input of the second integrator 25. This additional path 400 facilitates a loop around the second integrator 25 at high frequencies with correspondingly lower phase delay. The drawback is that the additional feedback path 400 requires an additional DAC 27 and an additional subtractor 26, thus increasing complexity and power consumption.

(30) Another example is shown in FIG. 5, which is a schematic illustration of a second order delta-sigma ADC 50 with an additional feedforward path 500 for loop stability where the feedforward path 500 is inserted from the output of the first integrator 22 to the input of the quantizer 300. The feedforward path 500 provides a loop around only the first integrator 22 at high frequencies bypassing the second integrator 25, and thus has a lower phase delay. The drawback is that an analog summing circuit 28 is needed at the input of the quantizer 300, which is typically implemented using an op amp, again increasing complexity and power consumption.

(31) The discrete-time integrators such as the ones in FIGS. 2, 3, 4, and 5 are typically implemented in a switched-capacitor form. An example of a switched-capacitor integrator 60 is shown in FIG. 6 comprising a sampling capacitor 61, an integrating capacitor 62, an operational amplifier (op amp) 63, and switches S.sub.1 through S.sub.4. It operates off two non-overlapping clock phases .sub.1 and .sub.2. Two different clocking schemes can be chosen; In the first scheme, the clock phases .sub.1 and .sub.2 without the parentheses are used. In the second scheme, the clock phases .sub.1 and .sub.2 within the parentheses are used. Each of the switches S.sub.1 through S.sub.4 is closed when corresponding clock phase (.sub.1 or .sub.2) shown next to the switch is high; otherwise, it is open. For example, in the circuit in FIG. 6, when the first clocking scheme (clock signals without the parentheses) is employed, switches S.sub.2 and S.sub.4 are closed when .sub.1 is high, and switches S.sub.1 and S.sub.3 are closed when .sub.2 is high. When .sub.1 is high, sampling capacitor C.sub.S is discharged. When .sub.2 is high, the input voltage v.sub.i is applied to C.sub.S, resulting in a transfer function

(32) $\begin{array}{cc}H\left(z\right)=\frac{V_o}{V_i}=-\frac{C_S}{C_I}.Math.\frac{1}{1-z^{-1}}& \left(10\right)\end{array}$
This transfer function corresponds to a delayless inverting integrator.

(33) In some instances, a delayed integration of the input signal is desired, which can be achieved by using the second clocking scheme (clock signals .sub.1 and .sub.2 within the parentheses) in FIG. 6. The switches S.sub.1 and S.sub.4 are closed when .sub.1 is high, and switches S.sub.2 and S.sub.3 are closed when .sub.2 is high. When .sub.1 is high, the input voltage v.sub.i is sampled across the sampling capacitor C.sub.S. When .sub.2 is high, the sampled charge is transferred to the integrating capacitor C.sub.I. The resulting transfer function is given by

(34) $\begin{array}{cc}H\left(z\right)=\frac{V_o}{V_i}=-\frac{C_S}{C_I}.Math.\frac{z^{-1}}{1-z^{-1}}& \left(11\right)\end{array}$
This transfer function corresponds to a non-inverting integrator with a full delay.

(35) FIG. 7 is a schematic illustration of a fully-differential switched-capacitor integrator 70 according to the prior art. The fully-differential switched-capacitor integrator 70 is a fully-differential version of integrator 60 in FIG. 6. In the fully-differential switched-capacitor integrator 70, V.sub.CM is the system common-mode voltage. The sampling capacitors C.sub.Sp and C.sub.Sn in integrator 70 are the same as sampling capacitor C.sub.S in integrator 60 (i.e., C.sub.Sp=C.sub.Sn=C.sub.S), and the integrating capacitors C.sub.Ip and C.sub.In in integrator 70 are the same as integrating capacitor C.sub.I in integrator 60 (i.e., C.sub.Ip=C.sub.In=C.sub.I).

(36) As with the switched-capacitor integrator 60 in FIG. 6, two different clocking schemes can be chosen; In the first scheme, the clock phases 4 and .sub.2 without the parentheses are used. In the second scheme, the clock phases .sub.1 and .sub.2 within the parentheses are used. Each of the switches S.sub.1p through S.sub.4p and S.sub.1n through S.sub.4n is closed when corresponding clock phase (.sub.1 or .sub.2) shown next to the switch is high; otherwise, it is open.

(37) The difference between differential input voltages v.sub.ip and v.sub.in in integrator 70 is equal to the input voltage v.sub.i in integrator 60 (i.e., v.sub.ip and v.sub.in=v.sub.ipv.sub.in). Likewise, the difference between differential output voltages v.sub.op and v.sub.on in integrator 70 is equal to the output voltage v.sub.o in integrator 60 (i.e., v.sub.o=v.sub.opv.sub.on). differential output voltages v.sub.op and v.sub.on correspond to the positive and negative outputs of op amp 700. Delayless inverting integration is performed if clock phasing without the parentheses is employed, and delayed noninverting integration is performed if clock phasing within the parentheses is employed. In fully-differential integrators such as the one shown in FIG. 7, the polarity inversion is obtained by swapping either the inputs v.sub.ip and v.sub.in, or the outputs v.sub.op and v.sub.on, thus either inverting or noninverting integration can be achieved with or without delay.

(38) In some applications, it is desirable to have a zero in the transfer function of the integrator, primarily for better loop stability. FIG. 8 is a schematic illustration of a fully-differential switched-capacitor integrator 80 with a zero according to the prior art. It is similar to integrator 70 in FIG. 7, but non-switched capacitors C.sub.1p and C.sub.1n are added to integrator 80. Non-switched capacitors C.sub.1p and C.sub.1n in integrator 80 are equal to integrating capacitor C.sub.I in integrator 60 (i.e., C.sub.1p=C.sub.1n=C.sub.1). As with the fully-differential switched-capacitor integrator 70 in FIG. 7, two different clocking schemes can be chosen; In the first scheme, the clock phases .sub.1 and .sub.2 without the parentheses are used. In the second scheme, the clock phases .sub.1 and .sub.2 within the parentheses are used. Each of the switches S.sub.1p through S.sub.4p and S.sub.1n through S.sub.4n is closed when corresponding clock phase (.sub.1 or .sub.2) shown next to the switch is high; otherwise, it is open.

(39) If clock phasing without parentheses is employed, the resulting transfer function of the integrator 80 is given by:

(40) $\begin{array}{cc}H\left(z\right)=\frac{V_o}{V_i}=-\frac{C_S}{C_I}.Math.\frac{z^{-1}}{1-z^{-1}}-\frac{C_1}{C_I}=-\frac{1}{C_I}.Math.\frac{C_S+C_1-C_1{z}^{-1}}{1-z^{-1}}& \left(12\right)\end{array}$

(41) Compared with the transfer function of the integrator in Equation (11), which has a pole at z=1 and no zero in the transfer function, the additional capacitor C.sub.1 provides a zero at

(42) 0$z=\frac{C_1}{C_S+C_1}$
in the transfer function of the integrator 80. Since the zero is within the unit circle in the complex plane, it raises the phase as frequency rises towards the sampling frequency, and improves the stability in a feedback loop that employs such an integrator.

(43) On the other hand, if clock phasing in the parentheses is employed, the resulting transfer function of the integrator 80 is given by:

(44) $\begin{array}{cc}H\left(z\right)=\frac{V_o}{V_i}=\frac{C_S}{C_I}.Math.\frac{z^{-1}}{1-z^{-1}}-\frac{C_1}{C_I}=-\frac{1}{C_I}.Math.\frac{C_1-\left(C_S+C_1\right)z^{-1}}{1-z^{-1}}& \left(13\right)\end{array}$

(45) In this case, the zero is outside the unit circle in the complex plane, and it lowers the phase as frequency rises towards the sampling frequency, exacerbating stability. Therefore, this clock phasing is not suitable for improving stability of a feedback loop that employs such an integrator. Integrator 80 is disclosed in A. Pertijs, et. al., A CMOS Smart Temperature Sensor With a 3 Inaccuracy of +0.1 C. From 55 C. to 125 C., IEEE Journal of Solid-State Circuits, pp. 2805-2815, vol. SC-40, No. 12, December 2005, which is hereby incorporated by reference.

(46) There are instances where delayed integration is desired with a zero inside the unit circle. Such need arises typically in high-order delta-sigma ADCS. In high-order delta-sigma ADCS, high-order noise shaping is achieved by cascading integrators. For an optimum loop transfer function, delayless and delayed integrators are often alternated. In such cases, a delayed integrator with a zero inside the unit circle may be desired. However, such an integrator is unavailable in the prior art.

(47) FIG. 9 is a schematic illustration a fully-differential switched-capacitor delayed integrator 90 with a transfer function that includes a zero within the unit circle in the complex plane, according to one or more embodiments of the invention. In contrast to integrator 80 in FIG. 8, the non-switched capacitors C.sub.1p and C.sub.1n are connected to the opposite polarity inputs such that non-switched capacitor C.sub.1p receives the negative input voltage v.sub.in instead of the positive input voltage v.sub.ip (as in integrator 80), and non-switched capacitor C.sub.1N receives the positive input voltage v.sub.ip instead of the negative input voltage v.sub.in (as in integrator 80). The integrator 90 includes first and second outputs 910, 920, which correspond to positive and negative differential output voltages v.sub.op and v.sub.on, respectively. The first output 910 is in electrical communication with the positive input voltage v.sub.ip and the second output 920 is in electrical communication with the negative input voltage v.sub.in. The first and second outputs 910, 920 are also coupled to the outputs of discrete-time integrator 900.

(48) As with integrator 80 in FIG. 8, two different clocking schemes can be chosen; In the first scheme, the clock phases .sub.1 and .sub.2 without the parentheses are used. In the second scheme, the clock phases .sub.1 and .sub.2 within the parentheses are used. Each of the switches S.sub.1p through S.sub.4p and S.sub.1n through S.sub.4n is closed when corresponding clock phase (.sub.1 or .sub.2) shown next to the switch is high; otherwise, it is open.

(49) Using clock phasing inside the parenthesis, the resulting transfer function is given by:

(50) $\begin{array}{cc}H\left(z\right)=\frac{V_o}{V_i}=\frac{C_S}{C_I}.Math.\frac{z^{-1}}{1-z^{-1}}+\frac{C_1}{C_I}=-\frac{1}{C_I}.Math.\frac{C_1+\left(C_S-C_1\right)z^{-1}}{1-z^{-1}}& \left(14\right)\end{array}$

(51) Compared with the transfer function of integrator 80 in Equation (13) which has a pole at z=1 and a zero that is outside the unit circle in the complex plane when clock phasing in the parentheses is employed, the additional capacitors C.sub.1p=C.sub.1n=C.sub.1 provide a zero at

(52) $z=\frac{C_1-C_S}{C_1}.$
Since the zero is inside the unit circle in the complex plane, it raises the phase as frequency rises towards the sampling frequency, and thus improves stability. In certain applications, delayless integration with a zero outside the unit circle in the complex plane may be desired despite the fact that stability is compromised. In such cases, clock phasing without the parenthesis can be used to yield a transfer function:

(53) $\begin{array}{cc}H\left(z\right)=\frac{V_o}{V_i}=-\frac{C_S}{C_I}.Math.\frac{1}{1-z^{-1}}+\frac{C_1}{C_I}=\frac{1}{C_I}.Math.\frac{C_1-\left(C_S-C_1\right)z^{-1}}{1-z^{-1}}& \left(15\right)\end{array}$

(54) FIG. 10 is a schematic illustration of a circuit 1000 that includes a cascade of a fully-differential switched-capacitor delayless integrator 1001 and a fully-differential switched-capacitor delayed integrator 1003, according to one or more embodiments of the invention. The delayless integrator 1001 is cascaded with a delayed integrator 1003. Such a cascade effectively eliminates the phase error in discrete-time integration. The delayed integrator 1003 (e.g., a discrete time integrator) has additional non-switched capacitors C.sub.1p and C.sub.1n to implement a zero inside the unit circle in the complex plane. Various switches in FIG. 10 are closed when corresponding clock phase (.sub.1 or .sub.2) shown next to a switch is high; otherwise, they are open. The transfer function

(55) $H\left(z\right)=\frac{v_1}{v_i}$
has a two-series integration with a zero

(56) $z=\frac{C_1-C_S}{C_1},$
which is inside the unit circle in the complex plane. Clock phasing without the parenthesis yields the following transfer function:

(57) $\begin{array}{cc}H\left(z\right)=\frac{V_o}{V_i}=-\frac{C_{S1}}{C_{I1}}.Math.\frac{z^{-1}}{1-z^{-1}}\left(\frac{C_{S2}}{C_{I2}}.Math.\frac{1}{1-z^{-1}}-\frac{C_1}{C_{I2}}\right)=-\frac{C_{S1}}{C_{I1}}.Math.\frac{z^{-1}}{C_{I2}}.Math.\frac{C_{S2}+C_1-C_1{z}^{-1}}{{\left(1-z^{-1}\right)}^2}& \left(16\right)\end{array}$

(58) FIG. 11 illustrates another embodiment of the invention, showing a second order delta-sigma ADC 1100. As in FIG. 10, a delayless integrator 1001 is cascaded with a delayed integrator 1003 (e.g., a discrete time integrator). The delayless integrator 1001 has first and second outputs 1102, 1104, respectively. The first output 1102 is in electrical communication with a positive integrator input 1112 of the delayed integrator 1003, and the second output 1104 is in electrical communication with a negative integrator input 1114 of the delayed integrator 1003.

(59) Such a cascade effectively eliminates the phase error in discrete-time integration. The non-switched capacitors C.sub.1p and C.sub.1n implement a zero inside the unit circle. Various switches in FIG. 11 are closed when corresponding clock phase (.sub.1 or .sub.2) shown next to a switch is high; otherwise, they are open. An analog-to-digital converter (ADC) 1110, preferably a flash-type ADC, produces a digital output. The output of the ADC 1110 is electrically coupled to the input of a digital-to-analog converter (DAC) 1120. The digital output of ADC 110 is the converted back to analog by DAC 1120, preferably a switched-capacitor type. The DAC 1120 is coupled to the input of the first integrator 1001 to complete the delta-sigma ADC 1100 loop.

(60) The forward transfer function

(61) $H\left(s\right)=\frac{v_1}{v_i}$
has two-series integration with a zero

(62) $z=\frac{C_1-C_S}{C_1},$
as in the cascaded integrators in FIG. 10, which is inside the unit circle in the complex plane. At high frequencies, the zero raises the phase thus making the loop more stable in the delta-sigma ADC 1100. This effectively provides a feedforward path without requiring an analog summing circuit at the input of the quantizer (e.g., as in ADC 50). The ratio between C.sub.S and C.sub.1 are selected to place the zero at an optimum frequency for stability and noise shaping. The lower the zero frequency, the more stable the loop becomes (e.g., higher phase margin). However, the noise shaping is compromised due to the zero resulting in a lower SNR for a given OSR.

(63) FIG. 12 illustrates another embodiment of the invention, a third order delta-sigma ADC 1200. Two pairs of non-switched capacitors C.sub.1p and C.sub.1n couple the positive and negative outputs of the first integrator 1210 and the noninverting and inverting inputs, respectively, of the op amp 700 of the second integrator 1220, and non-switched capacitors C.sub.2p and C.sub.2n couple the positive and negative outputs of the first integrator 1210 and the noninverting and inverting inputs, respectively, of the op amp 700 of the third integrator 1230 to implement two zeros inside the unit circle in the complex plane. In FIG. 12, the first and third integrators 1210, 1230 are delayless integrators and the second integrator 1220 is a delayed integrator. Various switches in FIG. 12 are closed when corresponding clock phase (.sub.1 or .sub.2) shown next to a switch is high; otherwise, they are open.

(64) FIG. 13 shows another embodiment of the invention, a third order delta-sigma ADC 1300, where the first stage is a continuous-time integrator 1310. Two pairs of non-switched capacitors C.sub.1p and C.sub.1n couple the positive and negative outputs of the first integrator 1310 and the noninverting and inverting inputs, respectively, of the op amp 700 of the second integrator 1320, and non-switched capacitors C.sub.2p and C.sub.2n couple the positive and negative outputs of the first integrator 1310 and the noninverting and inverting inputs, respectively, of the op amp 700 of the third integrator 1330 to implement two zeros inside the unit circle in the complex plane. In FIG. 13, the third integrator 1330 is a delayless integrator and the second integrator 1320 is a delayed integrator. Various switches in FIG. 13 are closed when corresponding clock phase (.sub.1 or .sub.2) shown next to a switch is high; otherwise, they are open.

(65) While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

(66) The invention should not be considered limited to the particular embodiments described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent processes, as well as numerous structures to which the invention may be applicable, will be apparent to those skilled in the art to which the invention is directed upon review of this disclosure. The claims are intended to cover such modifications and equivalents.