Rational Ratio Multiplier (RRM) With Optimized Duty Cycle implementation

Abstract

Design and methods for implementing a Rational Ratio Multiplier (RRM) with close to 50% duty cycle. This invention gives an optimal way to implement RRM that save both area and power for a given design and able to achieve a good accuracy of the output clock with a difference between the high period and the low period of the output clock by only half a cycle of the input clock which is the closest to get to 50% duty cycle clock.

Claims

1. A Rational Ratio Multiplier (RRM) implementation comprising: a pair of inputs of N and D which gives the rational ratio fraction N/D while D>N; two registers which store the high and low periods of the output clock counting the number of rising and falling edges of the input clock; a counter that counts from 1 to the sum of the high period plus the low period; 4 T-FF's which two of them samples at the rising edge of the input clock and two at the falling edge of the input clock; random logic which generate from these 4 T-FF's the required frequency multiply output clock.

2. An RRM implementation of claim 1, wherein the high period and low period of the output clock are measured by the number of rising and falling edges of the input clock.

3. An RRM implementation of claim 1, wherein the high period of the output clock is either equal to the low period of the output clock (duty cycle of 50%) when N is equal to 1, or the high period of the output clock is larger by 1 half period of the input clock from the low period of the output clock if N isn't equal to 1.

4. An RRM implementation of claim 1, wherein the 4 T-FF's toggle as following: first T-FF which samples at the rising edge of input clock toggles when the counter equals to the high period or the sum of both the high and low periods; second T-FF which samples at the rising edge of input clock toggles when the counter equals to the half of the high period or the half of the sum of both the high and the low periods; third T-FF which samples at the falling edge of input clock toggles when the counter equals to the high period or the sum of both the high and low periods; fourth T-FF which samples at the falling edge of input clock toggles when the counter equals to the half of the high period+1 or the half of the sum of both the high and low periods+1.

5. An RRM implementation of claim 1, wherein the output clock is generated when N isn't equal to 1 by a XOR between one AND function of the first T-FF and the third T-FF with another AND function of the second T-FF and the fourth T-FF.

6. An RRM implementation of claim 1, wherein the output clock is generated when N is equal to 1 either by a XOR of the first T-FF with the fourth T-FF when the high period is odd or the XOR of the first T-FF with the second T-FF when the high period is even.

Description

DESCRIPTION OF INVENTION

[0015] To get an RRM which can work on any fractional ratio and give close to 50% duty cycle a new implementation is proposed which performs this accurate clock multiplication.

[0016] This invention may be used by any system which requires an accurate clock multiplication using a rational fraction ratio and requires an output clock with close to 50% duty cycle so any negative edge logic which uses this clock can work with timing constraint of the output clock.

[0017] This invention has been described as including various operations. Many of the processes are described in their most basic form, but operations can be added to or deleted from any of the processes without departing from the scope of the invention.

[0018] RRM Implementation with Optimized Duty Cycle—FIG. 4

[0019] The RRM implementation under this invention generates an output clock with cycle time which is the multiplication of the input clock by the fraction rational ratio of N/D while D>N.

[0020] The duty cycle of the resulted output clock is close to 50% with a difference of only one half a cycle of the input-clock between the high period and the low period of output clock.

[0021] The implementation under this invention is programmed by receiving the value of N (box 400 in FIG. 4) and D (box 401 in FIG. 4). The RRM implementation calculate the low period (box 403 in FIG. 4) which is the number of rising and falling edges of the input clock pulses that the output clock should be at zero and the high period (box 406 in FIG. 4) which is the number of rising and falling edges of the input clock pulses that the output clock should be at one. The low period is calculated according to the result of the D DIV N calculation (box 402 in FIG. 4) The high period equals to the low period if N==1 (this is the same as the implementation of a 1/D divider) or equals to the low period plus one (as shown with box 404 in FIG. 4).

[0022] In addition to the above, this invention includes a counter which counts from 1 to the sum of low period+high period (box 404 in FIG. 4) using the rising edge of the input clock.

[0023] Connected to this counter are 4 T-FF's which 2 of them are sampling on the rising edge of input clock and the other two on the falling edge of input clock. These FF's are toggling when the counter equals to the following values: [0024] The first T-FF (box 408 in FIG. 4) which samples at the rising edge of input clock toggles when the counter equals the high period or the sum of both the high and low periods. [0025] The second T-FF (box 409 in FIG. 4) which samples at the rising edge of input clock toggles when the counter equals to half of the high period or the half of the sum of both the high and low periods. [0026] The third T-FF (box 410 in FIG. 4) which samples at the falling edge of input clock toggles when the counter equals to the high period or the sum of both the high and low periods. [0027] The fourth T-FF (box 411 in FIG. 4) which samples at the falling edge of input clock toggles when the counter equals to the half of the high period+1 or the half of the sum of both the high and low periods+1

[0028] When N isn't equal to 1 (this means that the implementation isn't a 1/D implementation) then the output clock is generated by a XOR (box 414 in FIG. 4) with one AND function between the first T-FF and the third T-FF (box 413 in FIG. 4) with another AND function between the second T-FF and the fourth T-FF (box 412 in FIG. 4).

[0029] When N is equal to 1 (this means that the implementation is a 1/D implementation), the output clock is generated either by a XOR of the first T-FF with the fourth T-FF (box 416 in FIG. 4) when the high period is odd, or by a XOR of the first T-FF with the second T-FF (box 415 in FIG. 4) when the high period is even. The selection between these two XOR's is done by a multiplexer (box 417 in FIG. 4) which generate the output clock if N is equal to 1.

[0030] The last multiplexer on the output (box 418 in FIG. 4) is selecting the correct clock between the above two implementation depending on whether N is equal to 1 or not.