Vertical structure LEDs

Abstract

A method for manufacturing a light emitting diode can include forming a GaN-based semiconductor structure with a thickness of less than 5 microns on a substrate, the GaN-based semiconductor structure having a p-type GaN-based semiconductor layer; an active layer on the p-type GaN-based semiconductor layer; and an n-type GaN-based semiconductor layer on the active layer; forming a p-type electrode having multiple metal layers on the GaN-based semiconductor structure; forming a metal support layer on the p-type electrode; removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure; forming an n-type electrode on a flat portion produced by polishing the exposed upper surface of the GaN-based semiconductor structure, not only with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure but also with contacting the flat portion; and forming an insulating layer on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure, in which a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure and a side surface of the n-type electrode, and a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.

Claims

1. A method for manufacturing a light emitting diode, comprising: forming a GaN-based semiconductor structure with a thickness of less than 5 microns on a substrate, the GaN-based semiconductor structure comprising: a p-type GaN-based semiconductor layer; an active layer on the p-type GaN-based semiconductor layer; and an n-type GaN-based semiconductor layer on the active layer; forming a p-type electrode having multiple metal layers on the GaN-based semiconductor structure; forming a metal support layer on the p-type electrode; removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure; forming an n-type electrode on a flat portion produced by polishing the exposed upper surface of the GaN-based semiconductor structure, not only with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure but also with contacting the flat portion; and forming an insulating layer on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure, wherein a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure and a side surface of the n-type electrode, and wherein a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.

2. The method according to claim 1, further comprising: forming an open space exposing the n-type electrode by patterning the first part of the insulating layer; and forming a metal pad layer at the open space, the metal pad layer comprising: a first portion having a flat bottom surface on the n-type electrode; and a second portion having stepped surfaces.

3. The method according to claim 2 wherein a width of the open space is different from a width of the metal pad layer, and wherein a width of the p-type electrode is wider than a width of the n-type electrode.

4. The method according to claim 1, wherein the insulating layer includes at least one of SiO.sub.2 or Si.sub.3N.sub.4, and wherein the insulating layer is formed to extend to between the p-type GaN-based semiconductor layer of the GaN-based semiconductor structure and the metal support layer, with overlapping the first part of the insulating layer in the thickness direction of the GaN-based semiconductor structure.

5. The method according to claim 1, wherein a thickness of the GaN-based semiconductor structure is smaller than a thickness of the metal support layer.

6. The method according to claim 1, wherein the metal support layer is made of least two metals selected from. the group consisting of Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, and W.

7. The method according to claim 2, wherein the first part of the insulating layer contacts an upper surface of the n-electrode, and wherein an uppermost surface of the metal pad layer is formed at a higher position than the first part of the insulating layer.

8. The method according to claim 1, wherein a ratio of the thickness occupied by the p-type GaN-based semiconductor layer in the GaN-based semiconductor structure is higher than 1%.

9. The method according claim 1, wherein an area of a portion contacting the p-type GaN-based semiconductor layer in the insulating layer is smaller than an area of a portion contacting the n-type GaN-based semiconductor layer in the insulating layer.

10. The method according to claim 1, wherein the p-type electrode includes Pt or Ni.

11. The method according to claim 2, wherein the metal ad layer includes at least one of Cr or Au.

12. A method for manufacturing a light emitting diode, comprising: forming a GaN-based semiconductor structure with a thickness of less than 5 m on a substrate, the GaN-based semiconductor layer comprising: a p-type GaN-based semiconductor layer; an active layer on the p--type GaN-based semiconductor layer; and an n-type GaN-based semiconductor layer on the active layer; forming a p-type electrode on the p-type GaN-based semiconductor layer; forming a metal support layer on the p-type electrode; removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure; forming an n-type electrode on the upper surface of the GaN-based semiconductor structure, with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure and with contacting a flat top portion produced by polishing the exposed upper surface of the GaN-based semiconductor structure; forming an insulating layer on an upper surface of the GaN-based semiconductor structure and on a side surface of the GaN-based semiconductor structure, wherein a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure, a side surface of the n-type electrode, and a top surface of the n-type electrode; forming an open space exposing the n-type electrode by patterning the first part of the insulating layer; and forming a metal pad layer at the open space, the metal pad layer comprising: a first portion having a flat bottom surface on the n-type electrode; and a second portion having stepped surfaces, the first width of the first portion of the metal pad layer being different from a second width of the second portion of the metal pad layer, wherein an area of a portion contacting the p-type GaN-based semiconductor layer in the insulating layer is smaller than an area of a portion contacting the n-type GaN-based semiconductor layer in the insulating layer, wherein the p-type electrode contacts a top surface of the metal support layer and a bottom surface of the GaN-based semiconductor structure, and wherein the second portion of the metal pad layer overlaps the first portion of the metal pad layer in the thickness direction of the GaN-based semiconductor structure.

13. The method according to claim 12, wherein a sum of the thickness of the GaN-based semiconductor structure and a thickness of the p-type electrode is less than a sum of 10 nm and 5 m.

14. The method according to claim 12, wherein the metal pad layer is formed to have a thickness greater than a thickness of the n-type electrode.

15. The method according to claim 12, wherein the GaN-based semiconductor structure is formed to have a width different from a width of the p-type electrode.

16. The method according to claim 12, wherein the p-type electrode is formed to have a width larger than a width of the n-type electrode.

17. The method according to claim 12, wherein the p-type electrode is formed to have a width smaller than a width of the metal support layer.

18. The method according to claim 12, wherein the n-type electrode comprises at least one of Al or Ti and the p-type electrode comprises at least one layer of Pt or Ni.

19. The method according to claim 12, wherein the insulating layer is formed to extend to between the p-type GaN-based semiconductor layer of the GaN-based semiconductor structure and the metal support layer, and wherein the extended part of the insulating layer overlaps the first part of the insulating layer in the thickness direction of the GaN-based semiconductor structure.

20. A method for manufacturing a light emitting diode, comprising: forming a GaN-based semiconductor structure with a thickness of a less than 5 microns on a substrate, the GaN-based semiconductor layer comprising: a p-type GaN-based semiconductor layer; an active layer on the p-type GaN-based semiconductor layer; and an n-type GaN-based semiconductor layer on the active layer; forming a p-type electrode having multiple metal layers on the p-type GaN-based semiconductor layer with contacting a bottom surface of the Gall-based semiconductor structure; forming a metal support layer comprising Ti and non-metal material on the p-type electrode, a top surface of the metal support layer contacting the p-type electrode; removing the substrate from the GaN-based semiconductor structure to expose an upper surface of the GaN-based semiconductor structure; forming an n-type electrode comprising Ti and Al on the upper surface of the GaN-based semiconductor structure, with overlapping at least a portion of the p-type electrode in a thickness direction of the GaN-based semiconductor structure; forming an insulating layer including at least one of SiO.sub.2 or Si.sub.3N.sub.4, on the upper surface of the GaN-based semiconductor structure and on an entire side surface of the GaN-based semiconductor structure, wherein a first part formed on the upper surface of the GaN-based semiconductor structure in the insulating layer contacts the upper surface of the GaN-based semiconductor structure; forming an open space exposing the n-type electrode by patterning the first part of the insulating layer; and forming a metal pad layer at the open space, an uppermost surface of the metal pad layer being formed at a higher position than the first part of the insulating layer, wherein a second part formed on the entire side surface of the GaN-based semiconductor structure in the insulating layer does not contact the n-type electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying figures, in which like reference numerals refer to identical or functionally-similar elements throughout the separate views and which are incorporated in and form part of the specification, further illustrate the present invention and, together with the detailed description of the invention, serve to explain the principles of the present invention.

(2) In the drawings:

(3) FIG. 1A illustrates a sectional view of a typical lateral topology GaN-based LED;

(4) FIG. 1B shows a top down view of the GaN-based LED illustrated in FIG. 1A;

(5) FIG. 2A illustrates a sectional view of a typical vertical topology GaN-based LED;

(6) FIG. 2B shows a top down view of the GaN-based LED illustrated in FIG. 2A; and

(7) FIGS. 3-15 illustrate steps of forming a light emitting diode that are in accord with the principles of the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

(8) The principles of the present invention provide for methods of fabricating semiconductor devices, such as GaN-based vertical topology LEDs, on insulating substrates, such as sapphire substrates, using metal support films. While those principles are illustrated in a detailed description of a method of fabricating vertical topology GaN-based LEDs on a sapphire substrate, those principles are broader than that illustrated method. Therefore, the principles of the present invention are to be limited only by the appended claims as understood under United States Patent Laws.

(9) FIGS. 3-15 illustrate a method of manufacturing vertical topology GaN-based light emitting diodes (LEDs) on sapphire substrates. Sapphire substrates are readily available in suitable sizes, are thermally, chemically, and mechanically stable, are relatively inexpensive, and support the growth of good quality GaN epitaxial layers. It should be understood that those figures are not to scale.

(10) Referring now to FIG. 3, initially a GaN-based LED layer structure is formed on a 330-430 micron-thick, 2 diameter (0001) sapphire substrate 122. The GaN-based LED layer structure includes an n-GaN buffer layer 124, an InGaN/GaN active layer 126 (beneficially having the proper composition to emit blue light) on the buffer layer 124, and a p-GaN contact layer 128 on the active layer 126.

(11) Still referring to FIG. 3, the buffer layer 124 beneficially includes both a 2 m undoped GaN layer formed directly on the substrate, and a 1 m thick, n-type, silicon doped, GaN layer. The p-GaN contact layer 128 is beneficially about 0.05 m thick and is doped with Mg. Overall, the GaN-based LED layer structure is beneficially less than about 5 microns thick. For instance, a ratio of a thickness of the buffer layer 124 to the thickness of the GaN-based LED layer structure can be more than 60%. Various standard epitaxial growth techniques, such as vapor phase epitaxy, MOCVD, and MBE, together with suitable dopants and other materials, can be used to produce the GaN-based LED layer structure.

(12) Referring now to FIG. 4, trenches 130 are formed through the vertical topology GaN-based LED layer structure. Those trenches 130 may extend into the sapphire substrate 122. The trenches 130 define the individual LED semiconductor structures that will be produced. Each individual LED semiconductor structure is beneficially a square about 200 microns wide. The trenches 130 are beneficially narrower than about 10 microns (preferably close to 1 micron) and extend deeper than about 5 microns into the sapphire substrate 122. The trenches 130 assist a subsequent chip separation process.

(13) Because of the hardness of sapphire and GaN, the trenches 130 are beneficially formed in the structure of FIG. 3 using reactive ion etching, preferably inductively coupled plasma reactive ion etching (ICP RIE). Forming trenches using ICP RIE has two main steps: forming scribe lines and etching. Scribe lines are formed on the structure of FIG. 3 using a photo-resist pattern in which areas of the sapphire substrate 122 where the trenches 130 are to be formed are exposed. The exposed areas are the scribe lines, while all other areas are covered by photo-resist. The photo-resist pattern is beneficially fabricated from a relatively hard photo-resist material that withstands intense plasma. For example, the photo-resist could be AZ 9260, while the developer used to develop the photo-resist to form the scribe lines could be AZ MIF 500.

(14) In the illustrated example, the photo-resist is beneficially spin coated to a thickness of about 10 microns. However, in general, the photo-resist thickness should be about the same as the thickness of the vertical topology GaN-based LED layer structure plus the etch depth into the sapphire substrate 122. This helps ensure that the photo-resist mask remains intact during etching. Because it is difficult to form a thick photo-resist coating in one step, the photo-resist can be applied in two coats, each about 5 microns thick. The first photo-resist coat is spin coated on and then soft baked, for example, at 90 F. for about 15 minutes. Then, the second photo-resist coat is applied in a similar manner, but is soft baked, for example, at 110 F. for about 8 minutes. The photo-resist coating is then patterned to form the scribe lines. This is beneficially performed using lithographic techniques and development. Development takes a relatively long time because of the thickness of the photo-resist coating. After development, the photo-resist pattern is hard baked, for example, at about 80 F. for about 30 minutes. Then, the hard baked photo-resist is beneficially dipped in a MCB (Metal Chlorobenzene) treatment for about 3.5 minutes. Such dipping further hardens the photo-resist.

(15) After the scribe lines are defined, the structure of FIG. 3 is etched. Referring now to FIG. 5, the ICP RIE etch process is performed by placing the structure of FIG. 3 on a bottom electrode 132 in a RIE chamber 134 having an insulating window 136 (beneficially a 1 cm-thick quartz window). The bottom electrode 132 is connected to a bias voltage supply 138 that biases the structure of FIG. 3 to enable etching. The bias voltage supply 138 beneficially supplies 13.56 MHz RF power and a DC-bias voltage. The distance from the insulating window 136 to the bottom electrode 132 is beneficially about 6.5 cm. A gas mixture of Cl.sub.2 and BCl.sub.2, and possibly Ar, is injected into the RIE chamber 134 through a reactive gas port 140. Furthermore, electrons are injected into the chamber via a port 142. A 2.5-turn or so spiral Cu coil 144 is located above the insulating window 136. Radio frequency (RF) power at 13.56 MHz is applied to the coil 144 from an RF source 146. It should be noted that magnetic fields are produced at right angles to the insulating window 136 by the RF power.

(16) Still referring to FIG. 5, electrons present in the electromagnetic field produced by the coil 144 collide with neutral particles of the injected gases, resulting in the formation of ions and neutrals, which produce plasma. Ions in the plasma are accelerated toward the structure of FIG. 3 by the bias voltage applied by the bias voltage supply 138 to the bottom electrode 132. The accelerated ions pass through the scribe lines, forming the etch channels 130 (see FIG. 4).

(17) Referring now to FIG. 6, after the trenches 130 are formed, thin p-contacts 150 are formed on the individual LED semiconductor structures of the GaN-based LED layer structure. Those contacts 150 are beneficially comprised of Pt/Au, Pd/Au, Ru/Au, Ni/Au, Cr/Au, or of indium tin oxide (ITO)/Au and are less than 10 nm. For instance, the thickness of the thin p-contacts 150 can be less than the thickness of p-GaN contact layer 128, which can be 0.05 m. Also, as shown in FIG. 6, a width of the thin p-contacts 150 can be equal to or smaller than a width of the GaN-based LED layer structure, in which a width direction is perpendicular to a thickness direction of the GaN-based LED layer structure from the bottom surface thereof to the top surface thereof. Such contacts can be formed using a vacuum evaporator (electron beam, thermal, sputter), followed by thermal annealing at an intermediate temperature (approximately 300-700 C.).

(18) As shown in FIG. 7, after the contacts 150 are formed, the trenches 130 are filled with an easily removed material (beneficially a photo-resist) to form posts 154.

(19) Referring now to FIG. 8, after the posts 154 are formed, a metal support layer 156 approximately 50 m is formed over the posts 154 and over the p-contacts 150. For instance, a ratio of the thickness of the GaN-based LED layer structure (e.g., 5 m) to a thickness of a support structure, which can include metal support layer 156 and the metallic coating layer 157, can be less than 0.1 The posts 154 prevent the metal that forms the metal support layer 156 from entering into the trenches. The metal support layer 156 is beneficially comprised of a metal having good electrical and thermal conductivity and that is easily formed, such as by electroplating, by electro-less plating, by CVD, or by sputtering. Before electroplating or electro-less plating, it is beneficial to coat the surface with a suitable metal 157, such as by sputtering. For example, the metal support layer 156 can be Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, or Al. Alternatively, the metal support layer 156 can be comprised of a metal-containing material such as titanium nitride.

(20) Turning now to FIG. 9, the sapphire substrate 122 is then removed from the remainder of the structure using light 158 from an excimer layer (having a wavelength less than 350 nanometers), while the sapphire substrate is biased away from the remainder of the structure (such as by use of vacuum chucks). The laser beam 158 passes through the sapphire substrate 122, causing localized heating at the junction of the sapphire substrate 122 and the n-GaN buffer layer 124. That heat decomposes the GaN at the interface of the sapphire substrate, which, together with the bias, causes the sapphire substrate 122 to separate, reference FIG. 10. It is beneficial to hold the other side of the structure with a vacuum chuck during laser lift off. This enable easy application of a separation bias.

(21) Laser lift off processes are described in U.S. Pat. No. 6,071,795 to Cheung et al., entitled, Separation of Thin Films From Transparent Substrates By Selective Optical Processing, issued on Jun. 6, 2000, and in Kelly et al. Optical process for liftoff of group III-nitride films, Physica Status Solidi (a) vol. 159, 1997, pp. R3-R4. Beneficially, the metal support layer 156 fully supports the individual LED semiconductor structures during and after separation of the sapphire substrate.

(22) Still referring to FIG. 10, the posts 154 are then removed, leaving the trenches 130 behind.

(23) Turning now to FIG. 11 the structure of FIG. 10 is inverted. Then, the side opposite the metal support layer 156 is cleaned with HCl to remove Ga droplets (laser beam 158 heating separates GaN into Ga+N). After cleaning, ICP RIE polishing (using Cl.sub.2 and/or Cl.sub.2+BCl.sub.3) is performed to smooth the exposed surface (which is rough due to the separation of the sapphire substrate). Polishing produces an atomically flat surface of pure n-GaN on the n-GaN buffer layer 124.

(24) Turning now to FIG. 12, n-type ohmic contacts 160 are formed on the n-GaN buffer layer 124 using normal semiconductor-processing techniques. Beneficially, the n-type ohmic contacts 160 are comprised of Ti/Al-related materials.

(25) Turning now to FIG. 13, to protect the semiconductor layers from subsequent processing, a passivation layer 162 is formed on the n-type ohmic contacts 160 and in the trenches 130. For instance, passivation layer 162 can extend from a support structure, which can include metal support layer 156 and the metallic coating layer 157, to the top surface of the GaN-based LED layer structure via the side surface of the GaN-based LED layer structure. In other words, as shown in FIG. 13, passivation layer 162 can include a first portion being directly in contact with a top surface of the support structure (e.g., 156 and 157), a second portion disposed on the side surface of the GaN-based LED layer structure, and a third portion disposed on the top surface of the GaN-based LED layer structure. Also, a length of the first portion of passivation layer 162 can be shorter than both a length of the second portion of passivation layer 126 and a length of the third portion of passivation layer 126. Electrical insulation comprised of SiO2 or Si3N4 are suitable passivation layer materials. Additionally, as shown, the passivation layer 162 is patterned to expose top surface portions of the n-type ohmic contacts 160. For instance, passivation layer 126 can include openings such that a top surface of the n-type ohmic contacts 160 is not covered by passivation layer 126.

(26) Turning now to FIG. 14, after the passivation layer 162 is formed, metal pads 164 are formed on the n-type ohmic contacts 160. As shown in FIG. 14, the metal pads 164 extend over portions of the passivation layer 162. For instance, passivation layer 162 is disposed on the top surface of the n-type ohmic contacts 160, and the openings of passivation layer 162 can be covered by metal pads 164 such that passivation layer 162 is disposed between the n-type ohmic contacts 160 and the metal pad 164. Also, as shown in FIG. 14, passivation layer 162 can include a fourth portion disposed on a side of the n-type ohmic contacts 160, and a fifth portion disposed on the top surface of the n-type ohmic contacts 160, in which a length of the fourth portion can be larger than the fifth portion. The metal pads 164 are beneficially comprised of Cr and Au.

(27) After the metal pads 164 are formed, individual devices can be diced out. Referring now to FIG. 15, dicing is beneficially accomplished using photolithographic techniques to etch through the metal support layer 156 to the bottom of the passivation layer 162 (at the bottom of the trenches 130) and by removal of the passivation layer 162. Alternatively, sawing can be used. In practice, it is probably better to perform sawing at less than about 0 C. The result is a plurality of vertical topology GaN LEDs 199 on conductive substrates.

(28) The foregoing has described forming trenches 130 before laser lift off of the sapphire substrate 122. However, this is not required. The sapphire substrate 122 could be removed first, and then trenches 130 can be formed.

(29) The embodiments and examples set forth herein are presented to best explain the present invention and its practical application and to thereby enable those skilled in the art to make and utilize the invention. Those skilled in the art, however, will recognize that the foregoing description and examples have been presented for the purpose of illustration and example only. Other variations and modifications of the present invention will be apparent to those of skill in the art, and it is the intent of the appended claims that such variations and modifications be covered. The description as set forth is not intended to be exhaustive or to limit the scope of the invention. Many modifications and variations are possible in light of the above teaching without departing from the spirit and scope of the following claims. It is contemplated that the use of the present invention can involve components having different characteristics. It is intended that the scope of the present invention be defined by the claims appended hereto, giving full cognizance to equivalents in all respects.