Abstract
A quantum circuit for Daubechies-6 wavelet transform includes: a B quantum circuit configured to receive a first part of n-dimensional data and generate a first intermediate result; a Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit configured to receive a second part of the n-dimensional data, and the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit coupled to the B quantum circuit to receive the first intermediate result, and the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit generating a second intermediate result corresponding to the first intermediate result and a first result corresponding to the second part; and an A quantum circuit coupled to the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit to receive the second intermediate result and to generate a second result according to the second intermediate result. The present disclosure further discloses a manufacturing method of a quantum circuit for Daubechies-6 wavelet transform and a quantum circuit for Daubechies-6 wavelet inverse transform corresponding to the aforementioned quantum circuit for Daubechies-6 wavelet transform.
Claims
1. A quantum circuit for Daubechies-6 (D6) wavelet transform comprising: a B quantum circuit configured to receive a first part of n-dimensional data and generate a first intermediate result, wherein the first part comprises data of (n−1)th dimension and data of nth dimension of the n-dimensional data; a Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit configured to receive a second part of the n-dimensional data, the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit coupled to the B quantum circuit to receive the first intermediate result, and the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit generating a second intermediate result corresponding to the first intermediate result and a first result corresponding to the second part, wherein the second part comprises data of 1st dimension to data of (n−2)th dimension of the n-dimensional data; and an A quantum circuit coupled to the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit to receive the second intermediate result and to generate a second result according to the second intermediate result; wherein the B quantum circuit and the A quantum circuit are configured to implement two 4×4 parameter matrixes, the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit is configured to implement a dot product of the two same 2.sup.n×2.sup.n unitary matrixes configured to transfer a state amplitude, the n is positive integer and a set of the first result and the second result serves an output of the quantum circuit for Daubechies-6 (D6) wavelet transform.
2. The quantum circuit for Daubechies-6 (D6) wavelet transform according to claim 1, wherein the A quantum circuit implement (U.sub.A1.Math.U.sub.A2).Math.M.Math.(A.sub.a1⊕A.sub.a2).Math.M.sup.†.Math.(V.sub.A1.Math.V.sub.A2), and the B quantum circuit implement (U.sub.B1.Math.U.sub.B2).Math.M.Math.(B.sub.b1⊕B.sub.b2).Math.M.sup.†.Math.(V.sub.B1.Math.V.sub.B2) the A.sub.a1 is the A.sub.a2 is the U.sub.A1 is the U.sub.A2 is the V.sub.A1 is the V.sub.A2 is the B.sub.b1 is the B.sub.b2 is the U.sub.B1 is the U.sub.B2 is the V.sub.B1 is the V.sub.B2 is a matrix form of the M is a matrix form of the M.sup.† is a conjugate transpose matrix of the maatrix form of the M, the 2.sup.n×2.sup.n unitary matris is
3. A quantum circuit for Daubechies-6 (D6) wavelet inverse transform comprising: a (A).sup.−1 quantum circuit configured to receive a first part of n-dimensional data and generate a first intermediate result, wherein the first part comprises data of (n−1)th dimension and data of nth dimension of the n-dimensional data; a (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit configured to receive a second part of the n-dimensional data, the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit coupled to the (A).sup.−1 quantum circuit to receive the first intermediate result, and the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit generating a second intermediate result corresponding to the first intermediate result and a first result corresponding to the second part, wherein the second part comprises data of 1st dimension to data of (n−2)th dimension of the n-dimensional data; and a (B).sup.−1 quantum circuit coupled to the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit to receive the second intermediate result and to generate a second result according to the second intermediate result; wherein the (A).sup.−1 quantum circuit and the (B).sup.−1 quantum circuit are configured to implement inverse matrixes of two 4×4 parameter matrixes, the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit is configured to implement a dot product of inverse matrixes of the two same 2.sup.n×2.sup.n unitary matrixes and the two same 2.sup.n×2.sup.n unitary matrixes configured to transfer a state amplitude, the n is positive integer and a set of the first result and the second result serves an output of the quantum circuit for Daubechies-6 (D6) wavelet inverse transform.
4. The quantum circuit for Daubechies-6 (D6) wavelet inverse transform according to claim 3, wherein the (A).sup.−1 quantum circuit achieves ((V.sub.A1).sup.−1.Math.(V.sub.A2).sup.−1).Math.M .Math.((A.sub.a1).sup.−1⊕(A.sub.a2).sup.−1).Math.M.sup.†.Math.((U.sub.A1).sup.−1.Math.(U.sub.A2).sup.−1), the (B).sup.−1 quantum circuit achieves ((V.sub.B1).sup.−1.Math.(V.sub.B2).sup.−1).Math.M.Math.((B.sub.b1).sup.−1⊕(B.sub.b2).sup.−1).Math.M.sup.†.Math.((U.sub.B1).sup.−1.Math.(U.sub.B2).sup.−1), the A.sub.a1 is the A.sub.a2 is the U.sub.A1 is the U.sub.A2 is the V.sub.A1 is the V.sub.A2 is the B.sub.b1 is the B.sub.b2 is the U.sub.B1 is the U.sub.B2 is the V.sub.B1 is the V.sub.B2 is Ph(−0.874471π). a matrix form of the M is a matrix form of the M.sup.† is a comjugate transpose matrix of the matrix form of the M, the b 2.sup.n×2.sup.n unitary matrix is
5. A manufacturing method of a quantum circuit for Daubechies-6 (D6) wavelet transform comprising: decomposing a matrix D.sub.2.sub.n.sup.(6) of Daubechies-6 (D6) wavelet into (I.sub.2.sub.n−2.Math.A).Math.Q.sub.2.sub.n.Math.Q.sub.2.sub.n.Math.(I.sub.2.sub.n−2.Math.B); decomposing a parameter matrix A into (U.sub.A1.Math.U.sub.A2).Math.M.Math.(A.sub.a1⊕A.sub.a2).Math.M.sup.†.Math.(V.sub.A1.Math.V.sub.A2), and decomposing a parameter matrix B into (U.sub.B1.Math.U.sub.B2).Math.M.Math.(B.sub.b1⊕B.sub.b2).Math.M.sup.†.Math.(V.sub.B1.Math.V.sub.B2); and constituting the quantum circuit for Daubechies-6 (D6) wavelet transform by a plurality of basic 1-bit logic gates, a controlled-NOT gate and a controlled-U gate based on (I.sub.2.sub.n−2.Math.A).Math.Q.sub.2.sub.n.Math.Q.sub.2.sub.n.Math.(I.sub.2.sub.n−2.Math.B), (U.sub.A1.Math.U.sub.A2).Math.M.Math.(A.sub.a1⊕A.sub.a2).Math.M.sup.†.Math.(V.sub.A1.Math.V.sub.A2) and (U.sub.B1.Math.U.sub.B2).Math.M.Math.(B.sub.b1⊕B.sub.b2).Math.M.sup.†.Math.(V.sub.B1.Math.V.sub.B2), wherein the Q.sub.2.sub.n is a 2.sup.n×2.sup.n unitary matrix configured to transfer a state amplitude, the M is the M.sup.† is a conjugate transpose matrix of the M, the A.sub.a1 is the A.sub.a2 is he U.sub.A1 is the U.sub.A2 is the V.sub.A1 is the V.sub.A2 is the B.sub.b1 is the B.sub.b2 is the U.sub.B1 is the U.sub.B2 is the V.sub.B1 is the V.sub.B2 is
6. The manufacturing method of the quantum circuit for Daubechies-6 (D6) wavelet transform according to claim 5, wherein the 2.sup.n×2.sup.n unitary matrix is
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1A to FIG. 1I illustrate element symbol diagrams of basic 1-bit logic gates being usable for the quantum circuit for Daubechies-6 (D6) wavelet transform according to one embodiment of the present disclosure.
[0022] FIG. 2A illustrates a schematic diagram of a controlled-NOT gate being usable for the quantum circuit for Daubechies-6 (D6) wavelet transform according to one embodiment of the present disclosure.
[0023] FIG. 2B illustrates a schematic diagram of a controlled-U gate being usable for the quantum circuit for Daubechies-6 (D6) wavelet transform according to one embodiment of the present disclosure.
[0024] FIG. 3A illustrates a circuit diagram of the quantum circuit for Daubechies-6 (D6) wavelet transform according to one embodiment of the present disclosure.
[0025] FIG. 3B illustrates a circuit diagram of the A quantum circuit in the quantum circuit for Daubechies-6 (D6) wavelet transform according to the embodiment illustrated in FIG. 3A.
[0026] FIG. 3C illustrates a circuit diagram of the B quantum circuit in the quantum circuit for Daubechies-6 (D6) wavelet transform according to the embodiment illustrated in FIG. 3A.
[0027] FIG. 3D illustrates a circuit diagram of the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit in the quantum circuit for Daubechies-6 (D6) wavelet transform according to the embodiment illustrated in FIG. 3A.
[0028] FIG. 4A illustrates a circuit diagram of the M quantum circuit in the quantum circuit for Daubechies-6 (D6) wavelet transform according to the embodiment illustrated in FIG. 3B or FIG. 3C.
[0029] FIG. 4B illustrates a circuit diagram of the Mt quantum circuit in the quantum circuit for Daubechies-6 (D6) wavelet transform according to the embodiment illustrated in FIG. 3B or FIG. 3C.
[0030] FIG. 4C to FIG. 4H illustrate circuit diagrams of A.sub.a1, A.sub.a2, U.sub.A1, U.sub.A2, V.sub.A1, V.sub.A2 in the quantum circuit for Daubechies-6 (D6) wavelet transform according to the embodiment illustrated in FIG. 3B.
[0031] FIG. 4I to FIG. 4N illustrate circuit diagrams of B.sub.b1, B.sub.b2, U.sub.B1, U.sub.B2, V.sub.B1, V.sub.B2 in the quantum circuit for Daubechies-6 (D6) wavelet transform according to the embodiment illustrated in FIG. 3C.
[0032] FIG. 5A illustrates a circuit diagram of the quantum circuit for Daubechies-6 (D6) wavelet inverse transform according to one embodiment of the present disclosure.
[0033] FIG. 5B illustrates a circuit diagram of the (A).sup.−1 quantum circuit in the quantum circuit for Daubechies-6 (D6) wavelet inverse transform according to the embodiment illustrated in FIG. 5A.
[0034] FIG. 5C illustrates a circuit diagram of the (B).sup.−1 quantum circuit in the quantum circuit for Daubechies-6 (D6) wavelet inverse transform according to the embodiment illustrated in FIG. 5A.
[0035] FIG. SD illustrates a circuit diagram of the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit in the quantum circuit for Daubechies-6 (D6) wavelet inverse transform according to the embodiment illustrated in FIG. 5A.
[0036] FIG. 6 illustrates a flowchart of the manufacturing method of the quantum circuit for Daubechies-6 (D6) wavelet transform according to one embodiment of the present disclosure.
DETAILED DESCRIPTION
[0037] The present disclosure sets forth the quantum circuit for Daubechies-6 (D6) wavelet transform and inverse transform based on the Daubechies-6 (D6) wavelet matrix. The quantum circuit indicates to include a combination of basic 1-bit logic gates (usually denoted as a 2×2 matrix), a controlled-NOT gate and a controlled-U gate, but is not limited thereto. In order to explain the aforementioned basic 1-bit logic gates, the controlled-NOT gate and the controlled-U gate to more clearly explain the quantum circuit for Daubechies-6 (D6) wavelet transform and inverse transform according to one embodiment of the present disclosure, please refer to FIG. 1A to FIG. 1I, FIG. 2A and FIG. 2B. Specifically, FIG. 1A to FIG. 1H sequentially illustrates an identity gate, a Hadamard gate, a Pauli-X gate, a Pauli-Y gate, a Pauli-Z gate, a Rotation-X gate, a Rotation-Y gate, a Rotation-Z gate and a Phase-Shift gate each of which is a basic 1-bit logic gate. Besides, FIG. 2A illustrates the controlled-NOT gate and FIG. 2B illustrates the controlled-U gate.
[0038] The Daubechies-6 (D6) wavelet matrix D.sub.2.sub.n.sup.(6) in the present embodiment is usually expressed as:
[00014]
wherein the parameters c.sub.0 to c.sub.5 are as follows:
[00015]
and
[00016]
[0039] Based on matrix calculation, the aforementioned matrix D.sub.2.sub.n.sup.(6) may be further decomposed into: (I.sub.2.sub.n−2.Math.A).Math.Q.sub.2.sub.n.Math.Q.sub.2.sub.n.Math.(I.sub.2.sub.n−2.Math.B). Thereby, the dimension of the Daubechies-6 (D6) wavelet matrix with the high dimension and complex coefficient relationship may be decreased to generate two parameter matrixes A, B merely involving 4×4 matrix complexity to facilitate the achievement of the quantum circuit for Daubechies-6 (D6) wavelet transform. In the aforementioned formula, I.sub.2.sub.n−2 is a unit matrix of 2.sup.n−2×2.sup.n−2; .Math. is an operator of direct product; Q.sub.2.sub.n is a 2.sup.n×2.sup.n unitary matrix for transferring a state amplitude as follows:
[00017]
and the parameter matrix A and the parameter matrix B are obtained as follows by the way of simultaneous equations:
[00018]
and
[00019]
[0040] Besides, the aforementioned parameter matrix A and the parameter matrix B may be further decomposed as: A=(U.sub.A1.Math.U.sub.A2).Math.M.Math.(A.sub.a1⊕A.sub.a2).Math.M.sup.†.Math.(V.sub.A1.Math.V.sub.A2); B=(U.sub.B1.Math.U.sub.B2).Math.M.Math.(B.sub.b1⊕B.sub.b2).Math.M.sup.†.Math.(V.sub.B1.Math.V.sub.B2), so as to apply two parameter matrixes to the quantum circuit. In the equations associated with the parameter matrix A and the parameter matrix B, ⊕ is an operator of direct sum; U.sub.A1, U.sub.A2, A.sub.a1, A.sub.a2, V.sub.A1, V.sub.A2, U.sub.B1, U.sub.B2, B.sub.b1, B.sub.b2, V.sub.B1 and V.sub.B2 are all 2×2 unitary matrixes to provide 1-bit logic gate to apply to the quantum circuit; M is a magic basis, and M.sup.† is a conjugate transpose matrix of the magic basis, that is, M.sup.†=(M).sup.−1, wherein the matrix form of the M and the M.sup.† is expressed as follows:
[00020]
[0041] According to the decomposed Daubechies-6 (D6) wavelet matrix D.sub.2.sub.n.sup.(6) (i.e., the aforementioned (I.sub.2.sub.n−2.Math.A).Math.Q.sub.2.sub.n.Math.Q.sub.2.sub.n.Math.(I.sub.2.sub.n−2.Math.B)), the quantum circuit 1 for Daubechies-6 (D6) wavelet transform in the present embodiment may be obtained as illustrated in FIG. 3A. In FIG. 3A, the A quantum circuit 11 configured to implement the parameter matrix A in one embodiment of the present disclosure may be illustrated in FIG. 3B, the B quantum circuit 12 configured to implement the parameter matrix B may be illustrated in FIG. 3C, the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit 13 configured to implement a dot product of the unitary matrix Q.sub.2.sub.n, and the unitary matrix Q.sub.2.sub.n (i.e., Q.sub.2.sub.n.Math.Q.sub.2.sub.n) may be illustrated in FIG. 3D. In the quantum circuit 1 for Daubechies-6 (D6) wavelet transform of the present embodiment, the B quantum circuit 12 is coupled to one side of the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit 13 and the A quantum circuit 11 is coupled to the other side of the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit 13. In operation, the quantum circuit 1 for Daubechies-6 (D6) wavelet transform of this embodiment is configured to receive n-dimensional data, wherein each dimension includes a 2×1 vector. In the aforementioned received n-dimensional data, the data of the 1st dimension to the data of the (n−2)th dimension which may correspond to j.sub.0 as illustrated in FIG. 3A to j.sub.n−3 not illustrated in FIG. 3A are input into the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit 13, and after the data of the (n−1)th dimension and the data of the nth dimension which may correspond to j.sub.n−2 and j.sub.n−1 as illustrated in FIG. 3A are input into the B quantum circuit 12, the operation result (denoted as the first intermediate result hereinafter) of the B quantum circuit 12 is input to the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit 13. Afterwards, the first operation result to the (n−2)th operation result (called the first result) generated by the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit 13 serve one part of output of the quantum circuit 1 for Daubechies-6 (D6) wavelet transform; and the (n−1)th operation result to the nth operation result (denoted as the second intermediate result hereinafter) corresponding to the first intermediate result generated by the Q.sub.2.sub.n.Math.Q.sub.2.sub.n quantum circuit 13 are input to the A quantum circuit 11. The operation result (called the second result) generated by the A quantum circuit 11 according to the second intermediate result serves as the other part of output of the quantum circuit 1 for Daubechies-6 (D6) wavelet transform.
[0042] Specifically, a M quantum circuit M1 of the magic basis M in the A quantum circuit 11 is illustrated in FIG. 4A and a M.sup.† quantum circuit M2 of the conjugate transpose matrix M.sup.† of the magic basis M is illustrated in FIG. 4B. A.sub.a1, A.sub.a2, U.sub.A1, U.sub.A2, U.sub.A2, V.sub.A1, V.sub.A2 in the A quantum circuit 11 are respectively expressed as:
[00021]
and A.sub.a1, A.sub.a2, U.sub.A1, U.sub.A2, V.sub.A1, V.sub.A2 in the A quantum circuit 11 may be respectively implemented by the basic 1-bit logic gates as illustrated in FIG. 4C to FIG. 4H. Similarly, B.sub.b1, B.sub.b2, U.sub.B1, U.sub.B2, V.sub.B1, V.sub.B2 in the B quantum circuit 12 are respectively expressed as:
[00022]
and B.sub.b1, B.sub.b2, U.sub.B1, U.sub.B2, V.sub.B1, V.sub.B2 in the B quantum circuit 12 may each be implemented by the basic 1-bit logic gates as illustrated in FIG. 4I to FIG. 4N. In the present embodiment, in each of input values (variables) of functions of the aforementioned basic 1-bit logic gates, each of the coefficients of π is expressed by five digits after decimal point under the situation in which the coefficients of π are irrational numbers, but the present disclosure is not limited thereto. In other words, the precision of these coefficients of π is adjustable as long as the quantum circuit with enough accuracy can be achieved. For example, under the situation in which five digits after decimal point of these coefficients of π have met the requirement, the sixth digit after decimal point of these coefficients of π may be regarded as any one of 0 to 9, and each of the other digits after decimal point of these coefficients of π is any one of 0 to 9. By the aforementioned method, the quantum circuit for Daubechies-6 (D6) wavelet transform may be implemented by decreasing the dimension to obtain the quantum circuit with much higher resolutions, thereby meeting the requirement of high information complexity in the current information field (particularly, the aspects of image processing and signal processing).
[0043] In another embodiment of the present disclosure, the quantum circuit 2 for Daubechies-6 (D6) wavelet inverse transform is further implemented and the quantum circuit 2 for Daubechies-6 (D6) wavelet inverse transform and the quantum circuit 1 for Daubechies-6 (D6) wavelet transform are paired. In the present embodiment, an inverse matrix (D.sub.2.sub.n.sup.(6).sup.−1 of the Daubechies-6 (D6) wavelet matrix D.sub.2.sub.n.sup.(6) may be decomposed into (I.sub.2.sub.n−2.Math.(B).sup.−1) (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1.Math.(I.sub.2.sub.n−2.Math.(A).sup.−1) and the quantum circuit 2 for Daubechies-6 (D6) wavelet inverse transform in the present embodiment may be illustrated in FIG. 5A. In this quantum circuit, the inverse matrix (A).sup.−1 of the parameter matrix A may be expressed as ((V.sub.A1).sup.−1.Math.(V.sub.A2).sup.−1).Math.M.Math.((A.sub.a1).sup.−1⊕(A.sub.a2).sup.−1).Math.M.sup.†.Math.((U.sub.A1).sup.−1.Math.(U.sub.A2).sup.−1), and a (A).sup.−1 quantum circuit 21 implementing the inverse matrix (A).sup.−1 is illustrated in FIG. 5B; similarly, the inverse matrix (B).sup.−1 of the parameter matrix B may be expressed as ((V.sub.B1).sup.−1.Math.(V.sub.B2).sup.−1).Math.M.Math.((B.sub.b1).sup.−1⊕(B.sub.b2).sup.−1).Math.M.sup.†.Math.((U.sub.B1).sup.−1.Math.(U.sub.B2).sup.−1), and a (B).sup.−1 quantum circuit 22 implementing the inverse matrix (B).sup.−1 is illustrated in FIG. 5C; an (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit 23 implementing the dot product (i.e., (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1) of the inverse matrix (Q.sub.2.sub.n).sup.−1 of the unitary matrix Q.sub.2.sub.n and the inverse matrix (Q.sub.2.sub.n).sup.−1 of the unitary matrix Q.sub.2.sub.n is illustrated in FIG. 5D.
[0044] Please refer to FIG. 5A, in contrast to the aforementioned quantum circuit 1 for Daubechies-6 (D6) wavelet transform, in the quantum circuit 2 for Daubechies-6 (D6) wavelet inverse transform in the present embodiment, the (A).sup.−1 quantum circuit 21 is coupled to one side of the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit 23 and the (B).sup.−1 quantum circuit 22 is coupled to the other side of the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit 23. In operation, the quantum circuit 2 for Daubechies-6 (D6) wavelet inverse transform of this embodiment is configured to receive n-dimensional data, wherein each dimension includes a 2×1 vector. In the aforementioned received n-dimensional data, the data of the 1st dimension to the data of the (n−2)th dimension (it may correspond to j.sub.0 as illustrated in FIG. 5A to j.sub.n−3 not illustrated in FIG. 5A) are input to the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit 23, and after the data of the (n−1)th dimension and the data of the nth dimension (it may correspond to j.sub.n−2 and as illustrated in FIG. 5A) are input to the (A).sup.−1 quantum circuit 21, the operation result of the (A).sup.−1 quantum circuit 21 is input to the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit 23. Afterwards, the first operation result to the (n−2)th operation result generated by the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit 23 serve as one part of output of the quantum circuit 2 for Daubechies-6 (D6) wavelet inverse transform; and the (n−1)th operation result to the nth operation result generated by the (Q.sub.2.sub.n).sup.−1.Math.(Q.sub.2.sub.n).sup.−1 quantum circuit 23 are input to the (B).sup.−1 quantum circuit 22, and the operation result generated by the (B).sup.−1 quantum circuit 22 serves as the other part of output of the quantum circuit 1 for Daubechies-6 (D6) wavelet transform. Besides, U.sub.A1, U.sub.A2, A.sub.a1, A.sub.a2, V.sub.A1, V.sub.A2, U.sub.B1, U.sub.B2, B.sub.b1, B.sub.b2, V.sub.B1, and V.sub.B2 may be referred to obtain inverse matrixes (U.sub.A1).sup.−1, (U.sub.A2).sup.−1, (A.sub.a1).sup.−1, (A.sub.a2).sup.−1, (V.sub.A1).sup.−1, (V.sub.A2).sup.−1, (U.sub.B1).sup.−1, (U.sub.B2).sup.−1, (B.sub.b1).sup.−1, (B.sub.b2).sup.−1, (V.sub.B1).sup.−1 and (V.sub.B2).sup.−1 of the U.sub.A1, U.sub.A2, A.sub.a1, A.sub.a2, V.sub.A1, V.sub.A2, U.sub.B1, U.sub.B2, B.sub.b1, B.sub.b2, V.sub.B1 and V.sub.B2 , and they are understandable.
[0045] Please refer to FIG. 6, in order to generate the aforementioned quantum circuit 1 for Daubechies-6 (D6) wavelet transform, the following steps may be performed by a computing device in collaboration with logic gate processing to implement a manufacturing method of the quantum circuit 1 for Daubechies-6 (D6) wavelet transform. In step S1, a matrix D.sub.2.sub.n.sup.(6) of Daubechies-6 (D6) wavelet transform is decomposed into (I.sub.2.sub.n−2.Math.A) Q.sub.2.sub.n.Math.Q.sub.2.sub.n.Math.(I.sub.2.sub.n−2⊕B); in step S2, the parameter matrix A is decomposed into (U.sub.A.Math.U.sub.A2).Math.M.Math.(A.sub.a1⊕A.sub.a2).Math.M.sup.†.Math.(V.sub.A1.Math.V.sub.A2) and the parameter matrix B is decomposed into (U.sub.B1.Math.U.sub.B2).Math.M.Math.(B.sub.b1⊕B.sub.b2).Math.M.sup.†.Math.(V.sub.B1.Math.V.sub.B2); finally, in step S3, the quantum circuit 1 for Daubechies-6 (D6) wavelet transform is constituted by the basic 1-bit logic gates, the controlled-NOT gate and the controlled-U gate based on the aforementioned (I.sub.2.sub.n−2.Math.A).Math.Q.sub.2.sub.n.Math.Q.sub.2.sub.n.Math.(I.sub.2.sub.n−2.Math.B), (U.sub.A1.Math.U.sub.A2).Math.M.Math.(A.sub.a1⊕A.sub.a2).Math.M.sup.†.Math.(V.sub.A1.Math.V.sub.A2) and (U.sub.B1.Math.U.sub.B2).Math.M.Math.(B.sub.b1⊕B.sub.b2).Math.M.sup.†.Math.(V.sub.B1.Math.V.sub.B2). The basic 1-bit logic gates may include the Hadamard gate, the Pauli-X gate, the Pauli-Z gate, the Rotation-Y gate, the Rotation-Z gate and the Phase-Shift gates.
[0046] By utilizing the aforementioned parameter matrix A and the parameter matrix B to simplify the matrix D.sub.2.sub.n.sup.(6) and the inverse matrix (D.sub.2.sub.n.sup.(6)).sup.−1 of Daubechies-6 (D6) wavelet transform for obtaining the quantum circuit for Daubechies-6 (D6) wavelet transform, the quantum circuit for Daubechies-6 (D6) wavelet transform may be merely implemented by the basic 1-bit logic gates, the controlled-NOT gate and the controlled-U gate. Moreover, the quantum circuit for Daubechies-6 (D6) wavelet transform/inverse transform may be further applied to the related fields about handling the high information complexity (particularly, aspects of image processing and signal processing) and the entire volume of the circuit is reduced to overcome the problem that the number of transistors in the conventional silicon chip computer daily increases.