Superconducting qubit capacitance and frequency of operation tuning

Abstract

A method for adjusting a resonance frequency of a qubit in a quantum mechanical device includes providing a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit comprising capacitor pads; and removing substrate material from the backside of the substrate at an area opposite the at least one qubit to alter a capacitance around the at least one qubit so as to adjust a resonance frequency of the at least one qubit.

Claims

1. A method for adjusting a resonance frequency of a qubit in a quantum mechanical device, comprising: providing a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit comprising a first capacitor pad and a second capacitor pad having a gap reserved therebetween; and removing substrate material from the backside of the substrate at least at an area below said gap to form a trench wherein a base of the trench is wider than the gap and extends under an entirety of the gap to alter a capacitance around the at least one qubit so as to adjust a resonance frequency of the at least one qubit.

2. The method according to claim 1, wherein removing the substrate material from the backside of the substrate at the area below said gap comprises chemically etching the backside of the substrate selectively using a chemical etchant selected depending on the substrate material.

3. The method according to claim 2, wherein prior to chemically etching the backside of the substrate, forming an initial cavity in the backside of the substrate in a vicinity of the at least one qubit below said gap by mechanically removing material from the backside of the substrate and then chemically etching the backside of the substrate at the formed initial cavity.

4. The method according to claim 3, wherein forming the initial cavity in the backside of the substrate comprises defining faces of the initial cavity having one or more first crystal planes and one or more second crystal planes so that the chemical etchant preferentially etches the substrate material from said one or more first crystal planes while substantially not etching substrate material from said one or more second crystal planes to form an etched final cavity of the trench in the vicinity of the at least one qubit below said gap.

5. The method according to claim 4, wherein the substrate material is silicon and the one or more first crystal planes comprises a (111) plane and the one or more second crystal planes comprises a (100) plane.

6. The method according to claim 4, further comprising controlling an amount of the substrate material etched by selecting a size and shape of the initial cavity so that the etching of the substrate material stops when said one or more first crystal planes are substantially eliminated so as to form size self-limited etched final cavities.

7. The method according to claim 6, wherein controlling the amount of the substrate material etched comprises controlling an etching depth of the etched final cavities from the backside to the frontside.

8. The method according to claim 1, wherein removing the substrate material from the backside of the substrate at the area opposite the at least one qubit comprises applying an etch mask film to the backside of the substrate and etching selected areas at the backside of the substrate opposite the at least one qubit.

9. The method according to claim 8, further comprising: subsequent to applying the etch mask film to the backside of the substrate and prior to etching the selected areas at the backside of the substrate, forming one or more openings in the etch mask film at the selected areas.

10. The method according to claim 9, wherein forming the one or more openings in the etch mask film comprises forming the one or more openings using a focused ion beam etching, laser ablation, or mechanical milling, or any combination thereof.

11. The method according to claim 9, further comprising disposing a chemical etchant container to define an area around the one or more openings in the etch mask film and providing a wet or dry etching chemical to remove substrate material from the defined area at the one or more openings in the etch mask film to form one or more cavities at the backside of the substrate.

12. The method according to claim 1, wherein removing the substrate material from the backside of the substrate at the area opposite the at least one qubit comprises removing material using laser ablation, mechanical milling, focused ion beam, or any combination thereof.

13. The method according to claim 1, wherein removing substrate material from the backside of the substrate comprises removing the substrate material from the backside of the substrate at a plurality of areas opposite to a plurality of qubits to form a plurality of cavities on the backside of the substrate.

14. The method according to claim 13, wherein said removing the substrate material from the backside of the substrate at the plurality of areas opposite to the plurality of qubits comprises removing the substrate material from the backside of the substrate at the plurality of areas opposite to the plurality of qubits substantially simultaneously using a global substrate etch process.

15. The method according to claim 14, wherein said global substrate etch process comprises applying a chemical etch process.

16. The method according to claim 14, further comprising controlling an amount of material etched by selecting a size and shape of a formed initial cavity for each of the plurality of areas so that the removing of the substrate material stops at different times depending upon a selected geometry or shape of the initial cavity.

17. The method according to claim 16, wherein forming the initial cavity comprises defining faces of the initial cavity having one or more first crystal planes and one or more second crystal planes in the substrate material so that the substrate material is etched from said one or more first crystal planes while substantially not etched from said one or more second crystal planes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

(2) The present disclosure, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, will become more apparent upon consideration of the following description and the appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in the various figures. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the invention.

(3) FIG. 1A is a schematic cross-section view of a qubit device, according to an embodiment of the present invention;

(4) FIG. 1B is an Electron Microscope (EM) image of a Josephson junction, according to an embodiment of the present invention;

(5) FIG. 1C is an electronic circuit diagram of the qubit device coupled to electromagnetic signal lines via capacitors, according to an embodiment of the present invention;

(6) FIG. 2 is a contour map of a simulated two-dimensional electric field generated by capacitor pads connected to the Josephson junction, according to an embodiment of the present invention;

(7) FIGS. 3A-3C are contour maps of a distribution of the electric potential around the capacitor pads, according to embodiments of the present invention;

(8) FIG. 4 is a plot of capacitance (in %) versus etch depth (in μm) corresponding to an amount of substrate material removed at a backside of the substrate, according to an embodiment of the present invention;

(9) FIG. 5 depicts schematically the concept of varying the capacitance of a plurality of qubits by different amounts by changing the shape and/or depth of a trench or cavity at the backside of the substrate, according to an embodiment of the present invention;

(10) FIG. 6 is a flow chart of a method for adjusting a resonance frequency of qubits (e.g., qubit 1, qubit 2, qubit 3) in a quantum mechanical device, according to an embodiment of the present invention;

(11) FIG. 7 is a schematic representation of an initial cavity formed on the backside of the substrate leading to a self-limiting anisotropic etch, according to an embodiment of the invention;

(12) FIG. 8 depicts the backside of the substrate having a plurality of cavities, according to an embodiment of the present invention;

(13) FIG. 9 shows a three-dimensional representation of an etch mask film applied to the backside of the substrate, according to an embodiment of the present invention;

(14) FIG. 10 shows an example micrograph image of a qubit chip having four qubits (qubit 1, qubit 2, qubit 3 and qubit 4), for example, on a frontside of a substrate of the qubit chip, according to an embodiment of the present invention;

(15) FIG. 11 is a schematic representation of a qubit chip bonded to interposer substrate with bump bonds, according to an embodiment of the present disclosure;

(16) FIG. 12 is a schematic representation of the qubit chip bonded to an interposer substrate having one or more openings formed on the backside of the substrate, according to an embodiment of the present disclosure;

(17) FIG. 13A is a schematic three-dimensional representation of a container deposited on the backside of the substrate to define an area around the one or more openings in the etch film mask, according to an embodiment of the present invention;

(18) FIG. 13B is a schematic top view inside the container showing the relative position of the qubit chip and the one or more openings, according to an embodiment of the present invention; and

(19) FIG. 13C is a schematic view showing the position of the qubit chip relative to the container, the chip being positioned on the frontside of the substrate, according to an embodiment of the present invention.

DETAILED DESCRIPTION

(20) FIG. 1A is a schematic cross-section view of a qubit device 100, according to an embodiment of the present invention. As shown in FIG. 1A, the qubit device 100 comprises Josephson junction 102 and capacitor pads 104A and 104B. The Josephson junction 102 is connected to capacitor pads 104A and 104B. The capacitor pads 104A and 104B can be in turn capacitively coupled to electromagnetic (e.g., microwave or radiofrequency) signal lines 106A, 106B and 106C via capacitors 108A, 108B and 108C, for example.

(21) FIG. 1B is an Electron Microscope (EM) image of the Josephson junction, according to an embodiment of the present invention. In an embodiment, the Josephson junction can have a size of about 100 by 100 nm.sup.2. FIG. 1C is an electronic diagram of the qubit device 100 coupled to electromagnetic signal lines via capacitors 108A, 108B and 108C, according to an embodiment of the present invention. The Josephson junction 102 has an internal capacitance Cj and internal inductance L.sub.j (for example, L.sub.j is about 20 nH and C.sub.j is about 1 fF). However, as it must be appreciated, the internal inductance Lj and internal capacitance C.sub.j of the Josephson junction can have other values depending on the construction of the Josephson junction 102. In addition to the Josephson junction internal capacitance C.sub.j, the qubit 100 also has a coupling capacitance or signal capacitance C.sub.s due to capacitor pads 104A and 104B. In an embodiment, the capacitance C.sub.s (from capacitor pads 104A and 104B) can be about 60 if. However, the capacitance C.sub.s can also have other values depending on the size, geometry or shape of the capacitor pads 104A and 104B.

(22) In an embodiment, the resonance frequency is determined by the capacitive and resistive contributions from both the Josephson junction (including the internal capacitance C.sub.j and inductance L.sub.j) and the associated capacitor C.sub.s from the capacitor pads 104A and 104B. Therefore, for example, a first resonance frequency f.sub.01 of a qubit depends on the device capacitance and can be expressed mathematically by the following equation (1). The “0” in the index indicates the ground state of the Josephson junction 102 and “1” in the index indicates the first excited state of the Josephson junction 102, for example.

(23) $\begin{array}{cc}{f}_{01}=\frac{1}{h}\sqrt{8E_j{E}_c}& \left(1\right)\end{array}$
where energies E.sub.j and E.sub.c can be expressed by the following two equations (2) and (3).

(24) $\begin{array}{cc}{E}_c=\frac{e^2}{2C_{\Sigma }}& \left(2\right)\\ E_J=\frac{{\mathrm{hI}}_c}{2e}& \left(3\right)\end{array}$
Where e is the electron charge, h is the Planck constant, C.sub.Σ is the sum of all capacitances, and I.sub.c is the critical current (Ambegaokar-Baratoff), given by the following equation (4).

(25) $\begin{array}{cc}{I}_c=\frac{1}{R_n}\frac{\pi \Delta }{2e}& \left(4\right)\end{array}$
Where R.sub.n is the resistance of the Josephson Junction (JJ), and Δ is the superconducting energy gap, which is a material property that is independent of the material geometry, where the size of the superconducting energy gap is indicative of the energy gain of two electrons when they form a Cooper pair. The energy gap is temperature dependent and increases with decreasing temperature.

(26) Therefore, by varying the capacitance C.sub.Σ, which includes the contribution of the capacitance Cs, it is possible to change or vary the resonance frequency (for example, the first resonance frequency f.sub.01) of the qubit.

(27) FIG. 2 is a contour map of a simulated two-dimensional electric field generated by the capacitor pads 104A and 104B connected to the Josephson junction 102, according to an embodiment of the present invention. The two capacitor pads 104A and 104B of the qubit 100 are represented as bars in FIG. 2. The Josephson junction 102 (not shown) is located between the two bars 104A and 104B. For example, the left bar corresponding to capacitor pad 104A can be connected to a zero electric potential while the right bar corresponding to capacitor pad 104B can be connected to a higher electric potential (for example, approximately 7 10.sup.3 V/m). In FIG. 2, the electric contour map is superposed on a representation of the capacitor pads 104A, 104B which are part of the quantum mechanical device 200. The qubit 100 is also part of the quantum mechanical device 200 which also include a substrate 202. The substrate 202 has frontside 202A and a backside 202B. The capacitor pads 104A and 104B represented as bars in FIG. 2 and the Josephson junction 102 located between the two capacitor pads 104A and 104B of the qubit 100 are located on the frontside 200A of the substrate 202 of the quantum mechanical device 200.

(28) Changes in electric field distribution are indicative of changes in the effective dielectric constant of the substrate 202. The capacitance of the quantum mechanical device 200 is related to the effective dielectric constant of the substrate 202. Changes in the electric field distribution can be implemented by changing a thickness of the substrate 200 at specific locations in the substrate 202. For example, this can be performed by etching the substrate 202 from the backside 202B, i.e., removing substrate material from the backside 202B. Changes in electric field distribution due to etching of the substrate 202 at the backside 202B are indicative of changes in the quantum mechanical device capacitance.

(29) FIGS. 3A-3C are contour maps of a distribution of the electric potential around the capacitor pads 104A and 104B, according to embodiments of the present invention. The electric potential contour lines 300 are drawn around the ends of the capacitor pads 104A and 104B. FIG. 3A shows the distribution the electric potential around the Josephson junction 102 with the backside 202B of the substrate 202 of the device 200 being not etched. Ends of the capacitor pads 104A, 104B can be recognized by the presence of higher concentration of the electric potential (shown generally as circular dots) 300. The Josephson junction 102 is located between an end of capacitor pad 104A and end of capacitor pad 104B.

(30) FIG. 3B shows the distribution of the electric potential around the Josephson junction 102. The Josephson junction 102 is also located between an end of capacitor pad 104A and an end of capacitor pad 104B. However, as shown in FIG. 3B, the backside 202B of the substrate 202 is etched in the vicinity of the Josephson junction 102. The profile of the etched material of the substrate 202 is shown as a trapezoid shape 302 wherein more material is removed in the vicinity of the Josephson junction 102 than away from the Josephson junction 102. The removal of material at the backside 202B of the substrate 202 modifies the shape of electric potential lines 300 and thus the distribution of the electric potential around or in the vicinity of the Josephson junction 102. Therefore, this indicates that the capacitance of the qubit 100 around the Josephson junction 102 and the capacitor pads 104A and 104B is altered.

(31) FIG. 3C shows the distribution of the electric potential around the Josephson junction 102. The Josephson junction 102 is also located between an end of capacitor pad 104A and an end of capacitor pad 104B. As shown in FIG. 3C, the backside 202B of the substrate 202 is etched in the vicinity of the Josephson junction 102 even further in comparison with the etching profile shown in FIG. 3B. The profile of the etched material of the substrate 202 is shown as a trapezoid shape 304 wherein even more material is removed in the vicinity of the Josephson junction 102 in comparison with the trapezoid profile 302 shown in FIG. 3B. The removal of material at the back 202B of the substrate 202 modifies the shape of electric potential lines 300 and thus the distribution of the electric potential around or in the vicinity of the Josephson junction 102. Therefore, this indicates that the capacitance of qubit around the Josephson junction 102 and the capacitor pads 104A and 104B is altered even further in comparison with FIG. 3B.

(32) FIG. 4 is a plot of capacitance (in %) versus etch depth (in μm) corresponding to the amount of substrate material removed at the backside 202B of the substrate 202, according to an embodiment of the present invention. The etch depth point 400 at about 0 μm corresponds to zero etch depth shown in FIG. 3A. The etch depth point 402 at about 70 μm corresponds to the etch depth shown in FIG. 3B. The etch depth point 404 at about 100 μm corresponds to the etch depth shown in FIG. 3C. At etch depth point 400, the capacitance is at 100% corresponding to the capacitance at full value. At etch depth point 402, the capacitance is at about 80%. At etch depth point 404, the capacitance is at about 20%. The capacitance decreases with increasing etch depth. At etch depth point 402, the remaining or residual thickness of the substrate material is about 30 μm. In an embodiment, a range of useful tuning of the frequency of the qubit is provided by a capacitance between about 100% and about 80% (e.g., a change in capacitance between about 0.2% to about 20%). However, it is also contemplated to provide a wider range of frequency tuning by allowing for a wider range of capacitance change, such as between 0.1% and 50%, with the removal of substrate material at depths in the range between for example about 10 μm and about 90 μm. The plot shown in FIG. 4 is provided for a specific type of substrate material in the present case silicon. Therefore, similar plots can also be provided for other types of substrate materials such as sapphire, etc. The curve capacitance vs. etch depth for silicon may be different from the curve capacitance vs. etch depth for sapphire, for example. Therefore, the above numbers for the capacitance and for the etch depth are only provided for illustration purposes to show the variation of capacitance as a function of etch depth.

(33) FIG. 5 depicts schematically the concept of varying the capacitance of a plurality of qubits by different amounts by changing the shape and/or depth of a trench or cavity at the backside of the substrate, according to an embodiment of the present invention. FIG. 5 also depicts a cross-section of three cavities in a plurality of cavities formed by etching the backside 202B of the substrate 202 of a quantum mechanical device 500. The cross-section is taken along line 5-5, as shown in FIG. 8. For example, as shown in FIG. 5, a capacitance of a first qubit (qubit 1) of the quantum mechanical device 500 is changed by about 1%, a capacitance of a second qubit (qubit 2) of the quantum mechanical device 500 is changed by about 20%, and a capacitance of a third qubit (qubit 3) of the quantum mechanical device 500 is changed by about 3%. As shown in FIG. 5, the capacitance of the qubit 1 is changed by about 1% by forming a trench or cavity 501 (e.g., a triangular trench) at the backside 202B of the substrate 202 opposite qubit 1 which is located on the frontside 202A of the substrate 202. Similarly, the capacitance of the qubit 3 is changed by about 3% by forming a wider trench or cavity 503 (e.g., a wider triangular trench) wherein more substrate material is removed or etched at the backside 202B of the substrate 202 opposite qubit 3 which is located on the frontside 202A of the substrate 202. The capacitance of the qubit 2 is changed by about 20% by forming an even wider trench or cavity 502 (e.g., a wider trapezoid trench) wherein even more substrate material is removed or etched at the backside 202B of the substrate 202 opposite qubit 2 which is located on the frontside 202A of the substrate 202.

(34) Therefore, as it can be appreciated from the above paragraphs, there is provided the quantum mechanical device 500 having a plurality of qubits (qubit 1, qubit 2, qubit 3) formed on the frontside 202A of the substrate 202. The plurality of qubits (qubit 1, qubit 2, qubit 3) include a plurality of capacitor pads 104A, 104B. The substrate 202 has one or more cavities 501, 502, 503 formed on the backside 202B of the substrate 202 opposite one or more qubits (qubit 1, qubit 2, qubit 3) of the plurality of qubits (qubit 1, qubit 2, qubit 3). A size or a shape, or both, of the one or more cavities 501, 502, 503 are selected to alter a capacitance around the one or more of qubits (qubit 1, qubit 2, qubit 3) so as to adjust a resonance frequency of the one or more qubits (qubit 1, qubit 2, qubit 3).

(35) In an embodiment, the substrate 202 can be for example silicon, high resistivity silicon, or sapphire. In an embodiment, the plurality of capacitor pads 104A, 104B are made from a superconducting material. The superconducting material can be, for example, aluminum (Al), niobium (Nb), etc.

(36) In an embodiment, the resonance frequency of the one or more qubits (qubit 1, qubit 2, qubit 3) can be adjusted by 0.2% to 20%. For example, the resonance frequency of qubit 1 can be adjusted by about 2% by changing a capacitance by about 1%. The resonance frequency of qubit 2 can be adjusted by about 40% by changing a capacitance by about 20%. The resonance frequency of qubit 3 can be adjusted by about 6% by changing a capacitance by about 3%. Therefore, in an embodiment, the resonance frequency of each of the one or more qubits (qubit 1, qubit 2, qubit 3) can be adjusted by a different amount depending on the size or the shape, or both, of the one or more cavities 501, 502 and 503.

(37) As it can be appreciated from the above paragraphs, there is also provided a method for adjusting a resonance frequency of a qubit (e.g., qubit 1, qubit 2, qubit 3) in a quantum mechanical device (e.g., quantum mechanical device 500). FIG. 6 is a flow chart of the method for adjusting a resonance frequency of the qubit (e.g., qubit 1, qubit 2, qubit 3) in the quantum mechanical device (e.g., quantum mechanical device 500), according to an embodiment of the present invention. The method includes providing substrate 202 having frontside 202A and backside 202B, at step S602. The frontside 202A has at least one qubit (qubit 1, qubit 2, qubit 3) formed thereon. The at least one qubit (qubit 1, qubit 2, qubit 3) includes capacitor pads 104A, 104B. The method further includes removing substrate material from the backside 202B of the substrate 202 at an area opposite the at least one qubit (qubit 1, qubit 2, qubit 3) to alter a capacitance around the at least one qubit (qubit 1, qubit 2, qubit 3) so as to adjust a resonance frequency of the at least one qubit (qubit 1, qubit 2, qubit 3), at step S604.

(38) In an embodiment, removing the substrate material from the backside 202B of the substrate 202 at the area opposite the at least one qubit (qubit 1, qubit 2, qubit 3) includes chemically etching the backside 202B of the substrate 202 selectively using a chemical etchant selected depending on the substrate material (e.g., silicon, sapphire, etc.). In an embodiment, prior to chemically etching the backside 202B of the substrate 202, forming an initial cavity in the backside 202B of the substrate 202 in a vicinity of the at least one qubit (e.g., qubit 1, qubit 2, qubit 3) by mechanically removing material from the backside 202B of the substrate 202 and then chemically etching the backside 202B of the substrate 202 at the formed initial cavity.

(39) FIG. 7 is a schematic representation of an initial cavity 602 formed on the backside 202B of the substrate 202 leading to a self-limiting anisotropic etch, according to an embodiment of the invention. In an embodiment, forming the initial cavity 602 in the backside 202B of the substrate 202 includes defining faces 604 of the initial cavity 602 having one or more first crystal planes 604A (e.g., crystal plane (111)) and one or more second crystal planes 604B (e.g., crystal plane (100)) so that the chemical etchant preferentially etches the substrate material from the one or more first crystal planes 604A (e.g., crystal plane (111)) while substantially not etching the substrate material from the one or more second crystal planes 604B (e.g., crystal plane (100)) to form an etched final cavity 606 in the vicinity of the at least one qubit (not shown in FIG. 7). In this way, the etching is anisotropic as it etches preferentially one crystal plane over another crystal plane and is self-limiting because when the etchant reaches the less etchable crystal plane (second crystal plane), the etching automatically stops.

(40) In an embodiment, the substrate material can be for example silicon in which case the one or more first crystal planes includes a (111) silicon crystal plane and the one or more second crystal planes includes a (100) silicon crystal plane. However, other crystal planes can be selected depending of the type of substrate material.

(41) In an embodiment, the method includes controlling an amount of the substrate material etched by selecting a size and shape of the initial cavity (e.g., cavity 602) so that the etching of the substrate material stops when the one or more first crystal planes 604A (e.g., (111)-plane) are substantially eliminated so as to form size self-limited etched final cavities. In an embodiment, controlling the amount of material etched includes controlling an etching depth of the etched final cavities from the backside 202B to the frontside 202A of the substrate 202.

(42) FIG. 8 depicts the backside 202B of the substrate 202 having a plurality of cavities 800, according to an embodiment of the present invention. For example, the size and/or the shape of the cavities can be controlled by selecting an appropriate shape for the initial cavities 602 (shown in FIG. 7). In this way, the etching of the substrate material stops when the one or more first crystal planes 604A (e.g., (111)-plane) are substantially eliminated so as to form size self-limited etched final cavities 800. A cross-section along line 5-5 of formed three cavities is shown in FIG. 5.

(43) In an embodiment, the removing the substrate material from the backside 202B of the substrate 202 at the area opposite the at least one qubit 100 (e.g., qubit 1, qubit 2, qubit 3) includes applying an etch mask film 900 to the backside 202B of the substrate 202 and etching selected areas at the backside 202B of the substrate 202 opposite the at least one qubit 100. FIG. 9 shows a three-dimensional representation of an etch mask film 900 applied to the backside 202B of the substrate, according to an embodiment of the present invention. In an embodiment, applying the etch mask film 900 to the backside 202B of the substrate 202 includes depositing niobium (Nb) on the backside 202B of the substrate 202. In another embodiment, applying the etch mask film 900 to the backside 202B of the substrate 202 includes depositing an oxide or silicon nitride (SiN) on the backside 202B of the substrate 202. In yet another embodiment, creating an etch mask includes oxidizing a silicon substrate 202 and removing an oxide layer on the frontside 202A of the silicon substrate 202.

(44) In an embodiment, after applying or creating the etch mask 900 on the substrate 202, processing the substrate by performing aluminum evaporation on the frontside 202A of the substrate 202 to create the capacitor pads, the Josephson junction, etc. The backside coated processed substrate is then diced to create a plurality of chips 1002. A micrograph image is then taken of the frontside 202A of the diced qubit chip 1002 to register the locations of the qubits 100 (e.g., qubit 1, qubit 2, qubit 3) relative to the diced edges. FIG. 10 shows an example micrograph image of the qubit chip 1002 having four qubits (qubit 1, qubit 2, qubit 3 and qubit 4), for example, on frontside 1004A of substrate 1004 of qubit chip 1002, according to an embodiment of the present invention.

(45) The method also includes bump-bonding the substrate 1004 of the qubit chip 1002 having the qubits (qubit 1, qubit 2, qubit 3 and qubit 4) to an interposer substrate 1102. FIG. 11 is a schematic representation of a qubit chip 1002 bonded to interposer substrate 1102 with bump bonds 1006, according to an embodiment of the present disclosure. The frontside 1004A of the substrate 1004 of the qubit chip 1002 having the qubits provided thereon faces the interposer substrate 1102 while the backside 1004B of the substrate 1004 of the qubit chip 1002 faces away from or opposite to the interposer substrate 1102.

(46) In an embodiment, the method also includes, subsequent to applying the etch film mask 900 to the backside 1004B of the substrate 1004 and prior to etching the selected areas at the backside 1004B of the substrate 1004, forming one or more openings 1202 in the etch film mask 900 at the selected areas. FIG. 12 is a schematic representation of the qubit chip 1002 bonded to interposer substrate 1102 having one or more openings 1202 formed on the backside 1004B of the substrate 1004, according to an embodiment of the present disclosure. In an embodiment, the one or more openings 1202 can be formed, for example, by using focused ion beam (FIB) etching, laser ablation, mechanical milling, or any combination thereof, or other etching methods.

(47) In an embodiment, the method further includes disposing a chemical etchant container 1302 to define an area 1304 around the one or more openings 1202 in the etch film mask 900 and providing a wet or dry etching chemical to remove substrate material from the defined area 1304 at the one or more openings 1202 in the etch film mask 900 to form one or more cavities (such as cavities 501, 502, 503 shown in FIG. 5) at the backside 1004B of the substrate 1004. FIG. 13A is a schematic three-dimensional representation of container 1302 deposited on the backside 1004B of the substrate 1004 to define area 1304 around the one or more openings 1202 in the etch film mask 900, according to an embodiment of the present invention. FIG. 13B is a schematic top view inside the container 1302 showing the relative position of the qubit chip 1002 and the one or more openings 1202, according to an embodiment of the present invention. FIG. 13C is a schematic view showing the position of the qubit chip 1002 relative to the container 1302, the qubit chip being positioned on the frontside 1004A of the substrate 1004, according to an embodiment of the present invention.

(48) In an embodiment, removing substrate material from the backside 1004B of the substrate 1004 at an area 1304 opposite the at least one qubit (qubit 1, qubit 2, . . . ) includes removing the substrate material from the backside 1004B of the substrate 1004 at a plurality of areas 1304 opposite to a plurality of qubits to form a plurality of cavities on the backside 1004B of the substrate 1004. In an embodiment, removing the substrate material from the backside 1004B of the substrate 1004 at the plurality of areas opposite to the plurality of qubits includes removing the substrate material from the backside 1004B of the substrate 1004 at the plurality of areas 1304 opposite to the plurality of qubits substantially simultaneously using a global substrate etch process. In an embodiment, the global etch process includes applying a chemical etch process. For example, the chemical etchant can be poured into the chemical etchant container 1302 to etch the substrate at the one or more openings 1202.

(49) In an embodiment, the method further includes controlling an amount of material etched by selecting a size and shape of a formed initial cavity for each of the plurality of areas so that the etching of the substrate material stops at different times depending upon a selected geometry or shape of the initial opening (for example as shown in FIG. 7). In an embodiment, forming the initial cavity includes defining faces of the initial cavity having one or more first crystal planes and one or more second crystal planes in the substrate material so that the substrate material is etched from the one or more first crystal planes while substantially not etched from the one or more second crystal planes, as described in the above paragraphs.

(50) The above backside etching method has many benefits including: 1) individual qubits can be independently frequency tuned, for example, by using varying degrees of backside substrate removal at a proximity of each qubit thereby changing qubit capacitance by different amounts; 2) individual qubits can be independently frequency tuned using a global substrate etch process; 3) backside etching enables qubit operational specifications to be modified with substantially less perturbation or minimal perturbation to the environment of the qubit; 4) qubit frequency tuning after bump bonding or packaging of the chip is enabled, thus allowing fine tuning the qubit specifications after packaging has taken place which enables a more reliable and controllable end product for optimal device performance.

(51) The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.