Parallel write scheme utilizing spin hall effect-assisted spin transfer torque random access memory

Abstract

A magnetoresistive random access memory (MRAM) and associated apparatus and methods are described. The MRAM generally includes a heavy metal layer coupled to a source line, and a plurality of bit cells coupled to a word line, a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines.

Claims

1. An apparatus comprising: a magnetoresistive random access memory (MRAM), comprising: a heavy metal layer coupled to a source line; and a plurality of bit cells coupled to a word line, and a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines; and a controller coupled to the MRAM and configured to: apply a first voltage to at least a portion of the heavy metal layer and a second voltage lower than the first voltage at another portion of the heavy metal layer during a first phase; and apply a third voltage to the heavy metal layer during a second phase, the third voltage being between the first voltage and the second voltage.

2. The apparatus of claim 1, wherein the controller is configured to write a value to the MTJs via spin Hall effect-assisted spin transfer torque write operations.

3. The apparatus of claim 2, wherein, during the first phase, the controller is configured to apply the first voltage and the second voltage, such that free layers of the MTJs are magnetized via the spin Hall effect of the heavy metal layer as the first and second voltages are applied.

4. The apparatus of claim 3, wherein, during the second phase, the controller is configured to apply the third voltage to the heavy metal layer and a fourth voltage to at least one of the bit lines, such that the free layer of the MTJ coupled to the at least one of the bit lines is magnetized in a first direction relative to a fixed layer of the MTJ coupled to the at least one of the bit lines via spin transfer torque (STT).

5. The apparatus of claim 4, wherein, during the second phase, the controller is configured to apply the third voltage to the heavy metal layer and a fifth voltage to at least one of the bit lines, such that the free layer of the MTJ coupled to the at least one of the bit lines is magnetized in a second direction relative to a fixed layer of the MTJ coupled to the at least one of the bit lines via spin transfer torque (STT).

6. The apparatus of claim 4, wherein the fourth voltage is less than the third voltage, and wherein the controller is configured to apply the first and second voltages before the third and fourth voltages.

7. The apparatus of claim 5, wherein the third voltage is less than the fifth voltage, and wherein the controller is configured to apply the first and second voltages before the third and fifth voltages.

8. The apparatus of claim 1, wherein the heavy metal layer comprises at least one of tantalum (Ta), tungsten (W), or platinum (Pt).

9. The apparatus of claim 1, wherein each free layer of the MTJs is coupled to the heavy metal layer.

10. A method of writing to a magnetoresistive random access memory (MRAM) comprising a plurality of bit cells coupled to a word line, a plurality of bit lines, and a heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to a source line, the method comprising: applying, during a first phase, a first voltage to at least a portion of the heavy metal layer and a second voltage lower than the first voltage at another portion of the heavy metal layer, such that free layers of magnetic tunnel junctions (MTJs) of the bit cells are magnetized via a spin Hall effect of the heavy metal layer; and applying, during a second phase, at least one of: a third voltage being between the first voltage and the second voltage to the heavy metal layer and a fourth voltage to at least one of the bit lines, such that the free layer of the MTJ coupled to the at least one of the bit lines is magnetized in a first direction relative to a fixed layer of the MTJ coupled to the at least one of the bit lines via spin transfer torque (STT), or the third voltage being between the first voltage and the second voltage to the heavy metal layer and a fifth voltage to at least one of the bit lines, such that the free layer of the MTJ coupled to the at least one of the bit lines is magnetized in a second direction relative to the fixed layer of the MTJ coupled to the at least one of the bit lines via STT.

11. The method of claim 10, wherein: the fourth voltage is less than the third voltage, the third voltage is less than the fifth voltage, and applying the first and second voltages occurs before applying at least one of the third and fourth voltages or the third and fifth voltages.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

(2) FIG. 1 is a schematic illustrating an example Spin Hall Effect (SHE)-assisted STT-MRAM, in accordance with certain aspects of the present disclosure.

(3) FIG. 2 is a diagram illustrating example writing operations for the SHE-assisted STT-MRAM, in accordance with certain aspects of the present disclosure.

(4) FIG. 3A illustrates a diagram view of an example MTJ partially rotating the magnetization of the free layer, in accordance with certain aspects of the present disclosure.

(5) FIG. 3B illustrates a diagram view of an example MTJ for modifying the free layer to a first direction relative to the magnetization of the fixed layer (e.g., parallel magnetization), in accordance with certain aspects of the present disclosure.

(6) FIG. 3C illustrates a diagram view of an example MTJ for modifying the free layer to a second direction relative to the magnetization of the fixed layer (e.g., anti-parallel magnetization), in accordance with certain aspects of the present disclosure.

(7) FIG. 4 is a flow diagram of example operations for writing to STT-MRAM utilizing the SHE-assisted STT technique described herein, in accordance with certain aspects of the present disclosure.

(8) FIG. 5 illustrates an example system-on-chip (SOC) that may include various components configured to perform the writing operations disclosed herein, in accordance with certain aspects of the present disclosure.

(9) To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation.

DETAILED DESCRIPTION

(10) Aspects of the present disclosure provide apparatus, MRAM, and methods for writing to MRAM using a Spin Hall effect to assist in modifying a magnetic layer of a magnetic tunnel junction during a spin transfer torque operation.

(11) The following description provides examples, and is not limiting of the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For instance, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim. The word exemplary is used herein to mean serving as an example, instance, or illustration. Any aspect described herein as exemplary is not necessarily to be construed as preferred or advantageous over other aspects.

Example Parallel Write Scheme for Stt-Mram

(12) As indicated above, challenges with STT-MRAM are the high write energy and insufficient switching speed, which are barriers to implementing STT-MRAM in embedded system memory applications (e.g., SoCs or ASICs in wireless communication devices). To achieve a nanosecond switching time via STT, the write current needs to be exponentially increased, which in turn requires a large size access transistor, limiting the cell array density. For example, switching times achieved for STT-MRAM are greater than 10 nanoseconds with write energies exceeding 100 fJ. The spin Hall effect (SHE) enables nanosecond switching with a moderate current by reducing the incubation time. However, in case of controlling perpendicular MTJ, SHE requires an external magnetic field to break the symmetry for realizing a deterministic switching, and thus limiting the cell array density. The present disclosure provides a parallel write scheme for STT-MRAM that utilizes a SHE-assisted STT operation in an array level, providing low write energy, high-density, and high-throughput. This may enable the STT-MRAM to provide switching times and write energies suitable for embedded memory applications.

(13) FIG. 1 illustrates a schematic view of an example STT-MRAM, in accordance with certain aspects of the present disclosure. As shown, the STT-MRAM 100 includes a plurality of bit cells 102 and a heavy metal layer 114. The bit cells 102 and heavy metal layer 114 represent an example word line column, which be implemented in an MRAM cell array structure having multiple word line columns and bit line rows. In certain aspects, the number of bit cells per word line may vary depending on, for example, the impedance of the heavy metal layer 114 and available supply voltage. For instance, although four bit cells 102 are depicted in FIG. 1, a word line may have 2, 4, 8, 16, 32, or more bit cells.

(14) The bit cells 102 are coupled to a word line WL, a plurality of bit lines BL.sub.0-BL.sub.3, and the heavy metal layer 114. Each of the bit cells 102 includes a magnetic tunnel junction 104 (MTJ) having a magnetically fixed layer 106 (i.e., pinned or reference layer) and a magnetically free layer 110. The fixed layer 106 and the free layer 110 may be separated by a non-magnetic spacer layer 108. The magnetization orientation of the fixed layer 106 is pinned in a predetermined direction (as indicated by the single-headed arrow) while the magnetization orientation of the free layer 110 is free to rotate (as indicated by the double-headed arrow). The magnetization orientations of the free layer 110 and fixed layer 106 may be either parallel or anti-parallel relative to each other. Each free layer 110 of the MTJs 104 is coupled to the heavy metal layer 114.

(15) Each of the bit cells 102 also includes a transistor 112 that couples the MTJ 104 to a word line WL and one of the bit lines BL.sub.0-BL.sub.3. A gate of the transistor 112 is coupled to the word line WL, and at least one of a source or a drain of the transistor 112 is coupled to the MTJ 104 or at least one of the bit lines BL.sub.0-BL.sub.3, depending on the current direction through the MTJ 104. The transistors 112 may be used to control the voltage applied to the MTJs 104 during the SHE-assisted STT write operation as further described herein

(16) The heavy metal layer 114 is coupled to a source line SL.sub.1, SL.sub.2 via transistors 116. The heavy metal layer 114 is a continuous layer or continuous strip of metal coupling the bit cells 102 to the source line SL.sub.1, SL.sub.2. That is, the bits cells 102 are coupled in parallel via the heavy metal layer 114, which may be a continuous strip of metal. The heavy metal layer 114 may include a heavy metal such as tantalum (Ta), tungsten (W), platinum (Pt), any other suitable heavy metal, or a combination thereof. The transistors 116 may be used to control the voltage applied to the heavy metal layer 114 during the SHE-assisted STT write operation as further described herein.

(17) The STT-MRAM 100 may also include a controller 120 configured to write values to the MTJs 104 via SHE-assisted STT writing operations as further described herein. The controller 120 may have output terminals coupled to the corresponding word line WL, bit lines BL.sub.0-BL.sub.3, and source line SL.sub.1, SL.sub.2 to apply control signals to the bit cells 102 and heavy metal layer 114. The controller 120 may be a processor, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, or a combination thereof.

(18) FIG. 2 illustrates timing diagrams of example writing operations for STT-MRAM (e.g., STT-MRAM 100), in accordance with certain aspects of the present disclosure. As shown, the timing diagrams 202, 204, 206, 208 represent functions of voltage with respect to time. The timing diagrams 202, 204, 206, 208 demonstrate that the write operation may undergo an initial SHE phase followed by an STT phase. The voltages V.sub.H, V.sub.L, V.sub.M, V.sub.AP, and V.sub.P are control signals applied to the heavy metal layer or the bit cells used to apply an SHE to the heavy metal layer and assist an STT writing operation. The timing diagrams 202, 204 illustrate the voltages (V.sub.H, V.sub.L, V.sub.M) applied to the heavy metal layer during the SHE and STT phases. The timing diagram 206 illustrates an example voltage (V.sub.AP) applied to one of the bit cells to rotate the magnetization of the free layer to a first direction (e.g., an anti-parallel magnetization) during the STT phase. The timing diagram 208 illustrates an example voltage (V.sub.P) applied to one of the bit cells to rotate the magnetization of the free layer to a second direction (e.g., a parallel magnetization) during the STT phase.

(19) As illustrated in FIG. 2, the SHE phase is initially performed to partially rotate the magnetization of the free layer, for example, to an in-plane level, which enables less write energy and write time to be used to complete the rotation of the free layer during the STT phase. For example, during the SHE phase, the voltage V.sub.H may be applied to a portion of the heavy metal layer (such as SL.sub.1), and the voltage V.sub.L may be applied to another portion of the heavy metal layer (such as SL.sub.2). The current conducted through the heavy metal layer may induce an SHE in the free layer to rotate the magnetization of the free layer, for example, to an in-plane level.

(20) After the magnetization of the free layer is partially rotated during the SHE phase, voltages V.sub.AP or V.sub.P may be applied to the MTJs to continue the rotation of the magnetization of the free layers utilizing the effect of STT. For example, during the STT phase, the voltage V.sub.M may be applied to the heavy metal layer (such as SL.sub.1 and SL.sub.2) to provide a reference voltage to the MTJs and enables the MTJs to conduct current in a direction depending on the bit line control signals V.sub.AP, and V.sub.P. The voltage V.sub.AP may be applied to one of the bit lines (BL.sub.0-BL.sub.3) to rotate the magnetization of the free layer to a first direction (e.g., an anti-parallel magnetization). The voltage V.sub.P may also be applied to one of the bit lines (BL.sub.0-BL.sub.3) to rotate the magnetization of the free layer to a second direction (e.g., an anti-parallel magnetization). Thus, the current may flow in one direction across an MTJ when the voltages V.sub.AP and V.sub.M are applied to a bit cell, whereas the current flows in another direction across the MTJ when the voltages V.sub.P and V.sub.M are applied to the bit cell. In addition, a control signal via the word line (e.g., WL of FIG. 1) is applied to the gate of transistors (e.g., transistor 112) coupled to the MTJs to select the column of bit cells for the writing operation during the STT phase.

(21) As depicted in FIG. 2, the voltage V.sub.L (e.g., 0 V) is less than the voltage V.sub.H (e.g., 1 V); the voltage V.sub.M (e.g., 0.5 V) is less than the voltage V.sub.AP (e.g., 1 V), and the voltage V.sub.P (e.g., 0 V) is less than the voltage V.sub.M (e.g., 0.5 V). In certain aspects, different voltage levels for voltages V.sub.H, V.sub.L, V.sub.M, V.sub.AP, and V.sub.P may be used to conduct the SHE-assisted STT writing operation described herein. For example, the voltage V.sub.AP and V.sub.P may be swapped depending on how the magnetization of the fixed layer is oriented. That is, V.sub.M may be less than the voltage V.sub.P, and the voltage V.sub.AP may be less than the voltage V.sub.M. Further, although V.sub.H and V.sub.AP are depicted in FIG. 2 as being at similar voltage levels, these voltages may vary depending on the impedance characteristics of the heavy metal layer, the available supply voltages, or other factors to achieve the SHE-assisted STT writing operation as described herein. Likewise, V.sub.L and V.sub.P may also vary from the voltage levels depicted in FIG. 2.

(22) FIG. 3A illustrates a diagram view of an example MTJ for partially rotating the magnetization of the free layer, in accordance with certain aspects of the present disclosure. As shown, voltages V.sub.H and V.sub.L are initially applied to the heavy metal layer 114 to induce spin accumulation at the lateral boundaries of the heavy metal layer 114 (i.e., the SHE is applied to the heavy metal layer 114). This spin accumulation magnetically polarizes the heavy metal layer 114 and partially rotates the magnetization of the free layer 110. As illustrated in FIG. 3A, the magnetization of the free layer 110 may be oriented orthogonal to the current direction. For example, the magnetization of the free layer 110 may be oriented with {circumflex over (x)} or {circumflex over (x)}, as shown in FIG. 3A, depending on the current direction. This partial rotation of the magnetization of the free layer 110 enables faster writes and less write energy during the STT phase as depicted in FIGS. 3B and C.

(23) FIG. 3B illustrates a diagram view of an example MTJ for modifying the free layer to a first direction relative to the magnetization of the fixed layer (e.g., parallel magnetization), in accordance with certain aspects of the present disclosure. As shown, after the SHE phase, the voltage V.sub.M is applied to the heavy metal layer 114 to provide a reference voltage that enables current to be conducted through the MTJ 104. The voltage V.sub.P is applied to the MTJ 104 to conduct current in a direction that rotates the magnetization of the free layer in the first direction relative to the magnetization of the fixed layer 106. In this example, the magnetization of the free layer 110 is rotated to have a parallel magnetization relative to the fixed layer 106.

(24) FIG. 3C illustrates a diagram view of an example MTJ for modifying the free layer to a second direction relative to the magnetization of the fixed layer (e.g., anti-parallel magnetization), in accordance with certain aspects of the present disclosure. As discussed above, the voltage V.sub.M provides a reference voltage that enables current to be conducted through the MTJ 104. The voltage V.sub.AP is applied to the MTJ 104 to conduct current in a direction that rotates the magnetization of the free layer in the second direction relative to the magnetization of the fixed layer 106. In this example, the magnetization of the free layer 110 is rotated to have an anti-parallel magnetization relative to the fixed layer 106.

(25) FIGS. 3A-C illustrate example SHE-assisted STT writing operations for a single MTJ. The writing operations described herein with respect to FIGS. 3A-C are also applicable to multiple MTJs coupled in parallel via the heavy metal layer such as the bit cells depicted in FIG. 1.

(26) FIG. 4 is a flow diagram of example operations for writing to STT-MRAM utilizing the SHE-assisted STT technique described herein, in accordance with certain aspects of the present disclosure. The operations 400 may be performed, for example, by a controller (e.g., controller 120) coupled to the STT-MRAM to conduct the writing operation.

(27) The operations 400 may begin, at 402, where the controller applies a first voltage to at least a portion of the heavy metal layer and a second voltage lower than the first voltage at another portion of the heavy metal layer, such that free layers of magnetic tunnel junctions (MTJs) of the bit cells are magnetized via a spin Hall effect of the heavy metal layer. At 404, the controller applies a third voltage to the heavy metal layer via the source line, and the controller may apply a fourth voltage to at least one of the bit lines, such that the free layer of the MTJ coupled to the at least one of the bit lines is magnetized in a first direction relative to a fixed layer of the MTJ coupled to the at least one of the bit lines via spin transfer torque (STT). At 404, the controller may also apply a fifth voltage to at least one of the bit lines, such that the free layer of the MTJ coupled to the at least one of the bit lines is magnetized in a second direction relative to the fixed layer of the MTJ coupled to the at least one of the bit lines via STT.

(28) In certain aspects, the SHE-assisted STT MRAM may be packaged on a stand alone memory chip or an integrated circuit having a processing system. For example, FIG. 5 illustrates an example system-on-chip (SoC) 500 that may include various components configured to perform the writing operations disclosed herein, such as the SHE-assisted STT writing operations illustrated in FIG. 4. The SoC 500 includes a chip package 502 having a processor 504 coupled to a computer-readable medium/memory 508 via a bus 506. In certain aspects, the computer-readable medium/memory 1012 may include STT-MRAM 510 and read-only memory 512 (ROM). The STT-MRAM 510 is configured to perform the SHE-assisted STT writing operation discussed herein.

(29) The processor 504 may also be coupled to a modem 514, a visual processing system 516, and an image signal processor 518 via the bus 506. In certain aspects, these components may vary depending on the application of the SoC 500. For instance, the SoC 500 may lack a visual processing system 516 and/or an image signal processor 518 for internet of things (IoT) applications.

(30) The SHE-assisted STT-MRAM provides various improvements over conventional STT-MRAM. The SHE-assisted STT-MRAM described herein may enable a reduction in the write current for the STT phase, which facilitates the use of smaller access transistors (e.g., transistors 112) and increases the density of the MRAM. For example, the SHE-assisted STT-MRAM may reduce the area of the bit cell structure by about 50% relative to a conventional STT-bit cell. In addition, the SHE-assisted STT-MRAM may also facilitate the use of less energy during the write operation and faster write times.

(31) The methods disclosed herein comprise one or more steps or actions for achieving the methods. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

(32) As used herein, a phrase referring to at least one of a list of items refers to any combination of those items, including single members. As an example, at least one of: a, b, or c is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

(33) As used herein, the term determining encompasses a wide variety of actions. For example, determining may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, determining may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, determining may include resolving, selecting, choosing, establishing and the like.

(34) The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean one and only one unless specifically so stated, but rather one or more. Unless specifically stated otherwise, the term some refers to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. 112(f) unless the element is expressly recited using the phrase means for or, in the case of a method claim, the element is recited using the phrase step for.

(35) The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

(36) The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

(37) If implemented in hardware, an example hardware configuration may comprise a processing system implemented on a SoC. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement the signal processing functions of the PHY layer. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further. The processor may be implemented with one or more general-purpose and/or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

(38) If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer readable medium. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. The processor may be responsible for managing the bus and general processing, including the execution of software modules stored on the machine-readable storage media. A computer-readable storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer readable storage medium with instructions stored thereon separate from the wireless node, all of which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Examples of machine-readable storage media may include, by way of example, RAM (Random Access Memory), flash memory, ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product.

(39) A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. The computer-readable media may comprise a number of software modules. The software modules include instructions that, when executed by an apparatus such as a processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module.

(40) Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer-readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.

(41) Thus, certain aspects may comprise a computer program product for performing the operations presented herein. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. For example, instructions for performing the operations are described herein and illustrated in FIG. 4.

(42) Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.

(43) It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.