III-V SEMICONDUCTOR DIODE

Abstract

A stacked III-V semiconductor diode having an n.sup.+-layer with a dopant concentration of at least 10.sup.19 N/cm.sup.3, an n.sup.-layer with a dopant concentration of 10.sup.12 -10.sup.16 N/cm.sup.3, a layer thickness of 10-300 microns, a p.sup.+-layer with a dopant concentration of 510.sup.18-510.sup.20 cm.sup.3, with a layer thickness greater than 2 microns, wherein said layers follow one another in the sequence mentioned, each comprising a GaAs compound. The n.sup.+-layer or the p.sup.+-layer is formed as the substrate and a lower side of the n.sup.-layer is materially bonded with an upper side of the n.sup.+-layer, and a doped intermediate layer is arranged between the n-layer and the p+-layer and materially bonded with an upper side and a lower side.

Claims

1. A stacked III-V semiconductor diode comprising: an n.sup.+-layer with an upper side, a lower side, a dopant concentration of at least 10.sup.19 N/cm.sup.3 and a layer thickness of 50-675 microns, and comprising a GaAs compound; an n.sup.-layer with an upper side and a lower side, a dopant concentration of 10.sup.12-10.sup.16 N/cm.sup.3, a layer thickness of 10-300 microns, and comprising a GaAs compound; a p.sup.+-layer with an upper side, a lower side, a dopant concentration of 510.sup.18-510.sup.20 N/cm.sup.3, with a layer thickness greater than 2 microns and comprising a GaAs compound; and a p-doped intermediate layer with a layer thickness of 1-50 microns and a dopant concentration of 10.sup.12-10.sup.17 N/cm.sup.3 is disposed between the n.sup.-layer and the p.sup.+-layer, and is materially bonded with an upper side and a lower side, the lower side of the p-doped intermediate layer being materially bonded with the upper side of the n.sup.-layer, and the upper side of the p-doped intermediate layer being materially bonded with the lower side of the p.sup.+-layer, wherein the n.sup.+-layer, the n.sup.-layer, and the p.sup.+-layer are monolithically formed, wherein the n.sup.+-layer is formed as a substrate and the lower side of the n.sup.-layer is materially connected to the upper side of the n.sup.+-layer, wherein the p-doped intermediate layer is materially bonded with the n.sup.-layer and with the p.sup.+-layer, wherein the stacked III-V semiconductor diode has a first defect layer with a layer thickness between 0.5 microns and 40 microns, wherein the first defect layer is arranged within the p-doped intermediate layer, wherein the defect layer has a defect concentration ranging between 110.sup.13 N/cm.sup.3 and 510.sup.16 N/cm.sup.3, and wherein a first contact is materially bonded with a lower side of the n.sup.+-layer and a second contact is materially bonded with an upper side of the p.sup.+-layer.

2. The stacked III-V semiconductor diode according to claim 1, wherein the first defect layer has half the layer thickness of the p-doped intermediate layer.

3. The stacked III-V semiconductor diode according to claim 1, wherein the first defect layer has a layer thickness ranging between 0.5 microns and 10 microns and a defect density ranging between 110.sup.13N/cm.sup.3 and 510.sup.16 N/cm.sup.3.

4. The stacked III-V semiconductor diode according to claim 1, wherein the first defect layer is at a distance from a space charge region.

5. The stacked III-V semiconductor diode according to claim 1, wherein the semiconductor diode has a second defect layer, wherein the second defect layer has a layer thickness between 0.5 microns and 40 microns and a defect concentration between 110.sup.13 N/cm.sup.3 and 510.sup.16 N/cm.sup.3 and is spaced from the upper side of the p-doped intermediate layer by not more than half of the layer thickness of the p-doped intermediate layer.

6. The stacked III-V semiconductor diode according to claim 1, wherein the first defect layer and/or a second defect layer each comprise a first layer region with a first defect concentration and a second layer region with a second defect concentration.

7. The stacked III-V semiconductor diode according to claim 1, wherein a defect concentration over the layer thickness of the first defect layer and/or of a second defect layer occurs according to a random distribution.

8. The stacked III-V semiconductor diode according to claim 1, wherein the first defect layer and/or a second defect layer comprises Cr and/or indium and/or aluminum.

9. The stacked III-V semiconductor diode according to claim 1, wherein the first defect layer and/or the second defect layer is generated by implantation of H.sub.2 molecules with the relevant energy and dosage or by electron beam radiation.

10. The stacked III-V semiconductor diode according to claim 1, wherein a total height of a stacked layer structure formed of the p.sup.+-layer, the n.sup.-layer, the p-doped intermediate layer and the n.sup.+-layer is at most 150-800 microns.

11. The stacked III-V semiconductor diode according to claim 1, wherein the layer thickness of the n.sup.+-layer ranges between 100 microns and 675 microns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

[0059] FIG. 1 is a view of an according to the invention of a III-V semiconductor diode;

[0060] FIG. 2 is a view of an embodiment according to the invention of a III-V semiconductor diode;

[0061] FIG. 3 is a plan view of the III-V semiconductor diode from FIG. 1 or from FIG. 2;

[0062] FIG. 4 is a view of an embodiment according to the invention of a III-V semiconductor diode; and

[0063] FIG. 5 is a view of an embodiment according to the invention of a III-V semiconductor diode.

DETAILED DESCRIPTION

[0064] The illustration of FIG. 1 shows a view of a first embodiment of a stacked III-V semiconductor diode 10 according to the invention, comprising an n.sup.+-layer 12 as a substrate, a low doped n.sup.-layer 14 that is cohesively bonded with the n.sup.+-layer 12, and a p-doped intermediate layer 15 that is materially bonded to the n.sup.-layer 14, and a p.sup.+layer 18 that is cohesively connected with the intermediate layer, as well as a first contact 20 and a second contact 22. Within the p-type layer 15, a first defect layer 16 is arranged.

[0065] The first contact 20 is materially connected with a lower side of the n.sup.+-layer 12, while the second contact 22 is materially bonded to an upper side of the p.sup.+-layer 18.

[0066] The n.sup.+-layer 12 is heavily n-doped and has a dopant concentration of 10.sup.19 N/cm.sup.3. A layer thickness D1 of the n.sup.+-layer 12 is between 100 m and 675 m.

[0067] The n.sup.-layer 14 is low n-doped with a dopant concentration of 10.sup.12-10.sup.16 N/cm.sup.3 and has a layer thickness D2 of 10-300 microns.

[0068] The p-type intermediate layer 15 is low p-doped with a dopant concentration of 10.sup.12-10.sup.17 N/cm.sup.3 and a layer thickness D5 between 1 micron and 50 microns.

[0069] The p.sup.+-layer 18 is heavily p-doped with a dopant concentration of 10.sup.19 N/cm.sup.3 and a layer thickness D3 greater than 2 microns.

[0070] The first defect layer 16 has a layer thickness D41 ranging between 0.5 m and 10 m and a defect density ranging between 110.sup.13 N/cm.sup.3 and 510.sup.16 N/cm.sup.3.

[0071] The illustrations of FIGS. 2 show a second embodiment of a III-V semiconductor diode, wherein the difference to the illustration of FIG. 1 is that the p+-layer 18 is formed as a substrate, followed by the further layers.

[0072] The illustration of FIGS. 3 shows a plan view of the first embodiment of an inventive III-V semiconductor diode shown in FIG. 1. In the following, only the differences to the illustration of FIG. 1 are explained.

[0073] The stacked layer structure 100 of the III-V semiconductor diode 10, consisting of the n.sup.+-substrate 12, the n.sup.-layer 14 comprising the defect layer 16, and the p.sup.+-layer 18, has a rectangular circumference and thus also a rectangular surface with the edge lengths L1 and L2. The contact surface 22 disposed on the surface of the layer sequence 100 covers only a part of the surface.

[0074] In an embodiment, the corners of the stacked layer structure 100 are rounded to avoid field strength peaks at high voltages.

[0075] In an embodiment, the surface of the stacked layer structure 100 is round. As a result, excessive increases in field strength are particularly effectively reduced. Preferably, the surface is circular or oval.

[0076] The illustration of FIGS. 4 shows a development of the III-V semiconductor diode shown in FIG. 1, wherein in contrast to the first embodiment, the p-type intermediate layer 15 of the semiconductor diode 10 has a second defect layer 24 with a thickness D42.

[0077] The layer thickness D42 of the second defect layer 24 is between 0.5 microns and 40 microns. The defect concentration is between 110.sup.13 N/cm.sup.3 and 510.sup.16 N/cm.sup.3. The distance to the top of the p-type layer is at most half the layer thickness D5 of the intermediate layer.

[0078] The illustrations of FIGS. 5 show a development of the III-V semiconductor diode from FIG. 2, wherein the p-type layer 15 of the semiconductor diode 10 has a second defect layer 24 as compared to the second embodiment.

[0079] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.