SEMICONDUCTOR DEVICE AND FABRICATION METHOD

Abstract

A semiconductor device comprising a nominally or exactly or equivalent orientation silicon substrate on which is grown directly a <100 nm thick nucleation layer (NL) of a III-V compound semiconductor, other than GaP, followed by a buffer layer of the same compound, formed directly on the NL, optionally followed by further III-V semiconductor layers, followed by at least one layer containing III-V compound semiconductor quantum dots, optionally followed by further III-V semiconductor layers. The NL reduces the formation and propagation of defects from the interface with the silicon, and the resilience of quantum dot structures to dislocations enables lasers and other semiconductor devices of improved performance to be realized by direct epitaxy on nominally or exactly or equivalent orientation silicon.

Claims

1-24. (canceled)

25. A semiconductor device comprising: a nominally or exactly (001) or equivalent orientation silicon substrate; a nucleation layer (NL) comprised of a III-V compound, other than GaP, formed directly on the substrate; and at least one layer of the same III-V compound, other than GaP, formed directly on the NL; and at least one layer containing III-V compound quantum dots.

26. A semiconductor device according to claim 25, wherein the mean thickness of the NL is less than 100 nm.

27. A semiconductor device according to claim 25, wherein the mean thickness of the NL is less than 50 nm.

28. A semiconductor device according to claim 25, wherein the NL III-V compound layer grown on the substrate is one of a GaAs layer, an InP layer or a GaSb layer.

29. A semiconductor device according to claim 25, wherein the NL III-V compound layer has a zinc blende crystal structure.

30. A semiconductor device according to claim 25, which incorporates dislocation filter layers (DFL) on nominal (001) or equivalent orientation silicon.

31. A semiconductor device according to claim 25, which incorporates one or more dislocation filter layers (DFL) based on quantum well super-lattice layers on nominal (001) silicon.

32. A semiconductor device according to claim 25, which incorporates one or more dislocation filter layers (DFL) based on quantum well super-lattice layers (SLSs), wherein each SLS is made of one or more periods of In.sub.x[X].sub.1-xAs/GaAs layers on nominal (001) silicon, wherein the SLSs comprises a compound of the formula:
In.sub.x[X].sub.1-xAs wherein: X is at least one group III element other than In; x is greater than or equal to 0; and x is less than or equal to 0.5.

33. The device of claim 32, wherein the number of repeats of SLSs is in the range of 3 to 6.

34. The device of claim 32, wherein the number of periods of In.sub.x[X].sub.1-xAs/GaAs is 5.

35. The device of claim 32, wherein X is Ga.

36. The device of claim 32, wherein the thickness of In.sub.x[X].sub.1-xAs is in the range of 8 nm to 11 nm.

37. The device of claim 32, wherein the thickness of GaAs within the In.sub.x[X].sub.1-xAs/GaAs SLS is in the range of 8 nm to 11 nm.

38. The device of claim 32, wherein the thickness of the GaAs spacer layer is in the range of 250 nm to 350 nm.

39. A semiconductor device according to claim 25, wherein one or more epitaxial growth steps are paused and the substrate temperature increased to promote annealing of epitaxial defects for III-V lasers grown on nominal (001) silicon substrates.

40. The device of claim 39, wherein the annealing temperature is in the range of 660 C. to 750 C.

41. The device of claim 39, wherein the annealing time is in the range of 1 min to 10 mins.

42. The device of claim 39, wherein the number of annealing processes is in the range of 1 to 5.

43. A quantum dot laser comprising a semiconductor device according to claim 25.

44. A quantum dot laser according to claim 43, wherein the lasing wavelength is in the range of from 1250 nm to 1350 nm.

45. A quantum dot laser according to claim 43 comprising InAs/GaAs quantum dot structures.

46. A method of fabricating a semiconductor device comprising: providing a nominally or exactly (001) orientation silicon substrate; epitaxially growing a NL comprised of a III-V compound, other than GaP, formed directly on the substrate; and epitaxially growing at least one layer of the same III-V compound, other than GaP, formed directly on the NL; and epitaxially growing at least one layer containing III-V compound quantum dots.

47. A method according to claim 46, comprising growing the NL to have a mean thickness of less than 100 nm, preferably less than 50 nm.

48. A method according to claim 46, wherein the NL is GaAs.

Description

[0014] This silicon-based QD laser has also been tested under pulsed operation, and lasing up to 120 C. was demonstrated with an output of over 130 mW at room temperature with limited self-heating as seen in FIG. 6 and FIG. 7. The poor T.sub.0 value of 32K observed here is mainly due to hole excitation out of the lasing state {C. Jin, T. Badcock, H. Liu, K. Groom, R. Royce, D. Mowbray, and M. Hopkinson, Observation and modelling of a room-temperature negative characteristic temperature 1.3-m p-type modulation-doped quantum-dot laser, IEEE J. Quantum Electron. 42(12), 1259-1265 (2006)}. It should be mentioned that the active region studied in this work is undoped. Note that p-type modulation doping of the QDs has been well established to increase the value of T.sub.0, even to T.sub.0 for GaAs-based InAs QD lasers by suppressing hole excitation {M. Sugawara and M. Usami, Quantum dot devices: Handling the heat, Nat. Photonics 3(1), 30-31 (2009)}.

[0015] These results have demonstrated the use of direct grown GaAs on nominal (001) Si substrates for silicon-based 1.3-m InAs/GaAs QDs lasers. RT cw lasing at 1.3 m is achieved with threshold current density of 425 A/cm.sup.2. With limited self-heating, we show significantly improved device performance with lasing operation over 100 C. and output from a single facet exceeding 130 mW at room temperature under pulsed operation, values which are better than conventional values for 1.3-m InAs/GaAs QD devices grown on Si substrates with a GaP nucleation layer.

Detailed Methods

[0016] Crystal Growth:

[0017] The compound semiconductor layers were grown by solid-source III-V molecular beam epitaxy (MBE). InAs/GaAs QD samples were grown on a GaAs coated silicon piece cut from standard on-axis Si (001) 300 mm substrates with an offcut angle about 0.15 towards the [110] direction. The oxide desorption was performed by thermally heating the GaAs/Si virtual substrate to a temperature of 610 C. in ultra-high vacuum exposed with a high molecular beam flux of arsenic for 8 minutes. The substrate was then cooled down to 590 C. for the growth of a 600-nm GaAs buffer and a 100 nm superlattice consisting of alternating layers of 1 nm Al.sub.0.4Ga.sub.0.6As and 1 nm GaAs. Five sets of 10-nm In.sub.0.18Ga.sub.0.82As/10-nm GaAs stained layer superlattices (five periods) followed by 350-nm GaAs were then deposited as dislocation filter layers. Thermal annealing was introduced after growth of the stained layer superlattices and prior to the 350-nm GaAs. Finally, a layer InAs/InGaAs dot-in-a-well (DWELL) laser structure, consisting of 1400 nm Si-doped Al.sub.0.4Ga.sub.0.6As bottom cladding layer, 50 nm undoped Al.sub.0.2Ga.sub.0.8As spacer and 70 nm undoped GaAs bottom waveguide layers, five periods of InAs/In.sub.0.18Ga.sub.0.82As QWELLs, 70 nm undoped GaAs and 50 nm undoped Al.sub.0.2Ga.sub.0.8As spacer top waveguide layers, 1400 nm Be-doped Al.sub.0.4Ga.sub.0.6As top cladding layer, and finally 300 nm heavily Be-doped GaAs top contact layer. Each period of InAs/In.sub.0.18Ga.sub.0.82As QWELLs consists of 2.7 MLs of InAs quantum dots sandwiched by 2 nm of In.sub.0.18Ga.sub.0.82As and 6 nm of In.sub.0.18Ga.sub.0.82As. These DWELL lasers were grown at 510 C. The five periods of DWELLs were separated by 45-nm GaAs barriers grown at 580 C. for GaAs.

[0018] Device Fabrication:

[0019] The Si-based QD laser structure was fabricated into broad-area lasers with varying stripe widths of 25 m and 50 m following standard optical lithography and wet chemical etching techniques. The top mesa was etched to about 100 nm above the active region. The top n-contact layer was etched down to the highly n-doped GaAs buffer layer just below the n-type AlGaAs cladding layer. Ti/Pt/Au and Ni/GeAu/Ni/Au were deposited on top of the etch mesa and exposed highly n-doped GaAs buffer layer to form the p- and n-contacts, respectively. After thinning the silicon substrate to 120 m, the laser bars were cleaved into the desired cavity lengths, which were then mounted on copper heatsinks and gold-wire bonded to enable testing. The final devices described here were 25 m in width and 3 mm in length, and no facet coatings were applied.

[0020] Measurements:

[0021] The surface morphology was characterized by a Nanoscope Dimension 3100 SPM atomic force microscopy (AFM) system using a standard tapping mode. The structural properties were investigated by cross-section transmission electron microscopy (TEM) using a JEOL 2010F field-emission microscope operating at 200 kV. Optical properties were measured by photoluminescence (PL) measurements excited from a 532 nm diode-pumped solid-state laser. Laser device characteristics were measured under both cw and pulsed conditions of 1 s pulse-width and 1% duty-cycle.

Other Embodiments

[0022] Although the use of superlattice DFLs has been described above, their number and design may be varied according to the dislocation density at the MOCVD/MBE epitaxy interface layer.

[0023] In the earlier described embodiments of the invention, the layer that is grown on top of the NL epilayer is GaAs. However, any suitable III-V compound could be used, such as InP, GaSb, GaAs or mixtures of the elements in these compounds. GaN is excluded from the possible III-V compounds because it has a wurtzite crystal structure, so is generally not compatible with the epilayer, which is typically of the zinc blende crystal structure. In contrast, GaAs has a zinc blende crystal structure and a similar lattice constant to AlAs, so the AlAs nucleation layer (epilayer) has close crystallographic properties to GaAs and specifically mitigates the presence of defects at the interface; consequently, active photonic structures grown on top can have enhanced properties.

[0024] Optionally, the mean thickness of the NL is at least 2.5 nm. By providing that the mean thickness of the NL is at least 2.5 nm, the prevention of threading dislocations can be improved.

[0025] Optionally, the buffer layer of the III-V compound, other than GaP, formed directly on the NL has a mean thickness of at least 100 nm.

[0026] Optionally, the silicon substrate has an offcut angle of less than 0.5 towards the direction. Optionally, the silicon substrate has a non-zero offcut angle towards the [110] direction.

[0027] The invention is not limited to a quantum dot laser on a Si substrate, but could be used for other general semiconductor structures, for example detectors, modulators or other III-V photonic devices on a Si substrate. III-V electronic devices, such as diodes and transistors could also be fabricated with the use of this invention. Applications include but are not limited to chip-to-chip optical inter-connects, solar cells, optical fibre communications (light emitters and detectors).

[0028] In a method embodying the present invention, the NL can be grown at a relatively low temperature, because it is relatively thin. This can be advantageous in lowering the quality of any interfacial defects. Preferably, it is grown at a temperature below 500 C. A suitable temperature range is from 300 C. to 500 C., and is exemplified in the description above at 400 C.

[0029] In the detailed method described above, the crystal growth is by both MOCVD and MBE, but it could also be done by any combination of these techniques or by chemical vapour deposition (CVD) or by other epitaxy techniques.

[0030] Semiconductor devices and fabrication methods have been described above with reference to various specific embodiments and examples. However, it is to be understood that the claims below are in no way limited to these specific embodiments and examples.