Half bridge resonant converters, circuits using them, and corresponding control methods

Abstract

A half bridge resonant converter comprises a half bridge inverter having a high side switch and a low side switch with an output defined from a node between the high side switch and the low side switch. The output connects to a resonant circuit. There are separate control circuits for generating the gate drive signals for controlling the switching of the high side switch and low side switch, in dependence on an electrical feedback parameter, each with different reference voltage supplies.

Claims

1. A half bridge resonant converter, comprising: a pair of DC voltage lines arranged to provide a bus voltage, wherein the pair of DC voltage lines comprises a high voltage line and a low voltage line; a half bridge inverter in series between the high voltage line and the low voltage line, wherein the half bridge inverter comprises a high side switch and a low side switch, wherein an output of the half bridge inverter is defined from a switch node between the high side switch and the low side switch; a resonant circuit coupled to the output of the half bridge inverter; a first control circuit for generating a first gate drive signal for controlling switching of the high side switch, wherein the first control circuit is arranged to control a duty cycle of the high side switch by increasing an on-time of the high side switch if an average switch node voltage is lower than a fraction of the bus voltage and by decreasing the on-time of the high side switch if the average switch node voltage is higher than the fraction of the bus voltage; and a second control circuit for generating a second gate drive signal for controlling switching of the low side switch in dependence on an electrical feedback parameter.

2. The half bridge resonant converter as claimed in claim 1 wherein the first control circuit is arranged to turn on the high side switch after the low side switch is turned off and a dead-time has elapsed.

3. The half bridge resonant converter as claimed in claim 1 wherein the second control circuit is arranged to turn on the low side switch after the high side switch is turned off and a dead-time has elapsed.

4. The half bridge resonant converter as claimed in claim 1 wherein the second control circuit is arranged to control at least one of an output power and a power factor of the half bridge resonant converter by controlling the low side switch.

5. The converter as claimed in claim 1, wherein the first control circuit comprises: a first end of slope detection circuit having the high voltage line as an input; a first latch element triggered by the end of slope detection circuit and which generates a first control signal for switching the high side switch to a first state; and a first signal generator for generating a second control signal for switching the high side switch to a second state.

6. The converter as claimed in claim 5, wherein the first signal generator has a reference input for controlling a duration of the first state.

7. The converter as claimed in claim 1, wherein the second control circuit comprises: a second end of slope detection circuit having the switch node as an input; a second latch element triggered by the second end of slope detection circuit and which generates a third control signal for switching the low side switch to a first state; and a second signal generator for generating a fourth control signal for switching the low side switch to a second state.

8. The converter as claimed in claim 7, wherein the second signal generator has a feedback control input for controlling a duration of the first state in dependence on the electrical feedback parameter.

9. The converter as claimed in claim 1, wherein the electrical feedback parameter comprises a voltage which is dependent on an output current delivered by the converter to a load.

10. The converter as claimed in claim 1, wherein the resonant circuit comprises an LLC circuit.

11. The converter as claimed in claim 1, wherein the first circuit and the second control circuits each comprises an integrated circuit.

12. An apparatus comprising: the half bridge resonant converter as claimed in claim 1; and an output load.

13. The apparatus as claimed in claim 12 wherein the output load is an LED arrangement of one or more LEDs.

14. A conversion method, comprising: operating a half bridge inverter comprising a high side switch and a low side switch between a DC high voltage line and a DC low voltage line providing a bus voltage, using a gate drive signal and providing an output from a switch node between the high side switch and the low side switch; providing the output of the half bridge inverter to a resonant circuit; generating a first gate drive signal using a first control circuit, for controlling a duty-cycle of the high side switch by increasing an on-time of the high side switch if an average switch node voltage is lower than a fraction of the bus voltage and by decreasing the on-time of the high side switch if the average switch node voltage is higher than the fraction of the bus voltage; and generating a second gate drive signal using a second control circuit, for controlling switching of the low side switch in dependence on an electrical feedback parameter.

15. The method as claimed in claim 14, further comprising generating a first supply voltage from a high voltage line and from a voltage at the switch node, and generating a second supply voltage from the low voltage line and from the voltage at the switch node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Examples of the invention will now be described in detail with reference to the accompanying drawings, in which:

(2) FIG. 1 shows the general architecture of a half bridge resonant converter;

(3) FIG. 2 shows one more specific example of a half bridge resonant converter used in a resonant AC/DC converter which forms a PFC stage;

(4) FIG. 3 shows another more specific example of a half bridge resonant converter used in a resonant DC/DC converter;

(5) FIG. 4 shows a first known level shifting arrangement for generating gate drive signals;

(6) FIG. 5 shows a second known level shifting arrangement for generating gate drive signals;

(7) FIG. 6 shows an example of a circuit in accordance with the invention, in schematic form;

(8) FIG. 7 shows an example of a circuit in accordance with the invention, in more detail;

(9) FIG. 8 shows an example of the implementation of the high side control circuit;

(10) FIG. 9 shows a timing diagram for the operation of the circuit of FIG. 8;

(11) FIG. 10 shows an example of the implementation of the low side control circuit;

(12) FIG. 11 shows a timing diagram for the operation of the circuit of FIG. 10;

(13) FIG. 12 shows an example of the implementation of the high side supply generation circuit; and

(14) FIG. 13 shows an example of the implementation of the low side supply generation circuit.

(15) FIG. 14 shows another example of AC/DC LLC converter circuit which may use a converter of the invention; and

(16) FIG. 15 shows the controller in FIG. 14 in more detail for a single threshold voltage implementation.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(17) The invention provides a half bridge resonant converter comprising a half bridge inverter having a high side switch and a low side switch with an output defined from a switch node between the high side switch and the low side switch. The output connects to a resonant circuit. There are separate control circuits for generating the gate drive signals for controlling the switching of the high side switch and low side switch, in dependence on an electrical feedback parameter, each with different reference voltage supplies.

(18) FIG. 6 shows converter using a half bridge topology with an LLC resonant tank circuit 25 and a full wave rectifier 32 controlled by two local control circuits.

(19) The converter is supplied by a pair of DC voltage lines comprising a DC high voltage line 60 (node B) and a low voltage line 62, e.g. ground. As in the examples above, the half bridge inverter comprises a high side switch 28 and a low side switch 30 in series between the high voltage line 60 and the low voltage line 62. The output of the half bridge inverter is defined from the switch node X between the high side switch and the low side switch.

(20) A first control circuit 64 generates a gate drive signal for controlling the switching of the high side switch 28 in dependence on an electrical feedback parameter (as discussed below). The first control circuit 64 has as its reference voltage supply the voltage at the switch node X and a first supply voltage 65 greater than the voltage at the switch node X. As explained below, the first supply voltage is generated from the main power supply before the circuit is oscillating but it is generated by feedback from the resonant circuit during oscillation, thereby saving power.

(21) A second control circuit 66 generates a gate drive signal for controlling the switching of the low side switch 30, again in dependence on the electrical feedback parameter, wherein the second control circuit 66 has as its reference voltage supply the low voltage line 62 and a second supply voltage 67 greater than the voltage at the low voltage line. Again, the second supply voltage is generated from the main power supply before the circuit is oscillating but it is generated by feedback from the resonant circuit during oscillation, thereby saving power.

(22) The feedback may directly control the timing of only one of the switches. However, it will then indirectly control the other in that there is a switching sequence between the two switches. Thus, the overall control block 31 may be considered to be the combination of the control circuits 64 and 66, and feedback control (shown as input FB) is used by the controller. The switching frequency is typically controlled, either based on a frequency control circuit or based on threshold detection of a self-oscillating resonant tank circuit 25.

(23) This arrangement avoids the need for a level shifter transformer and also enables high frequency operation by using separate low voltage circuitry locally connected to both switches.

(24) FIG. 7 shows an implementation of the circuit in more detail.

(25) A first generating circuit 70 is used for generating the first supply voltage 65 from the high voltage line 60 and from the voltage at the switch node X. A second generating circuit 72 is used for generating the second supply voltage 67 from the low voltage line 62 and from the voltage at the switch node X.

(26) The first generating circuit 70 has a first input 71 for receiving a voltage SUP.sub.HS between the switch node X (Vx) and the resonant circuit. As shown, this high side supply voltage SUP.sub.HS is derived from a switch node between a series output capacitor 74 and the resonant circuit.

(27) Capacitors 74 and 76 function as a capacitive voltage divider with respect to the resonant capacitor Cs. If for example the peak to peak voltage across Cs is 500V and Cs is 1 nF, the capacitor 74 may be about 20 nF to achieve a maximum voltage drop of about 25V for the supply, which practically turns into a lower value at the first supply voltage 65 (LV.sub.HS) depending on the charge pump impedances (the charge pump is explained below with reference to FIG. 12) and the load. The voltage SUP.sub.HS is an AC voltage with respect to the switch node X.

(28) This voltage is used to generate the power supply for controlling the switching of the high side switch, once the circuit is oscillating.

(29) The second generating circuit 72 has a second input 73 for receiving a low side supply voltage SUP.sub.LS between the resonant circuit and the low voltage line 62. In particular this low side supply voltage SUP.sub.LS is derived from a switch node between the resonant circuit and a low side series capacitor 76, which capacitor then connects to the low voltage line 62.

(30) This voltage is used to generate the power supply for controlling the switching of the low side switch, once the circuit is oscillating.

(31) This arrangement achieves valley switching by using an end-of-slope trigger action as explained in more detail below. This is implemented using a capacitor 78 (C.sub.ONHS) between the high voltage line 60 and the first control circuit 64, and a capacitor 79 (C.sub.ONLS) between the switch node X and the low side control circuit 66.

(32) The high side control circuit 64 receives power from the resonant tank circuit by means of the capacitor 74 and from the first generating circuit 70, and the low side control circuit 66 receives power from the resonant tank circuit by means of the capacitor 74 and the second generating circuit 72. Both local supplies need to be powered by alternative means before the start-of-oscillation occurs, and this requires a high voltage transistor for each. These high voltage transistors reside inside the generating circuits 70, 72 as shown below.

(33) All the circuitry described may be implemented using low voltage discrete components, low voltage ICs or a combination of both, except for the end-of-slope sense capacitors 78, 79 and the high voltage supply transistor inside each generating circuit.

(34) The capacitor arrangement (C.sub.ONHS, C.sub.ONLS) is used to ensure that the power switch will be switched on at the minimum voltage across its own (parasitic) output capacitance. This implies zero voltage switching when there is a sufficiently large current at the moment of switch-off of the complementary power switch.

(35) Communication between the high side and low side drive circuit is established using the switch node voltage (Vx) information and by means of resistors R.sub.SS1 and R.sub.SS2. These form a potential divider between the high voltage line and the low voltage line, providing a 1:2 division of the voltage at terminal B. The output is used as a reference with which the average switch node voltage is compared, and the average is thus controlled to be half of the voltage at node B. This provides balancing control.

(36) The on-signal is not directly transmitted but the previous off-signal causes the switch node commutation which in turn is sensed by the other voltage domain. Secondly, the switch node average voltage is explicitly controlled by one domain which implies the same on-time as the other domain but without direct transmission of any on-time signal between the voltage domains.

(37) In the example shown, the voltage generated by the resistors R.sub.SS1 and R.sub.SS2 is used to control the on-time of the high side) switch 28. The on-time of the lower switch is then controlled by means of a feedback system. A feedback voltage V.sub.CTRL is compared with a reference level V.sub.SET to provide error based feedback control. In this example, the feedback voltage V.sub.CTRL is proportional to the output current I.sub.OUT of the converter. The output current I.sub.OUT supplies the LED string, connected between LED+ and LED, and the output filter capacitor C.sub.DC which provides 100 Hz ripple reduction.

(38) Note that the roles of the lower switch and upper switch control may be exchanged.

(39) The feedback voltage is the voltage across an output resistor ROUT in response to the output current I.sub.OUT and the voltage V.sub.CTRL is controlled to be equal to the reference V.sub.SET. This control loop thus controls the output current of the converter I.sub.OUT.

(40) The advantages of using these local drive circuits are that only cheap and fast low voltage components are involved to control and drive the local power switch except for a small and inexpensive capacitor of a few pF across each power switch, for example a 500V capacitor (i.e. the capacitors 78, 79). This results in automatic ZVS (Zero Voltage Switching) or VS (Valley Switching) for both power switches. Additionally, a simple and cheap local supplementary low voltage supply is derived from the resonant tank circuit using low voltage components. The initial supply voltage before start-of-oscillation can then be supplied e.g. via a low cost 500V BJT (Bipolar Junction Transistor) capable of handling a few mA. A MOSFET may instead be used.

(41) Except for a few high voltage components, the local control circuitry can be integrated using a low voltage IC process (e.g. 10V to 25V). The same IC may be used twice for driving the high side and low side gate. The respective control task can be selected e.g. via external components.

(42) FIG. 8 shows an implementation of the high side (first) control circuit 64 and FIG. 9 shows the operation using waveforms.

(43) The first control circuit comprises a first end of slope detection circuit 80 having as input the high voltage line (node B). A first latch element 82, in this example in the form of a D-type flip flop, is triggered by the end of slope detection circuit 80 and generates a first control signal HS_ON for switching the high side switch to a first, ON, state. It is provided to the clock input of the flip flop.

(44) A first signal generator 84 is used for generating a second control signal HS_OFF for switching the high side switch to a second state. Its inverse is provided to the (inverse) reset input of the flip flop 82. The first signal generator 84 has a reference input from the resistive divider R.sub.SS1, R.sub.SS2 for controlling the duration of the first state.

(45) In this way, the high side control circuit 64 uses an end-of-slope detection mechanism formed by the capacitor 78 and a diode and resistor circuit (D.sub.NEG, D.sub.POS, D.sub.OFF and R.sub.CLK) which triggers the positive edge triggered flip flop 82 ON at the end of the negative slope of V.sub.B,X (i.e. V.sub.B relative to V.sub.X) and switches the high side power switch 28 on via the output from flip flop 82, GATE_HS.

(46) The high side power switch 28 is switched off by means of the control signal HS_OFF in a manner which provides balancing.

(47) FIG. 9 shows the control signals arising in the circuit.

(48) The first positive pulse of V.sub.B,X is with the high side OFF and low side ON, so that V.sub.X is pulled down by the low side switch hence V.sub.B is greater than V.sub.X. The low side switch is turned ON only after the high side switch as turned OFF, as shown.

(49) The start of the negative slope in the voltage V.sub.B,X (caused by turning the low side off, LS_OFF) pulls down HS_ON (relative to the voltage at switch node X), and the next rising edge only arises at the end of the slope. Once the high side switch is ON there is the dip to zero in the voltage V.sub.B,X.

(50) FIG. 10 shows an implementation of the low side (second) control circuit 66 and FIG. 11 shows the operation using waveforms.

(51) The second control circuit comprises a second end of slope detection circuit 90 having as input the switch node X. A second latch element 92, again in the form of a positive edge triggered D-type flip flop, is clocked by the end of slope detection circuit 90 and it generates a third control signal LS_ON for switching the low side switch to a first, ON, state.

(52) A second signal generator 94 is used for generating a fourth control signal LS_OFF for switching the low side switch to a second state. Its inverse is provided to the (inverse) reset input of the flip flop 92. The second signal generator 94 receives the feedback control input VC FRL for controlling the duration of the first, ON, state in dependence on the feedback.

(53) The low side control circuit 66 thus also uses an end-of-slope detection mechanism formed by the capacitor 79 and a diode and resistor circuit (D.sub.NEG, D.sub.POS, D.sub.OFF and R.sub.CLK) which triggers the positive edge triggered flip flop ON at the end of the negative slope on the switch node voltage V.sub.X and switches the low side power switch 30 ON via the flip flop output GATE_LS.

(54) FIG. 11 shows the control signals arising in the circuit.

(55) The first dip in V.sub.X is with the high side OFF and low side ON, so that V.sub.X is pulled down by the low side switch.

(56) The start of the negative slope in the voltage V.sub.X (caused by turning the high side off, HS_OFF seen in FIG. 9) pulls down LS_ON, and the next rising edge only arises at the end of the slope. Once the low side switch is ON there is the dip to zero in the voltage V.sub.X. The rise in the voltage at switch node X is triggered by the LS_OFT signal which turns off the low side switch, with timing based on feedback control implemented by the second signal generator 94.

(57) FIG. 12 shows the first (high side) generating circuit. It comprises a supply transistor 120 between the high voltage line (node B) and the output LV.sub.HS of the first generating circuit. A charge pump circuit 122 is used for converting the AC voltage SUP.sub.HS at the first input into a DC voltage and storing it on a first output capacitor Co as the output of the first generating circuit at the first supply voltage. The low voltage rail for the circuit is the switch node X.

(58) The second (low side) generating circuit is the same but operates in a different voltage domain. It has a supply transistor 130 between the switch node X and the output LV.sub.LS of the second generating circuit.

(59) A charge pump circuit 132 is used for converting the AC voltage at the second input SUP.sub.LS into a DC voltage and storing it on a second output capacitor Co as the output of the second generating circuit at the second supply voltage. The low voltage rail for the circuit is the low voltage line 62.

(60) Thus, in both cases, the local power supply has a high voltage low current transistor (BJT or MOSFET) which charges an output capacitor Co before the start-of-oscillation occurs. The gate signal to the transistor GATE_LS GATE_HS is controlled to switch off the transistor when oscillation starts.

(61) In this way, the transistor may be considered to be a primary supply for startup, and the feedback from the resonant circuit provides a secondary supply which is used once the circuit is in oscillation.

(62) The charge pump converts the AC peak-to-peak voltage across the input capacitor (C.sub.SL or C.sub.SH) to a DC voltage across Co. A Zener function, represented by diode 124, 134, limits the output voltage in case of excessive supply.

(63) As mentioned above, the converter may be used within an AC/DC converter, a DC/DC converter or a DC/AC converter. It may be used in a front end PFC circuit.

(64) The front end PFC application of an LLC converter poses several problems for the feedback control of the inverter switch arrangement, which cannot be mastered by the conventional frequency control approach. This mainly has to do with the high gain ratio requirements. The gain ratio is the ratio between the maximum and the minimum gain.

(65) The gain ratio problem can be relaxed if instead of the switching frequency, a threshold for an LLC state variable is used as the manipulating variable for controlling the input current. For example a threshold voltage may be set for the capacitor voltage across the capacitor of the LLC tank. Alternatively, the transformer voltage, or the transformer input current can also be used.

(66) FIG. 14 shows an AC/DC LLC converter circuit using the capacitor voltage as the control variable.

(67) As in FIG. 1, the circuit has an AC mains input 10 followed by a rectifier 12. The switches 28, 30 of the half bridge inverter are controlled by a gate driver 140 which is controlled by a controller 142. The controller outputs a gate drive signal GS.

(68) The controller is provided with a threshold value which in this example is the threshold (or reference) capacitor voltage vC_ref. The controller 142 receives the measured quantity i.e., the actual resonant capacitor voltage vC, and processes the switching scheme for the gate driver 140 that in turn controls the inverter 28, 30 and the switch node voltage Vx, i.e. the voltage at the output of the half bridge inverter.

(69) The controller thus has an outer control loop 144 for setting a threshold level for the electrical feedback parameter (the capacitor voltage) in dependence on the output voltage vo in this example and the input voltage and current vm, im, and an inner control loop 142 for comparing the electrical feedback parameter with the threshold to derive the gate drive signal.

(70) The outer control loop 144 implements output control as well as implementing PFC, and the inner control loop 142 derives the switching control signal.

(71) FIG. 15 shows the controller 142 in more detail. The measured capacitor voltage vC is compared with the reference vC_ref by comparator 150, and the comparison result is used to reset a flip flop 152 which generates the output for the gate driver 140. A delay element 154 provides a delayed set pulse so that the reset operation has a fixed duration (which is a function of the clocking speed of the flip flop).

(72) This feedback system comprises a high frequency control loop implemented by the inner control loop 142.

(73) The outer low frequency controller 144 receives the mains voltage vm, the actual mains current im and output voltage vo and its set point vo_ref and processes, in accordance with the power factor needs, the manipulating value of vC_ref for the switching unit.

(74) In this example, there is only one threshold value (vC_ref) that is compared to a state variable (here vC). If the state variable exceeds the threshold, the flip-flop 152 in the controller 142 is reset and the inverter is switched off via the gate driver, i.e., the switch node voltage is set to its minimum value.

(75) The inverter is switched on again a certain time after the switch off event. This time adapted to result in a symmetric operation i.e., at a duty cycle of the switch node of 0.5.

(76) The capacitor voltage is one example of state variable which is used as a control input for the control of the inverter switching. An alternative state variable is the transformer voltage. The scheme is similar but signs have to be changed. For example, if a threshold is exceeded the flip flop 152 in the controller 142 has to be switched on.

(77) In another scheme, there are two thresholds. The inverter is switched off (on) once the state variable exceeds a first upper threshold and the inverter is switched on (off) if the state variable passes a second threshold. Here, the second threshold is a function of the first threshold and the input voltage.

(78) In this way, the control circuit is adapted to set a first threshold of the electrical feedback parameter for turning on the gate drive signal and a second threshold of the electrical feedback parameter for turning off the gate drive signal.

(79) Instead of using a transformer as isolation means, isolating capacitors may be used as well. For example, by using an extra isolating (e.g. DC blocking) capacitor between the inverter switch node and the transformer, and another between the other primary side winding terminal and the midpoint of the resonant capacitors.

(80) Alternatively, in order to save components, the resonant capacitors can also be designed for isolating from the mains voltage (Y-capacitors). Here the above mentioned state variable (vC) cannot be accessed directly any longer but can be derived by measuring and integrating the current into the isolating capacitors.

(81) In any of these configurations, the transformer need not to be isolating and can be simplified, depending on the end use of the circuit.

(82) There are various drive schemes that may be used for driving the high side and low side switches. Furthermore, the resonator may be self-oscillating or it may be driven by a frequency control circuit.

(83) In general, a control scheme is required to drive the switches 28, 30 into their on- and off-states such that the output voltage or current is regulated to a certain desired value or range of values and for a PFC circuit also to implement power factor correction.

(84) In order to exploit best the powertrain and to achieve the maximum efficiency, it is desired to operate the converter symmetrically (at least at full load) and to load the transformer and the rectifier in the secondary side equally. In the case of a transformer with center-tapped output windings that are symmetric in terms of turn-ratios and leakages, secondary side symmetry can be assured if the duty cycle of the half-bridge (i.e., its switch node) is kept at 50%.

(85) There are basically four transitions that the control scheme must handle:

(86) 1. Turn-on of the high-side MOSFET 28;

(87) 2. Turn-on of the low-side MOSFET 30;

(88) 3. Turn-off of the high-side MOSFET 28;

(89) 4. Turn-off of the low-side MOSFET 30.

(90) There are several known schemes that may be used in order to achieve this.

(91) A. Von-Voff is a control scheme where transition number 4 is initiated when some state variable crosses a certain threshold voltage (Von). Following this, the control waits for a certain time (i.e., the dead-time) before starting transition 1. This dead-time ensures that cross-conduction, or shoot-through, does not occur. The half-bridge is now in the on-state. Eventually, either the same or a different state variable will cross a second threshold (Voff), and transition number 3 will be initiated. As with the transition to the half-bridge on-state, there will then be a dead-time before transition number 2 is initiated. The half-bridge is now in the off-state, and then the procedure continues from the beginning once more. The actual values of the two thresholds are determined by an outer control loop in order to yield the correct output. This is a Von-Voff scheme in that voltage threshold controls the switching on and off.
B. Von-Ton is a control scheme where transition number 4 is initiated when some state variable crosses a certain threshold voltage (Von). As in case A, the dead-time is allowed to pass before starting transition number 1. Transition number 3 is initiated based on a certain time interval elapsing. This may be a fixed interval, or a controlled interval. After the dead-time has then elapsed, transition number 2 is initiated, and then the procedure continues from the beginning once more. The actual value of the voltage threshold is determined by an outer control loop in order to yield the correct output, and the time threshold may be fixed or controlled dynamically. This is a Von-Ton scheme in that a voltage threshold controls the turning on (after a dead time) and the time duration of the on period of the half bridge is then controlled.
C. Voff-Toff is similar to case B, except that the voltage and time thresholds define the off and on transitions of the half-bridge, respectively. Transition number 3 is initiated when some state variable crosses a certain threshold voltage (Voff). The dead-time is allowed to pass before starting transition number 2. Transition number 4 is initiated based on a certain time interval elapsing. After the dead-time has then elapsed, transition number 1 is initiated, and then the procedure continues from the beginning once more. As in case B, the actual value of the voltage threshold is determined by an outer control loop in order to yield the correct output, and the time threshold may be fixed or controlled dynamically. This is a Voff-Toff scheme in that a voltage threshold controls the turning off and the time duration of the off period of the half bridge is controlled (i.e. between turning off the high-side MOSFET and turning it on again after the time duration and dead-time).

(92) In cases B and C, it is most often desirable to control the on or off time such that it matches the off or on time respectively, i.e., it is usually beneficial to operate with a 50% duty cycle as mentioned above. There is no level shifter, gate drive transformer or any other means that could send synchronized signals between the first and second voltage domain of the first and second local control circuit. In order to yet allow constant duty cycle operation, the first control circuit (64) controls the duty-cycle via controlling the average switch node voltage (Vx) to be for example a fraction, preferably half, of the bus voltage. This is achieved by increasing the on-time of the high side switch if the measured and filtered switch node voltage (x) is lower than half the bus voltage and decreasing the on-time of the high side switch if the measured and filtered switch node voltage (x) is higher than half the bus voltage.

(93) In summary, the four switching signals that have to be generated per cycle can be divided into two groups: The two turn-on signals may be considered as slave signals that are generated in response to the two master (i.e., turn-off) signals. The turn-on of the high side switch follows the turn-off of the low side switch after a certain dead time and the turn-on of the low side switch follows the turn-off of the high side switch after a certain dead time. The synchronization is achieved by observing the switch node voltage transition by means of the end-of-slope-detection circuits. In contrast, the master signal of the first control circuit for controlling the switching of the high side switch is generated based on the filtered (average) switch node voltage (Vx). Thus, Vx is used in two manners in order to synchronize the switching of the two voltage domains; in terms of the two transients (high to low and low to high) and of the average value of Vx. The second master signal (and thus, the remaining fourth required switching signal) is generated by the second control circuit (84) for controlling the switching of the low side switch and is based on the electrical feedback parameter from the converter input or output in order to provide the control of the converter's power factor and/or output voltage or current. This signal determines the switching frequency, which either is generated explicitly in case of a frequency control or implicitly, in case of a threshold detection of a self-oscillating resonant tank circuit.

(94) In other cases, it is beneficial to operate with a defined duty cycle that is different from 50% in order to enlarge the output voltage or current window that the converter is capable of handling.

(95) For threshold-based resonant converters (such as a self-oscillating LLC converters), there is no oscillator present in the circuit. Threshold-based switching has a particular advantage with regards to the linearity of the transfer function when using the converter to cover a wide range of input and output operating conditions, such as in an LLC PFC for example, and frequency control is not feasible in such cases due to extreme variations in the gain that cannot easily be handled.

(96) The approach to the generation of the required voltages for switching the high side and low side power switches as explained above may be used in all of these situations.

(97) The invention may be used in various applications, such as LED drivers in general, and in particular front end (isolating) converters for standalone drivers (indoor and outdoor), particularly miniaturized or flat types, offline drivers for track lighting, emergency lighting drivers, and miniature, isolating single stage LED drivers. The converter may also be used in single-stage separated extra low voltage (SELV) power converters for fixed output voltages and generally in consumer and office electronics applications such as laptop adapters.

(98) Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.