Power convertor

Abstract

This power conversion device includes: a rectification circuit; an inverter circuit having a full-bridge configuration, and having a DC capacitor, and first and second legs each of which has two switching elements connected in series to each other; a transformer; and a control circuit for controlling operation of the inverter circuit, wherein the control circuit controls an ON period for the first leg, thereby controlling increase/decrease in current flowing through a first rectification circuit from an AC input, and controls an ON period for the second leg and a phase shift amount between the ON period for the first leg and the ON period for the second leg, thereby controlling voltage of the DC capacitor to be constant. Thus, it becomes possible to achieve high-power-factor control and output power control at the same time by a single stage of full-bridge inverter circuit.

Claims

1. A power conversion device comprising: a first rectification circuit which rectifies AC power inputted from an AC power supply; an inverter circuit having a first leg, a second leg, and a DC capacitor connected in parallel to each other, the first leg having a first switching element and a second switching element connected in series to each other by way of a first AC end, a positive-side DC terminal of the first rectification circuit being connected via a reactor to the first AC end which is a connection point between the first switching element and the second switching element, the second leg having a third switching element and a fourth switching element to which diodes are respectively connected in antiparallel, the third switching element and the fourth switching element being connected in series to each other, the inverter circuit having a negative-side DC bus connected to a negative-side DC terminal of the first rectification circuit; a transformer having a primary winding and a secondary winding, one end of the primary winding being connected to the first AC end of the inverter circuit, and another end of the primary winding being connected to a second AC end which is a connection point between the third switching element and the fourth switching element; a second rectification circuit having one end connected to the secondary winding of the transformer and another end connected to a DC load via a smoothing capacitor, the second rectification circuit rectifying AC power inputted from the transformer, and outputting the rectified AC power to the DC load; a control circuit which controls operation of the inverter circuit; a voltage detector which detects DC voltage of the DC capacitor; and a current detector which detects current outputted from the first rectification circuit, wherein the control circuit determines an ON period for the first leg on the basis of a detection result of the current detector, and controls the first switching element and the second switching element on the basis of the determined ON period for the first leg, thereby controlling current outputted from the first rectification circuit, and on the basis of a detection result of the voltage detector and the determined ON period for the first leg, the control circuit controls an ON period for the second leg and a phase shift amount between the ON period for the first leg and the ON period for the second leg, thereby controlling voltage of the DC capacitor to be constant, and wherein the control circuit controls the ON period for the first leg so that current outputted from the first rectification circuit becomes predetermined target sinewave current, and the control circuit controls the phase shift amount and the ON period for the second leg so that voltage of the DC capacitor becomes target voltage which is higher than peak voltage of AC voltage inputted from the AC power supply.

2. The power conversion device according to claim 1, wherein the control circuit uses: a first operation mode in which the first switching element and the fourth switching element are turned on; a second operation mode in which the first switching element and the third switching element are turned on; a third operation mode in which the second switching element and the third switching element are turned on; and a fourth operation mode in which the second switching element and the fourth switching element are turned on, and the control circuit controls respective periods of the first to fourth operation modes in this order, thereby controlling the inverter circuit.

3. The power conversion device according to claim 1, wherein the control circuit uses: a first operation mode in which the first switching element and the fourth switching element are turned on; a second operation mode in which the first switching element and the third switching element are turned on; a third operation mode in which the second switching element and the third switching element are turned on; and a fourth operation mode in which the second switching element and the fourth switching element are turned on, and the control circuit controls the inverter circuit, using a first operation sub mode in which respective periods of the first to fourth operation modes are controlled in this order, and a second operation sub mode in which the respective periods are controlled in order of the fourth operation mode, the third operation mode, the fourth operation mode, and then the first operation mode.

4. The power conversion device according to claim 1, wherein the control circuit controls the phase shift amount between the ON period for the first leg and the ON period for the second leg, using, as an upper limit, the smaller one of two ON periods of the first switching element and the second switching element.

5. The power conversion device according to claim 1, wherein the control circuit synchronizes timings of shifting phases for the third switching element and the fourth switching element, with each other.

6. The power conversion device according to claim 1, wherein the control circuit controls the ON periods for the first leg and second leg and the phase shift amount for the second leg so that a period during which an ON period of the first switching element and an ON period of the fourth switching element which is diagonal thereto overlap each other, and a period during which an ON period of the second switching element and an ON period of the third switching element which is diagonal thereto overlap each other, become equal to each other.

7. The power conversion device according to claim 6, further comprising a smoothing reactor connected to a DC terminal of the second rectification circuit, wherein the control circuit controls the ON period for the second leg on the basis of a voltage value of the DC capacitor, a voltage value of the smoothing capacitor, a current value of the smoothing reactor, a calculated value of a duty cycle for the first switching element, a duty cycle for the second switching element, and a calculated value of the phase shift amount for the second leg.

8. The power conversion device according to claim 6, further comprising a smoothing reactor connected to a DC terminal of the second rectification circuit, wherein the control circuit controls the ON period for the first leg on the basis of a voltage value of the DC capacitor, a voltage value of the smoothing capacitor, a current value of the smoothing reactor, a calculated value of a duty cycle for the first switching element, a duty cycle for the second switching element, and a calculated value of the phase shift amount for the second leg.

9. The power conversion device according to claim 1, wherein the control circuit controls the first switching element and the second switching element so that their ON and OFF states are inverted relative to each other, and in an initial state in which the phase shift amount is zero, the control circuit controls a gate pulse width and a phase for the third switching element to be equal to those for the first switching element, and controls a gate pulse width and a phase for the fourth switching element to be equal to those for the second switching element.

10. The power conversion device according to claim 9, wherein the control circuit uses saw-tooth waves as carrier waves for the first leg and the second leg, and the control circuit performs control such that, as the phase shift amount increases, a phase of rising of a gate pulse for the third switching element is shifted relative to a phase of rising of a gate pulse for the first switching element while an ON period of the third switching element is made equal to an ON period of the first switching element, and a phase of rising of a gate pulse for the fourth switching element is shifted relative to a phase of rising of a gate pulse for the second switching element while an ON period of the fourth switching element is made equal to an ON period of the second switching element.

11. The power conversion device according to claim 9, wherein the control circuit uses triangular waves as carrier waves for the first leg and the second leg, and the control circuit performs control such that, as the phase shift amount increases, a phase of rising of a gate pulse for the third switching element is shifted relative to a phase of rising of a gate pulse for the first switching element while an ON period of the third switching element is made equal to an ON period of the first switching element, and a phase of rising of a gate pulse for the fourth switching element is shifted relative to a phase of rising of a gate pulse for the second switching element while an ON period of the fourth switching element is made equal to an ON period of the second switching element.

12. The power conversion device according to claim 1, wherein the control circuit controls the first switching element and the second switching element so that their ON and OFF states are inverted relative to each other, and in an initial state in which the phase shift amount is zero, the control circuit controls a gate pulse width and a phase for the third switching element to be equal to those for the second switching element, and controls a gate pulse width and a phase for the fourth switching element to be equal to those for the first switching element.

13. The power conversion device according to claim 12, wherein the control circuit uses saw-tooth waves as carrier waves for the first leg and the second leg, and the control circuit performs control such that, as the phase shift amount increases, a phase of rising of a gate pulse for the third switching element is shifted relative to a phase of rising of a gate pulse for the second switching element while an ON period of the third switching element is made equal to an ON period of the first switching element, and a phase of rising of a gate pulse for the fourth switching element is shifted relative to a phase of rising of a gate pulse for the first switching element while an ON period of the fourth switching element is made equal to an ON period of the second switching element.

14. The power conversion device according to claim 12, wherein the control circuit uses triangular waves as carrier waves for the first leg and the second leg, and the control circuit performs control such that, as the phase shift amount increases, a phase of rising of a gate pulse for the third switching element is shifted relative to a phase of rising of a gate pulse for the second switching element while an ON period of the third switching element is made equal to an ON period of the first switching element, and a phase of rising of a gate pulse for the fourth switching element is shifted relative to a phase of rising of a gate pulse for the first switching element while an ON period of the fourth switching element is made equal to an ON period of the second switching element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a configuration diagram of a power conversion device shown in embodiment 1 of the present invention.

(2) FIG. 2 is a diagram illustrating operations of switching elements in the power conversion device shown in embodiment 1 of the present invention.

(3) FIG. 3 is a diagram showing a current route in the power conversion device shown in embodiment 1 of the present invention.

(4) FIG. 4 is a diagram showing a current route in the power conversion device shown in embodiment 1 of the present invention.

(5) FIG. 5 is a diagram showing a current route in the power conversion device shown in embodiment 1 of the present invention.

(6) FIG. 6 is a diagram showing a current route in the power conversion device shown in embodiment 1 of the present invention.

(7) FIG. 7 is a diagram showing the operation principle of the power conversion device shown in embodiment 1 of the present invention.

(8) FIG. 8 is a diagram showing the operation principle of the power conversion device shown in embodiment 1 of the present invention.

(9) FIG. 9 is a diagram showing a control system of the power conversion device shown in embodiment 1 of the present invention.

(10) FIG. 10 is a diagram showing the control system of the power conversion device shown in embodiment 1 of the present invention.

(11) FIG. 11 is a diagram showing the control system of the power conversion device shown in embodiment 1 of the present invention.

(12) FIG. 12 is a diagram showing the control system of the power conversion device shown in embodiment 1 of the present invention.

(13) FIG. 13 is a diagram showing the operation principle of the power conversion device shown in embodiment 1 of the present invention.

(14) FIG. 14 is a diagram showing the control system of the power conversion device shown in embodiment 1 of the present invention.

(15) FIG. 15 is a diagram showing the control system of the power conversion device shown in embodiment 1 of the present invention.

(16) FIG. 16 is a block diagram showing the hardware configuration of a control circuit shown in embodiment 1 of the present invention.

(17) FIG. 17 is a diagram showing the operation principle of a power conversion device shown in embodiment 2 of the present invention.

(18) FIG. 18 is a diagram showing a control system of the power conversion device shown in embodiment 2 of the present invention.

(19) FIG. 19 is a diagram showing the control system of the power conversion device shown in embodiment 2 of the present invention.

(20) FIG. 20 is a diagram showing the operation principle of a power conversion device shown in embodiment 3 of the present invention.

(21) FIG. 21 is a diagram showing a simple equivalent circuit of the power conversion device shown in embodiment 3 of the present invention.

(22) FIG. 22 is a diagram showing the operation principle of the power conversion device shown in embodiment 3 of the present invention.

(23) FIG. 23 is a diagram showing the operation principle of the power conversion device shown in embodiment 3 of the present invention.

(24) FIG. 24 is a diagram showing the operation principle of the power conversion device shown in embodiment 3 of the present invention.

(25) FIG. 25 is a diagram showing the operation principle of the power conversion device shown in embodiment 3 of the present invention.

(26) FIG. 26 is a diagram showing the operation principle of the power conversion device shown in embodiment 3 of the present invention.

(27) FIG. 27 is a diagram showing a control system of the power conversion device shown in embodiment 3 of the present invention.

(28) FIG. 28 is a diagram showing the control system of the power conversion device shown in embodiment 3 of the present invention.

DESCRIPTION OF EMBODIMENTS

Embodiment 1

(29) The configuration of a power conversion device according to embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of the power conversion device according to embodiment 1 of the present invention. The power conversion device shown in FIG. 1 is connected to an AC power supply 1 and a DC load 10, and converts AC power inputted from the AC power supply 1, to DC power, and outputs the DC power to the DC load 10.

(30) The power conversion device is composed of a main circuit for converting AC power inputted from the AC power supply 1 to DC power, and a control circuit for controlling the main circuit. The main circuit includes a transformer 6 having at least two windings. In the following description, of the main circuit, a side connected to the AC power supply 1 with respect to the transformer is assumed as a primary side, and a side connected to the DC load 10 is assumed as a secondary side. On the primary side of the main circuit, provided are: a rectification circuit (first rectification circuit) 200 for rectifying AC power; a reactor 3 operating as a current limiting circuit; and an inverter circuit 400 which converts DC power rectified by the rectification circuit 200 to AC power having desired voltage, and outputs the AC power to the transformer 6. On the secondary side of the main circuit, provided are: a rectification circuit (second rectification circuit) 700 for rectifying AC power outputted from the transformer 6 into DC power; and a smoothing reactor 8 and a smoothing capacitor 9 for smoothing DC power outputted from the rectification circuit 700.

(31) The rectification circuit 200 as the first rectification circuit is connected to the AC power supply 1, and rectifies input from the AC power supply 1 so as to be converted to DC power. The rectification circuit 200 is a full-bridge circuit composed of four diode elements 201 to 204. A DC terminal of the rectification circuit 200 is connected to the inverter circuit 400 via the reactor 3. Here, of the two DC terminals of the rectification circuit 200, the positive-side terminal is referred to as a positive-side DC terminal, and the negative-side terminal is referred to as a negative-side DC terminal. It is noted that the rectification circuit 200 is not limited to the above configuration but may be any circuit that rectifies AC power into DC power. For example, some or all of the diode elements in the rectification circuit 200 may be replaced with active elements such as switching elements.

(32) The reactor 3 is a current limiting reactor having an end connected to the positive-side DC terminal of the rectification circuit 200, and another end connected to the inverter circuit 400. The connection point between the reactor 3 and the inverter circuit 400 is connected to the primary-side terminal of the transformer 6. It is noted that the reactor 3 may be connected to the negative-side DC terminal of the rectification circuit 200, or reactors 3 may be distributed and connected to the two DC terminals of the rectification circuit 200.

(33) The inverter circuit 400 is a full-bridge inverter circuit having four semiconductor switching elements 401a to 404a, and each semiconductor switching element performs switching operation on the basis of a gate signal from the control circuit 11. For the semiconductor switching elements 401a to 404a, diodes 401b to 404b are respectively connected in antiparallel thereto, and capacitors 401c to 404c are connected in parallel thereto. For the semiconductor switching elements 401a to 404a, semiconductor elements such as MOSFETs may be used.

(34) The semiconductor switching element 401a (first switching element) and the semiconductor switching element 402a (second switching element) are connected in series, and the semiconductor switching element 403a (third switching element) and the semiconductor switching element 404a (fourth switching element) are connected in series. Here, the semiconductor switching element 401a and the semiconductor switching element 402a connected in series are referred to as a first leg, and the semiconductor switching element 403a and the semiconductor switching element 404a connected in series are referred to as a second leg. The semiconductor switching element 401a is diagonal to the semiconductor switching element 404a, and the semiconductor switching element 402a is diagonal to the semiconductor switching element 403a.

(35) The connection point (first AC end) between the semiconductor switching element 401a and the semiconductor switching element 402a is connected to the positive-side DC terminal of the rectification circuit 200 via the reactor 3, and is also connected to the primary-side terminal of the transformer 6. The inverter circuit 400 includes a DC capacitor 5, and the DC capacitor 5, the first leg, and the second leg are connected in parallel between DC buses (P and N buses). The negative-side bus of the inverter circuit 400 is connected to the negative-side DC terminal of the rectification circuit 200.

(36) The transformer 6 is an isolation transformer composed of two windings (primary winding and secondary winding). One end of the primary winding is connected to the first AC end of the inverter circuit 400, and the other end is connected to a second AC end which is the connection point between the semiconductor switching element 403a and the semiconductor switching element 404a. Here, a leakage inductance of the transformer 6 is used as a resonance element. However, an external reactor may be used therefor.

(37) The rectification circuit 700 as the second rectification circuit is a full-bridge circuit composed of four diode elements, as in the rectification circuit 200. The AC terminal of the rectification circuit 700 is connected to the secondary-side output terminal of the transformer 6, and rectifies AC power outputted from the transformer 6 and outputs the resultant power from the DC terminal of the rectification circuit 700. It is noted that the rectification circuit 700 is a full-bridge diode rectification type, but may be any circuit that rectifies AC power outputted from the transformer 6. For example, some or all of the diode elements in the rectification circuit 700 may be replaced with active elements such as semiconductor switching elements.

(38) The positive-side DC terminal of the rectification circuit 700 is connected to the smoothing reactor 8, and the smoothing capacitor 9 is connected between the subsequent stage of the smoothing reactor 8 and the negative-side DC terminal of the rectification circuit 700. The DC load 10 is connected to the smoothing capacitor 9, and DC power outputted from the rectification circuit 700 is supplied to the DC load.

(39) The DC load 10 is, for example, a storage battery (battery). Other than this, the DC load 10 may be a DC load needed to be isolated from the AC input, and for example, may be an electric double-layer capacitor.

(40) The power conversion device shown in FIG. 1 is provided with a current detector for detecting current (i.sub.ac) outputted from the rectification circuit 200 and flowing through the reactor 3, a voltage detector (first voltage detector) for detecting DC voltage (V.sub.dc) of the DC capacitor 5, and a voltage detector (second voltage detector) for detecting voltage (V.sub.bat) of the smoothing capacitor 9. In addition, a voltage detector for detecting power supply voltage (V.sub.ac) of the AC power supply 1, and a current detector for detecting current (i.sub.bat) inputted to the DC load 10, are provided. Information about these voltage values and current values is inputted to the control circuit 11.

(41) Next, operation of the power conversion device shown in embodiment 1 of the present invention, i.e., operation of converting AC power inputted from the AC power supply 1 to DC power and outputting the DC power to the DC load 10, will be described with reference to the drawings. FIG. 2 shows gate waveforms illustrating operations of the semiconductor switching elements 401a to 404a, current flowing through the reactor 3, and the charge/discharge condition of the DC capacitor 5. FIG. 3 to FIG. 6 show current routes in the power conversion device, in four operation modes defined in FIG. 2.

(42) Here, T is the drive cycle of the semiconductor switching elements 401a, 402a, 403a, 404a, and t2 is a switching time of the semiconductor switching elements 401a and 402a with which current control is performed. In addition, t1 is an OFF timing of the semiconductor switching element 404a, and t3 is an OFF timing of the semiconductor switching element 403a. In this case, operation modes can be classified into operation modes for four periods of 0 to t1 (first operation mode), t1 to t2 (second operation mode), t2 to t3 (third operation mode), and t3 to T (fourth operation mode). The current routes for the respective four operation modes are shown in FIG. 3 to FIG. 6.

(43) Operation of the power conversion device in the first operation mode, i.e., during the period of 0 to t1 shown in FIG. 2 will be described. In the first operation mode, the semiconductor switching elements 401a, 404a are ON and the semiconductor switching elements 402a, 403a are OFF. In the first operation mode, as shown in FIG. 3, current i.sub.ac inputted from the AC power supply 1 and rectified by the rectification circuit flows through the reactor 3, the transformer 6, and then semiconductor switching element 404a, to return to the input side. At the same time, current flows from the DC capacitor 5 via the semiconductor switching element 401a to the transformer 6, and then the current returns from the transformer 6 via the semiconductor switching element 404a to the DC capacitor 5. In the first operation mode, the potential at the stage subsequent to the reactor 3 is fixed at V.sub.dc by the semiconductor switching element 401a becoming ON. Here, in a state where DC voltage V.sub.dc of the DC capacitor 5 is controlled to be higher than peak voltage Vp of voltage V.sub.ac of the AC power supply 1, current i.sub.ac decreases. The DC capacitor 5 discharges current, and therefore V.sub.dc decreases.

(44) Operation of the power conversion device in the second operation mode, i.e., during the period of t1 to t2 shown in FIG. 2 will be described. In the second operation mode, the semiconductor switching elements 401a, 403a are ON and the semiconductor switching elements 402a, 404a are OFF. In the second operation mode, as shown in FIG. 4, current flows through the reactor 3, the transformer 6, the diode element 403b, and then the DC capacitor 5, to return to the input side. Part of the current having flowed through the diode element 403b flows through the semiconductor switching element 401a to circulate to the transformer 6. In the second operation mode, the potential at the stage subsequent to the reactor 3 is fixed at V.sub.dc by the semiconductor switching element 401a becoming ON, and in a state where voltage V.sub.dc of the DC capacitor 5 is controlled to be higher than peak voltage Vp of voltage V.sub.ac of the AC power supply 1, current i.sub.ac decreases. The DC capacitor 5 is charged with current, and therefore V.sub.dc increases. It is noted that, in the second operation mode, since the potential difference occurring between both ends of the transformer 6 is small, the amount of power outputted to the secondary side is small and therefore is not taken into consideration here.

(45) Operation of the power conversion device in the third operation mode, i.e., during the period of t2 to t3 shown in FIG. 2 will be described. In the third operation mode, the semiconductor switching elements 402a, 403a are ON and the semiconductor switching elements 401a, 404a are OFF. In the third operation mode, as shown in FIG. 5, current i.sub.ac flows back from the reactor 3 via the semiconductor switching element 402a to the input side. In addition, current flows from the DC capacitor 5 via the semiconductor switching element 403a, the transformer 6, and the semiconductor switching element 402a to the DC capacitor 5. In the third operation mode, the potential at the stage subsequent to the reactor 3 is fixed at zero by the semiconductor switching element 402a becoming ON, and current i.sub.ac increases. The DC capacitor 5 discharges current, and therefore V.sub.dc decreases.

(46) Operation of the power conversion device in the fourth operation mode, i.e., during the period of t3 to T shown in FIG. 2 will be described. In the fourth operation mode, the semiconductor switching elements 402a, 404a are ON and the semiconductor switching elements 401a, 403a are OFF. In the fourth operation mode, as shown in FIG. 6, current i.sub.ac flows back from the reactor 3 via the semiconductor switching element 402a to the input side. In addition, current circulates through the semiconductor switching element 402a, the diode 404b, and the transformer 6. In the fourth operation mode, the potential at the stage subsequent to the reactor 3 is fixed at zero by the semiconductor switching element 402a becoming ON, and current i.sub.ac increases. The DC capacitor 5 is not charged with current and does not discharge current, and therefore V.sub.dc is constant. It is noted that, in the fourth operation mode, as in the second operation mode, since the potential difference occurring between both ends of the transformer 6 is small, the amount of power outputted to the secondary side is small and therefore is not taken into consideration here.

(47) As described above, in the first operation mode and the third operation mode, current is inputted to the transformer 6 and power is supplied to the secondary side, while the polarity of the current is inverted between the first operation mode and the third operation mode. By changing these operation modes, AC current is inputted to the transformer 6. The AC power inputted to the primary side of the transformer 6 is subjected to voltage transformation in accordance with the ratio of the numbers of winding turns, and then outputted to the secondary side. At the stage subsequent to the transformer 6, AC power is converted to DC power by the rectification circuit 700, the DC power is smoothed by the smoothing reactor 8 and the smoothing capacitor 9, and the smoothed DC power is supplied to the DC load 10. That is, during the periods of the first operation mode and the third operation mode, DC power can be supplied to the DC load 10.

(48) In the power conversion device shown in embodiment 1 of the present invention, the ON period for the first leg, i.e., the time ratio between the first and second operation modes which correspond to the ON period of the semiconductor switching element 401a, and the third and fourth operation modes which correspond to the ON period of the semiconductor switching element 402a, is controlled. That is, through control of time t2 in FIG. 2, the ratio between the increase amount and the decrease amount of current i.sub.ac flowing through the reactor 3 can be controlled, whereby current i.sub.ac flowing through the reactor 3 can be controlled.

(49) In addition, the ON period of the second leg, i.e., the time ratio between the second and third operation modes which correspond to the ON period of the semiconductor switching element 403a, and the first and fourth operation modes which correspond to the ON period of the semiconductor switching element 404a, is controlled. In addition, a phase shift amount between the ON period for the first leg and the ON period for the second leg, i.e., an amount (phase shift amount) by which the phase of a drive signal for the semiconductor switching element 403a is shifted relative to the semiconductor switching element 401a, and an amount by which the phase of a drive signal for the semiconductor switching element 404a is shifted relative to the semiconductor switching element 402a, are controlled, whereby the charge amount and the discharge amount of the DC capacitor 5 are adjusted and thus voltage V.sub.dc of the DC capacitor 5 can be controlled to be constant. Alternatively, the difference between AC power taken through the current control as described above and power supplied to the DC load 10 is adjusted, whereby voltage V.sub.dc of the DC capacitor 5 is controlled to be constant. This means controlling time t1 and time t3 in FIG. 2. It is noted that, as described later, the period of 0 to t1 and the period of t2 to t3 are set to be equal to each other.

(50) As described above, in the power conversion device shown in embodiment 1, current control using the semiconductor switching element 401a and the semiconductor switching element 402a, and voltage control for V.sub.dc, using the semiconductor switching element 403a and the semiconductor switching element 404a, are performed individually, whereby it is possible to supply DC power to the DC load 10 while achieving current control and voltage control at the same time. Therefore, by performing current control, high-power-factor control for AC power can be performed, i.e., the power factor can be controlled to be approximately 1. In addition, by controlling voltage V.sub.dc of the DC capacitor 5 to be constant, output power to the DC load 10 can be controlled. Therefore, in the case where a battery is connected as the DC load, ripple components of unspecified frequencies in the battery current can be reduced, so that charge power with high quality can be supplied.

(51) Here, the way of determining t1, t2, t3 in FIG. 2 will be described. The time t2 is a timing determined by the current control, and a time ratio (duty cycle) D.sub.401 of the ON period of 0 to t2 of the semiconductor switching element 401a with respect to the switching cycle T is represented by expression (1). On the other hand, a time ratio (duty cycle) D.sub.402 of the ON period t2 to T of the semiconductor switching element 402a with respect to the switching cycle T is represented by expression (2).

(52) $\begin{array}{cc}\left[\mathrm{Mathematical}1\right]& \\ D_{401}=\frac{v_{\mathrm{ac}}}{V_{\mathrm{dc}}}.& \left(1\right)\\ \left[\mathrm{Mathematical}2\right]& \\ D_{402}=\frac{V_{\mathrm{dc}}-v_{\mathrm{ac}}}{V_{\mathrm{dc}}}.& \left(2\right)\end{array}$

(53) Here, v.sub.ac is the voltage of the AC power supply 1, and V.sub.dc is the voltage of the DC capacitor 5. Thus, the semiconductor switching element 401a and the semiconductor switching element 402a are driven with the time ratios based on expression (1) and expression (2), respectively.

(54) First, in the initial state, i.e., a state at the start of battery charge control operation, the phase shift amount for the second leg is set to zero. In the initial state, for making the phase shift amount be zero, rising of the ON state of the semiconductor switching element 403a is synchronized with rising of the ON state of the semiconductor switching element 401a. Similarly, rising of the ON state of the semiconductor switching element 404a is synchronized with rising of the ON state of the semiconductor switching element 402a. That is, the ON period (gate pulse width) and the phase for the third switching element are set to be equal to those for the first switching element, and the ON period (gate pulse width) and the phase for the fourth switching element are set to be equal to those for the second switching element. In this case, only operations in the second and fourth operation modes are performed, while the periods of the first and third operation modes become zero. The control circuit 11 controls the phase shift amount from this initial state. Thus, in the initial state, supply of power can be mildly started.

(55) For making the phase shift amount be zero, rising of the ON state of the semiconductor switching element 404a may be synchronized with rising of the ON state of the semiconductor switching element 401a. At this time, rising of the ON state of the semiconductor switching element 403a may be synchronized with rising of the ON state of the semiconductor switching element 402a. That is, the ON period (gate pulse width) and the phase for the fourth switching element are set to be equal to those for the first switching element, and the ON period (gate pulse width) and the phase for the third switching element are set to be equal to those for the second switching element. In this case, only operations in the first and third operation modes are performed, while the periods of the second and fourth operation modes become zero. The control circuit 11 controls the phase shift amount from this initial state. Thus, supply of power can be started sharply from the initial state. It is noted that it is not always necessary to make the phase shift amount be zero, but a phase shift amount defined in advance in accordance with requirements in the initial state may be set for the initial state.

(56) As described above, currents with opposite polarities flow through the transformer 6 in the period of the first operation mode and the period of the third operation mode, respectively. Therefore, in order to suppress magnetic bias of the isolation transformer, the overlap period (period of first operation mode) between the semiconductor switching elements 401a and 404a, and the overlap period (period of third operation mode) between the semiconductor switching elements 402a and 403a, are controlled to be equal to each other. That is, the period of 0 to t1 and the period of t2 to t3 in FIG. 2 are equal to each other. It is noted that it is not always necessary to make the period of the first operation mode and the period of the third operation mode equal to each other.

(57) Next, the phase shift amount for the second leg will be described. The phase shift amount for the second leg corresponds to the length of the period of the first operation mode (t0 to t1) in FIG. 2, and here, is represented as a time ratio in conformity with D.sub.401, D.sub.402. A phase shift amount D.sub.403 for the second leg is represented as shown by expression (3). Here, the number of turns on the primary side, i.e., the AC power supply side, of the transformer 6 is defined as N1, and the number of turns on the secondary side, i.e., the DC load side, is defined as N2. In addition, V.sub.bat is the voltage of the smoothing capacitor 9. In accordance with the phase shift amount shown by expression (3), the semiconductor switching element 403a and the semiconductor switching element 404a are operated with the same phase shift amount.

(58) $\begin{array}{cc}\left[\mathrm{Mathematical}3\right]& \\ D_{403}=\frac{V_{\mathrm{bat}}}{V_{\mathrm{dc}}}.Math.\frac{N_2}{N_1}.Math.\frac{1}{2}& \left(3\right)\end{array}$

(59) In the power conversion device shown in the present embodiment, D.sub.403 needs to be always smaller than D.sub.401 and D.sub.402. That is, t1 needs to satisfy a relationship of 0t1t2, and t3 needs to satisfy a relationship of t2t3T.

(60) FIG. 7 shows a schematic duty trajectory diagram of D.sub.401 and D.sub.402 satisfying the above relationships. In FIG. 7, the horizontal axis indicates the phase of voltage V.sub.ac of the AC power supply 1, and the vertical axis indicates the time ratio of the ON period of each semiconductor switching element with respect to the drive cycle. At phases zero and n of AC voltage, the voltage becomes zero, and in the vicinity thereof, D.sub.401 infinitely approaches zero, and therefore D.sub.401 becomes restriction on D.sub.403. On the other hand, in the vicinity of /2, D.sub.402<D.sub.401 is satisfied, and therefore D.sub.402 becomes restriction. As a result, the trajectory indicated by a thick line in FIG. 7 becomes a restriction duty D.sub.limit which is the upper limit value of D.sub.403. D.sub.limit can be represented by expression (4).

(61) $\begin{array}{cc}\left[\mathrm{Mathematical}4\right]& \\ D_{\mathrm{limit}}=\min \left\{\frac{\sqrt{2}{V}_{\mathrm{ac}}}{V_{\mathrm{dc}}},\frac{V_{\mathrm{dc}}-\sqrt{2}{V}_{\mathrm{ac}}}{V_{\mathrm{dc}}}\right\}& \left(4\right)\end{array}$

(62) If D.sub.403 is smaller than D.sub.limit, the current conduction periods of 0 to t1 and t2 to t3 for the transformer 6 can be optionally adjusted and the V.sub.dc control can be achieved. In the present embodiment, the control-allowed condition for controlling voltage V.sub.dc of the DC capacitor to be constant is that D.sub.403 is smaller than D.sub.limit at the peak phase, i.e., D.sub.limit_p. This means that expression (5) is the control-allowed condition.

(63) $\begin{array}{cc}\left[\mathrm{Mathematical}5\right]& \\ \frac{V_{\mathrm{bat}}}{V_{\mathrm{dc}}}.Math.\frac{N_2}{N_1}.Math.\frac{1}{2}<\min \left\{\frac{\sqrt{2}{V}_{\mathrm{ac}}}{V_{\mathrm{dc}}},\frac{V_{\mathrm{dc}}-\sqrt{2}{V}_{\mathrm{ac}}}{V_{\mathrm{dc}}}\right\}& \left(5\right)\end{array}$

(64) At a phase near zero, since D.sub.limit is in principle infinitely close to zero, the relationship of expression (5) cannot be satisfied. In this case, the command value D.sub.403 is controlled so as to be equal to or smaller than D.sub.limit. In this case, the trajectory of D.sub.403 is as shown in FIG. 8, wherein, when D.sub.403 is greater than D.sub.limit, D.sub.403 is set to D.sub.limit, and when D.sub.403 is smaller than D.sub.limit, D.sub.403 is set to the value calculated by expression (3). In this case, irrespective of the phase, D.sub.403 can always be smaller than D.sub.limit and thus satisfies the control-allowed condition.

(65) As described above, the phase shift amount D.sub.403 for the semiconductor switching element 403a and the semiconductor switching element 404a is set to be equal to or smaller than the limit D.sub.limit based on D.sub.401 and D.sub.402 defined by the current control using the semiconductor switching element .sub.401a and the semiconductor switching element 402a, whereby the control for making V.sub.dc constant is enabled, and thus the high-power-factor control and the output power control can be achieved with a single full-bridge inverter circuit.

(66) It is noted that, even if only the ON periods are controlled for the semiconductor switching elements 403a, 404a, the high-power-factor control and the output power control can be achieved, but a through current occurs in the semiconductor switches and the loss increases. However, by controlling also the phase shift amount for the second leg, the through current can be suppressed and high-efficiency operation by soft-switching operation is enabled.

(67) Since charging and discharging of the DC capacitor 5 are performed in the drive cycle T of the inverter circuit 400, voltage ripple based on the drive cycle occurs. In particular, the voltage ripple is prescribed by the voltage ripple during the charge period in the second operation mode. In general, in a single-phase inverter connected to a single-phase system, voltage ripple having a frequency twice as high as the AC frequency occurs at the DC part. However, in the power conversion device shown in the present embodiment, such voltage ripple having the two-fold frequency does not occur. Therefore, the capacitance of the DC capacitor 5 can be greatly reduced and the DC capacitor 5 can be downsized.

(68) In the power conversion device of the present embodiment, voltage and current of the AC power supply where the power factor becomes 1 are represented as shown by expressions (6), (7). In addition, power P.sub.ac of the AC power supply 1 is represented as shown by expression (8). In the power conversion device shown in the present embodiment, P.sub.ac represented by expression (8) is entirely transferred to the DC load 10. If the voltage of the DC load 10 is controlled to be constant voltage V.sub.bat, current I.sub.bat supplied to the DC load is defined by expression (9). Therefore, the current flowing into the DC load 10 has a pulsating component having a two-fold AC frequency.

(69) $\begin{array}{cc}\left[\mathrm{Mathematical}6\right]& \\ v_{\mathrm{ac}}=\sqrt{2}{V}_{\mathrm{ac}}\sin t& \left(6\right)\\ \left[\mathrm{Mathematical}7\right]& \\ i_{\mathrm{ac}}=\sqrt{2}{I}_{\mathrm{ac}}\sin t& \left(7\right)\\ \left[\mathrm{Mathematical}8\right]& \\ P_{\mathrm{ac}}=V_{\mathrm{ac}}{I}_{\mathrm{ac}}\left(1-\cos 2t\right)& \left(8\right)\\ \left[\mathrm{Mathematical}9\right]& \\ I_{\mathrm{bat}}=\frac{V_{\mathrm{ac}}{I}_{\mathrm{ac}}}{V_{\mathrm{bat}}}\left(1-\cos 2t\right)& \left(9\right)\end{array}$

(70) Next, the details of a method for the current control using the semiconductor switching element 401a and the semiconductor switching element 402a, i.e., controlling current i.sub.ac so as to be a predetermined target sinewave current so that the power factor becomes approximately 1, will be described. FIG. 9 is a control block diagram showing generation of duty command values used for output control for the semiconductor switching element 401a and the semiconductor switching element 402a in the control circuit 11. The control circuit 11 calculates duty command values for controlling the amount of current from the AC power supply 1 and current i.sub.ac so that the power factor from the AC power supply 1 becomes approximately 1. First, a current difference 20 between a predetermined current command (target sinewave current) i.sub.ac* having a sinusoidal waveform synchronized with power supply voltage V.sub.ac, and current i.sub.ac detected by the current detector, is calculated. Using the calculated current difference 20 as a feedback amount, PI control is performed to obtain output 21. Next, the output 21 is divided by voltage V.sub.dc of the DC capacitor 5 detected by the voltage detector, whereby a duty command value 22 for the semiconductor switching element 402a is calculated.

(71) A feedforward term 23 is added to the duty command value 22. Here, the feedforward term 23 is a value represented by expression (2) and is determined per drive cycle in accordance with the phase of the AC power supply 1. A duty command value 24 obtained by adding the feedforward term 23 is used as a duty command value for the semiconductor switching element 402a. In addition, a duty command value 25 obtained by subtracting the duty command value 24 for the semiconductor switching element 402a from 1 is used as a duty command value for the semiconductor switching element 401a.

(72) FIG. 10 is a calculation block diagram for D.sub.limit calculated on the basis of the duty command value 24 for the semiconductor switching element 402a and the duty command value 25 for the semiconductor switching element 401a. A duty selector (MUX) 26 selects the duty command value 24 or the duty command value 25 as D.sub.limit in accordance with the magnitude relationship between the duty command value 24 for D.sub.402 and the duty command value 25 for D.sub.401. That is, if the duty command value 25 is greater than the duty command value 24, a comparison signal 27 is outputted at L level, so that the duty selector 26 selects the duty command value 24 as D.sub.limit 28. On the other hand, if the duty command value 24 is greater than the duty command value 25, the comparison signal 27 is outputted at H level, so that the duty selector 26 selects the duty command value 25 as D.sub.limit 28.

(73) FIG. 11 is a control block diagram showing generation of a D.sub.403 command value in the control for making voltage V.sub.dc of the DC capacitor 5 constant by the semiconductor switching element 403a and the semiconductor switching element 404a. The D.sub.403 command value for adjusting the output power of the semiconductor switching element 403a and the semiconductor switching element 404a to control the voltage V.sub.dc of the DC capacitor 5 so as to be constant, is calculated.

(74) First, a difference 29 between a predetermined DC voltage command value V.sub.dc* for the DC capacitor 5 and voltage V.sub.dc detected by the voltage detector is calculated. Here, the DC voltage command value V.sub.dc* is set to a voltage value higher than the peak voltage of AC voltage inputted from the AC power supply. Using this difference 29 as a feedback amount, PI control is performed to obtain an output current command value 30 for the DC load 10. Using a difference value 31 between the output current command value 30 and a detection value I.sub.bat of DC current as a feedback amount, PI control is performed and a calculation result 32 thereof is inputted to a gain adjuster 33, to generate the D.sub.403 command value 34.

(75) FIG. 12 is a calculation block diagram in which a phase shift amount command value for the semiconductor switching element 403a and the semiconductor switching element 404a is generated from the D.sub.403 command value 34 calculated in the calculation block diagram shown in FIG. 11 and D.sub.limit 28 calculated in the calculation block shown in FIG. 10. First, the D.sub.403 command value 34 and the D.sub.limit 28 are inputted to a selector (MUX) 35. The selector 35 selects the D.sub.403 command value 34 or the D.sub.limit 28 in accordance with a calculation result 36 of magnitude comparison between the D.sub.403 command value 34 and the D.sub.limit 28. If the D.sub.403 command value 34 is smaller than D.sub.limit 28, the D.sub.403 command value 34 is used as a phase shift amount command value 37 for D.sub.403. On the other hand, if the D.sub.403 command value 34 is greater than D.sub.limit 28, D.sub.limit 28 is used as the phase shift amount command value 37 for D.sub.403. In this way, the phase shift amount command value 37 for D.sub.403 for the semiconductor switching element 403a and the semiconductor switching element 404a can be always made equal to or smaller than D.sub.limit 28, and thus the control-allowed condition for V.sub.dc control can be satisfied.

(76) Next, processes for generating a gate signal for the semiconductor switching element .sub.401a generated from the duty command value 25 for D.sub.401, a gate signal for the semiconductor switching element 402a generated from the duty command value 24 for D.sub.402, and gate signals for the semiconductor switching element 403a and the semiconductor switching element 404a generated from the phase shift amount command value 37 for D.sub.403, will be described. In the present embodiment, the case of generating these gate signals using a saw-tooth wave as a carrier wave will be described.

(77) FIG. 13 shows the relationship among a saw-tooth wave 38 as a carrier wave, the duty command value 25 for D.sub.401, the duty command value 24 for D.sub.402, the phase shift amount command value 37 for D.sub.403, and gate signals for the semiconductor switching elements 401a to 404a. FIG. 14 shows a calculation block diagram for generating the gate signals for the semiconductor switching element 401a and the semiconductor switching element 402a. FIG. 15 shows a calculation block diagram for generating the gate signals for the semiconductor switching element 403a and the semiconductor switching element 404a. The used saw-tooth waves have the same value and the same phase for the four elements of semiconductor switching elements 401a to 404a.

(78) As shown in FIG. 14, the duty command value 24 for D.sub.402 and the saw-tooth wave 38 are inputted to a gate signal generator 39. As shown in FIG. 13, as a result of comparison between the duty command value 24 for D.sub.402 and the saw-tooth wave 38, if the duty command value 24 for D.sub.402 is greater than the saw-tooth wave 38, a gate signal 40 for the semiconductor switching element 402a that turns on the semiconductor switching element 402a is generated. As a result of comparison between the duty command value 24 for D.sub.402 and the saw-tooth wave 38, if the duty command value 24 for D.sub.402 is smaller than the saw-tooth wave 38, a gate signal 41 for the semiconductor switching element 401a that turns on the semiconductor switching element 401a is generated. In this way, for the semiconductor switching element 401a and the semiconductor switching element 402a, the gate signals for the semiconductor switching element 401a and the semiconductor switching element 402a are generated on the basis of the duty command value 24 for D.sub.401 and the duty command value 25 for D.sub.402 calculated by the high-power-factor control.

(79) As shown in FIG. 15, the phase shift amount command value 37 for D.sub.403 and the saw-tooth wave 38 are inputted to a gate signal generator 42. In addition, a phase shift amount signal 43 obtained by summing the phase shift amount command value 37 for D.sub.403 and the duty command value 24 for D.sub.402, and the saw-tooth wave 38 are inputted to a gate signal generator 44. A signal representing a logical conjunction of a comparison signal between the phase shift amount signal 43 and the saw-tooth wave 38 and a comparison signal between the saw-tooth wave 38 and the phase shift amount command value 37 for D.sub.403, is used as a gate signal 45 for the semiconductor switching element 404a. A signal representing a negation of the gate signal 45 is used as a gate signal 46 for the semiconductor switching element 403a. As described above, the gate signals for the semiconductor switching elements 401a to 404a can be generated.

(80) The calculation block diagrams shown in FIGS. 9 to 12 and 14 may be implemented by hardware using a calculation circuit, or as shown in FIG. 16, may be implemented by software, using a memory storing a program, and a processor for processing the program.

(81) In the present embodiment, the case of not providing a dead time between the ON period of the semiconductor switching element 401a and the ON period of the semiconductor switching element 402a has been shown. However, the dead time may be provided. Similarly, a dead time may be provided between the semiconductor switching element 403a and the semiconductor switching element 404a.

(82) In the present embodiment, one terminal of the reactor 3 is connected to the positive-side DC output terminal of the rectification circuit 200, and the other terminal of the reactor 3 is connected to the first AC end which is the connection point between the semiconductor switching element 401a and the semiconductor switching element 402a, whereby high-power-factor control is performed using the semiconductor switching elements 401a, 402a. However, the other terminal of the reactor 3 may be connected to the connection point between the semiconductor switching elements 403a and 404a, to perform high-power-factor control using the semiconductor switching elements 403a, 404a. In this case, it suffices that the gate signal to be inputted to the semiconductor switching element 401a is inputted to the semiconductor switching element 403a, and the gate signal to be inputted to the semiconductor switching element 402a is inputted to the semiconductor switching element 404a.

(83) In the case where the reactor 3 is connected to the negative side output DC terminal of the diode rectification circuit or the reactors 3 are distributed and connected to the positive-side and negative-side output DC terminals of the diode rectification circuit, high-power-factor control is performed using the semiconductor switching elements 401a, 402a, and output power control is performed using the semiconductor switching element 403a and the semiconductor switching element 404a.

(84) In the present embodiment, as described above, the ON duties for the semiconductor switching element 401a and the semiconductor switching element 402a are controlled in accordance with the current command value, whereby input current from the AC power supply 1 is adjusted to a predetermined current value and thus the power factor can be controlled to be approximately 1. At the same time, the phase shift amount for the semiconductor switching element 403a and the semiconductor switching element 404a is changed so that DC voltage V.sub.dc of the DC capacitor 5 follows target voltage, whereby DC voltage of the DC capacitor 5 is controlled to be constant, and thus the output power to the DC load can be controlled.

(85) In the configuration of a single full-bridge inverter, the functions of high-power-factor control and output power control are separated for the respective legs, whereby it becomes possible to achieve both high-power-factor control and output power control by a single full-bridge inverter, and thus the entire circuit can be downsized as compared to a conventional method in which two general power converters are provided to achieve high-power-factor control and output power control individually.

(86) The power pulsation pulsating at a frequency twice as high as the AC power supply frequency occurring at the AC power supply 1 is entirely transferred to the DC load 10, and at the DC capacitor 5, voltage ripple occurs only by charging and discharging due to the switching cycle T. In this case, the DC capacitor 5 does not need to bear the power pulsation having a frequency twice as high as the AC power supply frequency, and as compared to the method in which two general power converters are provided and a capacitor is provided at a link portion between the two power converters, the DC capacitor 5 only has to bear charging and discharging due to the switching cycle T. Therefore, the capacitance needed for the DC capacitor 5 can be greatly reduced and the DC capacitor 5 can be downsized.

(87) In addition, the period during which the ON states of the semiconductor switching element 401a and the semiconductor switching element 404a overlap each other, and the period during which the ON states of the semiconductor switching element 402a and the semiconductor switching element 404a overlap each other, are set to be equal to each other, so as to suppress magnetic bias of the transformer 6, whereby more reliable control can be achieved.

Embodiment 2

(88) In embodiment 1, a saw-tooth wave is used as the carrier signal for ON period control in generation of the gate signals for the semiconductor switching elements 401a to 404a. In embodiment 2, the case of using a triangular wave as the carrier signal for ON period control will be described.

(89) The circuit configuration of the power conversion device and the control method in the present embodiment are the same as those shown in embodiment 1, and the description thereof is omitted. In addition, the duty command value 25 for D.sub.401, the duty command value 24 for D.sub.402, and the phase shift amount command value 37 for D.sub.403 are calculated by the same method as in embodiment 1. That is, the present embodiment is the same as embodiment 1 except for the operation for generating gate signals for the semiconductor switching elements shown in FIGS. 13 to 15.

(90) Processes for generating a gate signal for the semiconductor switching element 401a generated from the duty command value 25 for D.sub.401, a gate signal for the semiconductor switching element 402a generated from the duty command value 24 for D.sub.402, and gate signals for the semiconductor switching element 403a and the semiconductor switching element 404a generated from the phase shift amount command value 37 in the present embodiment, will be described.

(91) FIG. 17 shows the relationship among a carrier wave 47, the duty command value 25 for D.sub.401, the duty command value 24 for D.sub.402, the phase shift amount command value 37 for D.sub.403, and gate signals for the semiconductor switching elements 401a to 404a. The carrier wave 47 is a triangular wave, and the same triangular wave is used for generating the gate signals for the semiconductor switching elements 401a to 404a.

(92) On the basis of the magnitude relationship between the triangular wave 47, and a rectangular wave 48 of which the amplitude from the duty command value 24 for D.sub.402 as a reference is equal to the phase shift amount command value for D.sub.403, the phase for the semiconductor switching element 403a is shifted relative to the semiconductor switching element 401a, and the phase for the semiconductor switching element 404a is shifted relative to the semiconductor switching element 402a. The value of the rectangular wave is switched between the mountain and valley of the triangular wave. In this case, the first to fourth operation modes defined in FIG. 2 are newly defined as shown in FIG. 17, but the newly defined operation modes are configured in the same manner as the four operation modes defined in embodiment 1, whereby high-power-factor control is performed using the semiconductor switching element 401a and the semiconductor switching element 402a, and output power control is performed using the semiconductor switching element 403a and the semiconductor switching element 404a.

(93) Instead of the rectangular wave 48, two DC signals having the same values as the rectangular wave amplitudes may be used, and the signal to be used for magnitude comparison is switched at the mountain/valley timing of the triangular wave 47, so as to realize a pseudo rectangular wave.

(94) FIG. 18 shows a block diagram for generating the gate signal for the semiconductor switching element 401a and the gate signal for the semiconductor switching element 402a, from the duty command value 25 for D.sub.401 and the duty command value 24 for D.sub.402. The duty command value 24 for D.sub.402 and the triangular wave 47 are inputted to a gate signal generator 49. A gate signal 50 for the semiconductor switching element 402a is generated so as to turn on the semiconductor switching element 402a during a period in which the duty command value 24 for D.sub.402 is greater than the triangular wave 47. On the other hand, a gate signal 51 for the semiconductor switching element 401a is generated so as to turn on the semiconductor switching element 401a during a period in which the duty command value 24 for D.sub.402 is smaller than the triangular wave 47.

(95) FIG. 19 is a calculation block diagram showing a method for generating the gate signals for the semiconductor switching elements 403a, 404a. As shown in FIG. 19, first, the duty command value 24 for D.sub.402 is added to the rectangular wave 48 having one-side amplitude equal to the phase shift amount command value 37 for D.sub.403, thereby generating the rectangular wave 48. Next, the generated rectangular wave 48 and the triangular wave 47 are inputted to a comparator 52. A calculation result 53 of comparison between the rectangular wave 48 and the triangular wave 47 is used as the gate signal for the semiconductor switching element 404a. In addition, a signal 54 representing a negation of the calculation result 53 is used as the gate signal for the semiconductor switching element 403a. As described above, the gate signals for the semiconductor switching elements 401a to 404a can be generated.

(96) In the present embodiment, since the configuration and the control as described above are used, it is possible to achieve high-power-factor control and output power control at the same time by a single stage of full-bridge inverter circuit, as in the power conversion device shown in embodiment 1.

Embodiment 3

(97) In the power conversion devices shown in embodiments 1 and 2, during the flow-back period (second operation mode or fourth operation mode) in which the semiconductor switching elements 401a and 403a or the semiconductor switching elements 402a and 404a become ON, since a potential difference occurring between both ends of the transformer 6 is small, the amount of output to the secondary side is small and therefore is not taken into consideration. In the present embodiment, a power conversion device that enables more stable operation while considering a potential difference occurring between both ends of the transformer 6 will be described. It is noted that the configuration of the power conversion device shown in the present embodiment is the same as that shown in FIG. 1 and the description thereof is omitted.

(98) FIG. 20 shows the relationship among the saw-tooth wave 38 as a carrier wave, the duty command value 25 for D.sub.401, the duty command value 24 for D.sub.402, the phase shift amount command value 37 for D.sub.403, the gate signals for the semiconductor switching elements 401a to 404a, voltage of the transformer 6, and current of the smoothing reactor 8, in the case of considering minute voltage between both ends of the transformer 6 occurring in the second operation mode and the fourth operation mode. As shown in FIG. 20, even during the flow-back periods, minute voltage occurs between both ends of the transformer 6.

(99) FIG. 21 shows a simple equivalent circuit during the flow-back period in which the semiconductor switching elements 401a and 403a or the semiconductor switching elements 402a and 404a become ON. At this time, voltage V.sub.tr_p between both ends of the transformer 6 is represented as shown by the following expression (10). It is noted that the forward-direction voltage of the diodes 701 to 704 is defined as V.sub.f, the leakage inductance of the transformer 6 is defined as L.sub.k, and the inductance value of the smoothing reactor 8 is defined as Lf. It is noted that a leakage inductance 55 and an excitation inductance 56 of the transformer 6 may be replaced with an external reactor.

(100) $\begin{array}{cc}\left[\mathrm{Mathematical}10\right]& \\ V_{\mathrm{tr\_p}}=\frac{N_1}{N_2}\frac{V_{\mathrm{bat}}+2V_f}{1+\frac{L_f}{L_k}{\left(\frac{N_1}{N_2}\right)}^2}& \left(10\right)\end{array}$

(101) As shown in FIG. 20 and expression (10), in the case of considering minute voltage between both ends of the transformer 6, a product of voltage of the transformer 6 and time, and the time integral value of current of the smoothing reactor 8, are deviated. Therefore, in usage for large power capacity, a magnetic bias phenomenon can occur. In order to suppress the magnetic bias phenomenon without changing the specifications of passive elements such as the transformer and the reactor, it is necessary to eliminate deviation of a product of voltage of the transformer 6 and time and deviation of the time integral value of current of the smoothing reactor 8. Accordingly, in the power conversion device shown in the present embodiment, the power transmission period (first operation mode and third operation mode) and the flow-back period (second operation mode and fourth operation mode) are corrected to reduce deviation of a product of voltage of the transformer 6 and time and deviation of the time integral value of current of the smoothing reactor 8. Hereinafter, the details thereof will be described.

(102) The control circuit 11 calculates the time ratio (duty cycle) D.sub.401 for the semiconductor switching element 401a, the time ratio (duty cycle) D.sub.402 for the semiconductor switching element 402a, and the phase shift amount D.sub.403 for the second leg, by the same method as in embodiment 1 and embodiment 2. In the power conversion device shown in the present embodiment, these calculated values are corrected.

(103) FIG. 22 shows a schematic duty trajectory diagram in the case where the phase shift amount D.sub.403 for the second leg composed of the semiconductor switching element 403a and the semiconductor switching element 404a is corrected. In FIG. 22, the phase shift amount for the second leg is corrected as shown by a trajectory indicated by D.sub.4032. As shown in FIG. 22, the phase shift amount for the second leg is corrected, whereby the ON period and the phase shift amount for each of the semiconductor switching element 403a and the semiconductor switching element 404a are changed. Thus, it becomes possible to suppress deviation of a product of voltage of the transformer 6 and time and deviation of the time integral value of current of the smoothing reactor 8. The correction period in the power transmission period at this time is defined as T. In addition, for T, a polarity of increasing the power transmission period of the semiconductor switching element 402a and the semiconductor switching element 403a is defined as positive. As the correction method, using the center of the gate signal phase of each of the semiconductor switching element 403a and the semiconductor switching element 404a as a reference, both ends thereof are each increased or decreased by T/2. Instead of decreasing both ends by T/2, one of the pulse ends may be increased or decreased by T. It is noted that, as shown in FIG. 23, the duty cycle (ON period) for the first leg composed of the semiconductor switching element 401a and the semiconductor switching element 402a may be corrected.

(104) By suppressing deviation of the time integral value of current of the smoothing reactor 8, deviation of a product of voltage of the transformer 6 and time is also suppressed. Therefore, the control method using the time integral value of current of the smoothing reactor 8 will be described.

(105) As shown in FIG. 24, a period during which the phase shift amount D.sub.403 is smaller than D.sub.limit is defined as a first operation sub mode, and a period during which D.sub.403 is equal to or greater than D.sub.limit is defined as a second operation sub mode. First, the case of considering a correction period T1 for the power transmission period in the first operation sub mode will be described. As shown in FIG. 25, in the case of considering the correction period T1, the ON timing of the semiconductor switching element 402a is denoted by t02, and the OFF timing of the semiconductor switching element 403a is denoted by t12. In addition, the ON timing of the semiconductor switching element 401a is denoted by t22, and the OFF timing of the semiconductor switching element 404a is denoted by t32. In this case, operation modes can be classified into four operation modes of t02 to t12, t12 to t22, t22 to t32, and t32 to T.

(106) A time integral value of current of the smoothing reactor 8 over the period during which the semiconductor switching elements 401a and 404a are ON is defined as T.sub.int1, and a time integral value of current of the smoothing reactor 8 over the period during which the semiconductor switching elements 402a and 403a are ON is defined as T.sub.int2.

(107) The above four operation mode periods can be represented as shown by the following expressions (11) to (14). It is noted that the initial time t02 is set at 0.

(108) $\begin{array}{cc}\left[\mathrm{Mathematical}11\right]& \\ t_{12}=D_{403}T+\frac{T_1}{2}.& \left(11\right)\\ \left[\mathrm{Mathematical}12\right]& \\ t_{22}-t_{12}=\left(D_{402}-D_{403}\right)T-\frac{T_1}{2}.& \left(12\right)\\ \left[\mathrm{Mathematical}13\right]& \\ t_{32}-t_{22}=D_{403}T-\frac{T_1}{2}.& \left(13\right)\\ \left[\mathrm{Mathematical}14\right]& \\ T-t_{32}=\left(1-D_{402}-D_{403}\right)T+\frac{T_1}{2}.& \left(14\right)\end{array}$

(109) In this case, initial current i.sub.Lf of the smoothing reactor 8 in each operation mode can be represented as follows.

(110) $\begin{array}{cc}\left[\mathrm{Mathematical}15\right]& \\ i_{\mathrm{Lf}}\left(t_{12}\right)=\frac{\frac{N_2}{N_1}{V}_{\mathrm{dc}}-V_{\mathrm{bat}}}{L_f}\left(D_{403}T+\frac{T_1}{2}\right)+i_{\mathrm{Lf}}\left(0\right)& \left(15\right)\\ \left[\mathrm{Mathematical}16\right]& \\ i_{\mathrm{Lf}}\left(t_{22}\right)=\frac{-V_{\mathrm{bat}}}{L_f}\left\{\left(D_{402}-D_{403}\right)T-\frac{T_1}{2}\right\}+i_{\mathrm{Lf}}\left(t_{12}\right)& \left(16\right)\\ \left[\mathrm{Mathematical}17\right]& \\ i_{\mathrm{Lf}}\left(t_{32}\right)=\frac{\frac{N_2}{N_1}{V}_{\mathrm{dc}}-V_{\mathrm{bat}}}{L_{\mathrm{bat}}}\left(D_{403}T-\frac{T_1}{2}\right)+i_{\mathrm{Lf}}\left(t_{22}\right)& \left(17\right)\\ \left[\mathrm{Mathematical}18\right]& \\ i_{\mathrm{Lf}}\left(T\right)=\frac{-V_{\mathrm{bat}}}{L_f}\left\{\left(1-D_{402}-D_{403}\right)T+\frac{T_1}{2}\right\}+i_{\mathrm{Lf}}\left(t_{32}\right)& \left(18\right)\end{array}$

(111) From the above, each time integral value of current of the smoothing reactor 8 can be represented by expression (19) and expression (20).

(112) $\begin{array}{cc}\left[\mathrm{Mathematical}19\right]& \\ \begin{array}{c}{I}_{\mathrm{int}1}=\frac{1}{2}\left\{i_{\mathrm{Lf}}\left(t_{32}\right)+i_{\mathrm{Lf}}\left(t_{22}\right)\right\}\left(D_{403}T-\frac{T_1}{2}\right)\\ =\frac{1}{2L_f}[\left(\frac{N_2}{N_1}{V}_{\mathrm{dc}}-V_{\mathrm{bat}}\right){\left(D_{403}T-\frac{T_1}{2}\right)}^2-2V_{\mathrm{bat}}{D}_{402}T+\\ 2\frac{N_2}{N_1}{V}_{\mathrm{dc}}\left\{{\left(D_{403}T\right)}^2-\left(\frac{T_1^2}{2}\right)\right\}+2L_f{i}_{\mathrm{Lf}}\left(0\right)\left(D_{403}T-\frac{T_1}{2}\right)]\end{array}& \left(19\right)\\ \left[\mathrm{Mathematical}20\right]& \\ \begin{array}{c}{I}_{\mathrm{int}2}=\frac{1}{2}\left\{i_{\mathrm{Lf}}\left(t_{12}\right)+i_{\mathrm{Lf}}\left(0\right)\right\}\left(D_{403}T+\frac{T_1}{2}\right)\\ =\frac{1}{2L_f}[\left(\frac{N_2}{N_1}{V}_{\mathrm{dc}}-V_{\mathrm{bat}}\right){\left(D_{403}T+\frac{T_1}{2}\right)}^2+\\ 2L_f{i}_{\mathrm{Lf}}\left(0\right)\left(D_{403}T+\frac{T_1}{2}\right)]\end{array}& \left(20\right)\end{array}$

(113) From expression (19) and expression (20), deviation I.sub.int of the time integral value of current of the smoothing reactor 8 is represented as follows.

(114) 0$\begin{array}{cc}\left[\mathrm{Mathematical}21\right]& \\ \begin{array}{c}{I}_{\mathrm{int}}=I_{\mathrm{int}2}-I_{\mathrm{int}1}\\ =\frac{1}{2L_f}[\frac{N_2}{N_1}{V}_{\mathrm{dc}}{T}_1^2-4\left\{\left(V_{\mathrm{bat}}{D}_{402}T-\frac{N_2}{N_1}{V}_{\mathrm{dc}}\right)D_{403}T-L_f{i}_{\mathrm{Lf}}\left(0\right)\right\}\\ T_1-4\left(\frac{N_2}{N_1}{V_{\mathrm{dc}}\left(D_{403}T\right)}^2-V_{\mathrm{bat}}{D}_{402}T\right)]\end{array}& \left(21\right)\end{array}$

(115) In order to suppress magnetic bias of the transformer 6, I.sub.int needs to be zero. Therefore, from expression (21), the correction period T1 can be represented as follows.

(116) $\begin{array}{cc}\left[\mathrm{Mathematical}22\right]& \\ T_1=2\frac{{}_1-\sqrt{{}_1^2+\frac{N_2}{N_1}{V}_{\mathrm{dc}}\left\{\frac{N_2}{N_1}{V_{\mathrm{dc}}\left(D_{403}T\right)}^2-V_{\mathrm{bat}}{D}_{402}T\right\}}}{\frac{N_2}{N_1}{V}_{\mathrm{dc}}}& \left(22\right)\end{array}$

(117) It is noted that 1 in expression (22) is defined as follows.

(118) $\begin{array}{cc}\left[\mathrm{Mathematical}23\right]& \\ {}_1=\left(V_{\mathrm{bat}}{D}_{402}T-\frac{N_2}{N_1}{V}_{\mathrm{dc}}\right)D_{403}T-L_f{i}_{\mathrm{Lf}}\left(0\right)& \left(23\right)\end{array}$

(119) Next, the case of considering a correction period T2 for the power transmission period in the second operation sub mode in FIG. 24 will be described. As shown in FIG. 26, in the case of considering the correction period T2, the ON timing of the semiconductor switching element 402a is denoted by t03, and the OFF timing of the semiconductor switching element 403a is denoted by t13. In addition, the ON timing of the semiconductor switching element 401a is denoted by t23, and the OFF timing of the semiconductor switching element 404a is denoted by t33. In this case, operation modes can be classified into four operation modes of t03 to t13, t13 to t23, t23 to t33, and t33 to T.

(120) The above four operation mode periods can be represented as shown by expressions (24) to (27). It is noted that the initial time t03 is set at 0.

(121) $\begin{array}{cc}\left[\mathrm{Mathematical}24\right]& \\ t_{13}=\frac{T_2}{2}.& \left(24\right)\\ \left[\mathrm{Mathematical}25\right]& \\ t_{23}-t_{13}=D_{403}T-T_2.& \left(25\right)\\ \left[\mathrm{Mathematical}26\right]& \\ t_{33}-t_{23}=\left(D_{402}-D_{403}\right)T+\frac{T_2}{2}.& \left(26\right)\\ \left[\mathrm{Mathematical}27\right]& \\ T-t_{33}=\left(1-D_{402}\right)T.& \left(27\right)\end{array}$

(122) As in the above first operation sub mode, deviation I.sub.int of the time integral value of current of the smoothing reactor 8 in the second operation sub mode is represented by expression (28).

(123) $\begin{array}{cc}\left[\mathrm{Mathematical}28\right]& \\ \begin{array}{c}{I}_{\mathrm{int}}=I_{\mathrm{int}2}-I_{\mathrm{int}1}\\ =\frac{1}{2L_f}[\frac{N_2}{N_1}{V}_{\mathrm{dc}}{T}_2^2-\{\left(2\frac{N_2}{N_1}{V}_{\mathrm{dc}}-V_{\mathrm{bat}}\right)D_{403}T+2L_f{i}_{\mathrm{Lf}}\left(0\right)-\\ 2\frac{N_2}{N_1}{V}_{\mathrm{dc}}\left(1-D_{402}\right)T\}{T}_2+\\ [\frac{N_2}{N_1}{V}_{\mathrm{dc}}\left\{\left(D_{403}+2D_{402}-2\right)D_{403}-{\left(1-D_{402}\right)}^2\right\}T-\\ 2V_{\mathrm{bat}}\left\{\left(D_{402}-2D_{403}-2\right)D_{402}+D_{403}\right)\}T+2L_f{i}_{\mathrm{Lf}}\left(0\right)D_{403}]T\end{array}& \left(28\right)\end{array}$

(124) As in the above first operation sub mode, in order to suppress magnetic bias of the transformer 6, I.sub.int needs to be zero. Therefore, from expression (28), the correction period T2 is represented as follows.

(125) $\begin{array}{cc}\left[\mathrm{Mathematical}29\right]& \\ T_2=\frac{{}_2-\sqrt{{}_2^2-4\frac{N_2}{N_1}{V}_{\mathrm{dc}}{}_2}}{2\frac{N_2}{N_1}{V}_{\mathrm{dc}}}& \left(29\right)\end{array}$

(126) It is noted that 2 and 2 in expression (29) are defined as follows.

(127) $\begin{array}{cc}\left[\mathrm{Mathematical}30\right]& \\ {}_2=\left(2\frac{N_2}{N_1}{V}_{\mathrm{dc}}-V_{\mathrm{bat}}\right)D_{403}T+2L_f{i}_{\mathrm{Lf}}\left(0\right)-2\frac{N_2}{N_1}{V}_{\mathrm{dc}}\left(1-D_{402}\right)T& \left(30\right)\\ \left[\mathrm{Mathematical}31\right]& \\ {}_2=\left[\frac{N_2}{N_1}{V}_{\mathrm{dc}}\left\{\left(D_{403}+2D_{402}-2\right)D_{403}-{\left(1-D_{402}\right)}^2\right\}T-2V_{\mathrm{bat}}\left\{\left(D_{402}-2D_{403}-2\right)D_{402}+D_{403}\right)\right\}T+2L_f{i}_{\mathrm{Lf}}\left(0\right)D_{403}]T& \left(31\right)\end{array}$

(128) The correction periods of expression (22) and expression (29) can be calculated from detected values of voltage (V.sub.dc) of the DC capacitor 5 and voltage (V.sub.bat) of the smoothing capacitor 9, and calculated values of a current value (i.sub.Lf) of the smoothing reactor 8, the duty cycle D.sub.401 for the semiconductor switching element 401a, the duty cycle D.sub.402 for the semiconductor switching element 402a, and the phase shift amount D.sub.403 for the second leg, during the device operation. It is noted that the voltage value (V.sub.dc) of the DC capacitor 5 and the voltage value (V.sub.bat) of the smoothing capacitor 9 do not necessarily need to be detected values, but may be target voltages for the respective voltage values, or may be calculated values. In addition, the current value (i.sub.Lf) of the smoothing reactor 8 does not necessarily need to be a calculated value, but may be a detected value detected by a current detector.

(129) In the above description, the case of correcting the phase shift amount D.sub.403 for the second leg has been described. However, the duty cycle (ON period) for the first leg composed of the semiconductor switching element 401a and the semiconductor switching element 402a may be corrected. Also in this case, the duty cycles for the semiconductor switching element 401a and the semiconductor switching element 402a are corrected using similar correction values as in expression (22) and expression (29). That is, the correction of the ON period for the first leg is performed on the basis of the voltage value of the DC capacitor, the voltage value of the smoothing capacitor, the current value of the smoothing reactor, the calculated value of the duty cycle for the first switching element, the duty cycle for the second switching element, and the calculated value of the phase shift amount for the second leg. It is noted that, as described in embodiment 1, the upper limit value of the phase shift amount D.sub.403 depends on the duty cycles D.sub.401 and D.sub.402 for the semiconductor switching elements 401a and 402a, and therefore, in the case where D.sub.401 and D.sub.402 are corrected, the upper limit value of the phase shift amount D.sub.403 is also to be corrected accordingly.

(130) In the present embodiment, processes for generating the gate signal for the semiconductor switching element 401a generated from the duty command value 25 for D.sub.401 and the gate signal for the semiconductor switching element 402a generated from the duty command value 24 for D.sub.402 are the same as in embodiments 1 and 2, and the description thereof is omitted. In the case where a saw-tooth wave is used as a carrier wave as in embodiment 1, processes for generating the gate signals for the semiconductor switching element 403a and the semiconductor switching element 404a generated from the phase shift amount command value 37 and the correction period for the power transmission period, will be described.

(131) FIG. 27 is a calculation block diagram for generating a duty correction value dt for the semiconductor switching element 403a and the semiconductor switching element 404a from the correction periods T1 and T2 calculated by substituting the instantaneous values during the device operations into expression (22) and expression (29), the phase shift amount command value 37 for D.sub.403, and D.sub.limit 28. First, the correction period T1 (57) and the correction period T2 (58) are inputted to a selector (MUX) 59. The selector 59 selects the correction period T1 (57) and the correction period T2 (58) in accordance with a calculation result 60 of magnitude comparison between the phase shift amount command value 37 for D.sub.403 and D.sub.limit 28. If the phase shift amount command value 37 for D.sub.403 is smaller than D.sub.limit 28, the correction period T1 (57) is used as a correction value 61. On the other hand, if the phase shift amount command value 37 for D.sub.403 is greater than D.sub.limit 28, the correction period T2 (58) is used as the correction value 61. A product of the correction value 61 and a switching frequency 62 of the semiconductor switching elements 401a to 404a is outputted as a duty correction value dt63.

(132) As shown in FIG. 28, an addition value 64 obtained by summing the duty correction value dt63 and the phase shift amount command value 37 for D.sub.403, and the saw-tooth wave 38 are inputted to a gate signal generator 65. In addition, the phase shift amount command value 37 for D.sub.403 and the duty command value 24 for D.sub.402 are summed to obtain a phase shift amount signal 66. A difference value 67 between the phase shift amount signal 66 and the duty correction value dt63, and the saw-tooth wave 38 are inputted to a gate signal generator 68. A signal representing a logical conjunction of a comparison signal 69 between the addition value 64 and the saw-tooth wave 38 and a comparison signal 70 between the saw-tooth wave 38 and the difference value 67, is used as a gate signal 71 for the semiconductor switching element 404a. A signal representing a negation of the gate signal 71 is used as a gate signal 72 for the semiconductor switching element 403a. As described above, the gate signals for the semiconductor switching elements 403a and 404a can be generated.

(133) In the above gate signal generation processes, a saw-tooth wave is used for a carrier wave as in embodiment 1. However, as shown in embodiment 2, a triangular wave may be used for a carrier wave.

(134) In the present embodiment, the case of not providing a dead time between the ON period of the semiconductor switching element 401a and the ON period of the semiconductor switching element 402a, has been shown. However, the dead time may be provided. Similarly, a dead time may be provided between the semiconductor switching element 403a and the semiconductor switching element 404a.

(135) In the present embodiment, owing to the above configuration, a stable operation in which a magnetic bias phenomenon in the transformer 6 is suppressed is achieved, and in the above configuration and control, as in the power conversion devices shown in embodiments 1 and 2, it is possible to achieve high-power-factor control and output power control at the same time by a single stage of full-bridge inverter circuit.

DESCRIPTION OF THE REFERENCE CHARACTERS

(136) 1 AC power supply 3 reactor 5 DC capacitor 6 transformer 8 smoothing reactor 9 smoothing capacitor 10 DC load 11 control circuit 200 first rectification circuit 201 to 204 diode element 401a to 404a semiconductor switching element (first to fourth switching elements) 401b to 404b diode 401c to 404c capacitor 700 second rectification circuit 701 to 704 diode