Dynamic amplifier and chip using the same

Abstract

A dynamic amplifier with a bypass design. An input pair of transistors receives a pair of differential inputs Vip and Vin and further provides first, second and third terminals. A load circuit provides a pair of differential outputs Vop and Von with the load circuit connected at a common mode terminal. In an amplification phase, a driver for amplification is coupled to the first terminal and the load circuit is coupled to the second and third terminals. A bypassing circuit is specifically provided. The bypassing circuit is coupled to the second and third terminals during a bypass period within the amplification phase.

Claims

1. A dynamic amplifier, comprising: an input pair of transistors, receiving a pair of differential inputs Vip and Vin and further providing a first terminal, a second terminal and a third terminal; a load circuit, providing a pair of differential outputs Vop and Von with the load circuit coupled to a common mode terminal; a driver for amplification; and a bypassing circuit, operative to decrease currents of the load circuit, wherein: the driver is coupled to the first terminal in an amplification phase; in the amplification phase, the load circuit is coupled to the second terminal and the third terminal; and the bypassing circuit is coupled to the second terminal and the third terminal during a bypass period within the amplification phase.

2. The dynamic amplifier as claimed in claim 1, wherein: the load circuit includes a pair of load capacitors connected at the common mode terminal; and in the amplification phase, the load capacitors are separately coupled to the second terminal and the third terminal.

3. The dynamic amplifier as claimed in claim 2, wherein: the bypassing circuit includes a pair of bypass current sources operative to decrease currents of the load capacitors; and the pair of bypass current sources are separately coupled to the second terminal and the third terminal during the bypass period within the amplification phase.

4. The dynamic amplifier as claimed in claim 3, wherein: the driver for amplification is a current source for amplification which is coupled to the first terminal in the amplification phase.

5. The dynamic amplifier as claimed in claim 3, wherein: the bypass current sources provide variable bypass currents.

6. The dynamic amplifier as claimed in claim 1, wherein: the bypass period covers the amplification phase entirely.

7. The dynamic amplifier as claimed in claim 1, wherein: the bypass period just partially covers the amplification phase.

8. The dynamic amplifier as claimed in claim 7, wherein: the bypass period is arranged when the amplification phase has been on for a while.

9. The dynamic amplifier as claimed in claim 4, wherein: sources of the transistors of the input pair are connected at the first terminal; drains of the transistors of the input pair are regarded as the second terminal and the third terminal; and gates of the transistors of the input pair receive the differential inputs Vin and Vip.

10. The dynamic amplifier as claimed in claim 9, wherein: the amplification phase ends when a predetermined common mode voltage difference, Vcm, for a common mode voltage of the differential outputs Vop and Von is achieved.

11. The dynamic amplifier as claimed in claim 10, providing a gain that is equal to gm.Math.Vcm/(I.sub.1I.sub.2.Math.Tb/T_A), where: gm is a transconductance of each transistor of the input pair; the current source for amplification provides a current of 2.Math.I.sub.1; the bypass current sources each provide a bypass current of I.sub.2; the amplification phase is T_A long; and the bypass period is Tb long.

12. The dynamic amplifier as claimed in claim 9, wherein: the load capacitors are discharged in a reset phase prior to the amplification phase; and the load capacitors are charged in the amplification phase.

13. The dynamic amplifier as claimed in claim 12, wherein: the common mode terminal is ground; and the differential outputs Vop and Von are both pulled down to the ground in the reset phase.

14. The dynamic amplifier as claimed in claim 13, wherein: the differential outputs Vop and Von are raised in the amplification phase.

15. The dynamic amplifier as claimed in claim 12, wherein: the common mode terminal is a power source terminal; and the differential outputs Vop and Von are both connected to the power source terminal in the reset phase.

16. The dynamic amplifier as claimed in claim 15, wherein: the differential outputs Vop and Von drop in the amplification phase.

17. The dynamic amplifier as claimed in claim 9, wherein: the load capacitors are pre-charged in a reset phase prior to the amplification phase; and the load capacitors are discharged in the amplification phase.

18. The dynamic amplifier as claimed in claim 17, wherein: the common mode terminal is ground; and the differential outputs Vop and Von are both connected to a power source terminal in the reset phase.

19. The dynamic amplifier as claimed in claim 18, wherein: the differential outputs Vop and Von drop in the amplification phase.

20. The dynamic amplifier as claimed in claim 1, wherein: the differential outputs Vop and Von are sampled in a sample phase after the amplification phase.

21. A chip, comprising: the dynamic amplifier as claimed in claim 1; a front-stage circuit, transmitting the differential inputs Vip and Vin to the dynamic amplifier; and a back-stage circuit, receiving the differential outputs Vop and Von from the dynamic amplifier.

22. The chip as claimed in claim 21, further comprising: a register for setting a decreased amount of current that the bypassing circuit caused on the load circuit.

23. The chip as claimed in claim 21, further comprising: a register for arranging the bypass period for the dynamic amplifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

(2) FIG. 1 depicts a dynamic amplifier 100 in accordance with an exemplary embodiment of the disclosure;

(3) FIG. 2 shows waveforms of the control signals CS_R, CS_A and CSb and depicts the changes of the differential outputs Vop and Von;

(4) FIG. 3 depicts a dynamic amplifier 300 in accordance with another exemplary embodiment of the disclosure;

(5) FIG. 4 shows waveforms of the control signals CS_R, CS_A and CSb and depicts the changes of the differential outputs Vop and Von with respect to the dynamic amplifier 300;

(6) FIG. 5 depicts a dynamic amplifier 500 in accordance with another exemplary embodiment of the disclosure;

(7) FIG. 6 shows waveforms of the control signals CS_R/CLK, CS_A and CSb and depicts the changes of the differential outputs Vop and Von with respect to the dynamic amplifier 500; and

(8) FIG. 7 depicts a chip 700 comprising a dynamic amplifier 702 in accordance with an exemplary embodiment of the disclosure.

DETAILED DESCRIPTION OF THE INVENTION

(9) The following description shows exemplary embodiments carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

(10) FIG. 1 depicts a dynamic amplifier 100 in accordance with an exemplary embodiment of the disclosure, which includes an input pair 102 of transistors and a pair of load capacitors C1 and C2. A pair of differential inputs Vin and Vip are coupled to the dynamic amplifier 100 by the input pair 102 of transistors. The load capacitors C1 and C2 connected at a common mode terminal (GND in this example) are used to present the amplified signal on a pair of differential outputs Vop and Von.

(11) The dynamic amplifier 100 is operated in three phases, including a reset phase, an amplification phase and a sample phase. In the reset phase, the differential outputs Vop and Von are both reset to a predetermined level (short to ground GND in this example). The dynamic amplifier 100 uses a current source 104 to provide a current 2I.sub.1 for the amplification phase. The current source 104 is coupled to the load capacitors C1 and C2 via the input pair 102 controlled by the differential inputs Vin and Vip. The input pair 102 includes three (connection) terminals n1, n2 and n3. As shown, the sources of the transistors forming the input pair 102 are connected at the connection terminal n1, the drains of the transistors forming the input pair 102 are regarded as the connection terminals n2 and n3, and the gates of the transistors forming the input pair 102 are used to receive the differential inputs Vin and Vip. During the amplification phase, the connection terminal n1 is coupled to the first current source 104 while the connection terminal n2 is coupled to the load capacitor C1 and the connection terminal n3 is coupled to the load capacitor C2. Thus, the voltage levels of the differential outputs Vop and Von change. The amplification phase is ended when a predetermined common mode voltage difference (hereinafter Vcm) is made to a common mode voltage of the differential outputs Vop and Von. The sample phase is provided after the amplification phase to sample the differential outputs Vop and Von.

(12) As shown, a pair of bypass current sources 106 and 108 is specifically provided. The bypass current sources 106 and 108 each are operative to provide a bypass current I.sub.2. During a bypass period within the amplification phase, the connection terminals n2 and n3 are coupled to the bypass current sources 106 and 108, respectively and the current flowing through a load capacitor C1/C2 is (I.sub.1I.sub.2). To achieve the predetermined common mode voltage difference Vcm by the decreased currents, the amplification phase is prolonged and a larger difference is made between the differential outputs Vop and Von. Thus, a larger gain is provided because of the bypass design. The dynamic amplifier 100 has a wide signal swing even in low voltage operation.

(13) In FIG. 1, the switches controlled by the control signal CS_R are turned on in the reset phase, the switches controlled by the control signal CS_A are turned on in the amplification phase, and the switches controlled by the control signal CSb are turned on in the bypass period within the amplification phase. The sample phase is arranged after the enable state of the control signal CS_A. FIG. 2 shows waveforms of the control signals CS_R, CS_A and CSb and depicts the changes of the differential outputs Vop and Von. By the control signal CS_R being enabled during the reset phase T_R, the load capacitors C1 and C2 are discharged and the differential outputs Vop and Von are both reset to the ground level. During the amplification phase T_A, charging currents are provided to charge the load capacitors C1 and C2 and the voltage levels of the differential outputs Vop and Von are raised. Before the bypass period Tb, the charging current for each load capacitor (C1 or C2) is I1. Within the bypass period Tb, the charging current for each load capacitor (C1 or C2) is decreased to (I.sub.1I.sub.2). The amplification phase T_A ends when the predetermined common mode voltage difference Vcm for the common mode voltage of the differential outputs Vop and Von is achieved. The sample phase T_S is arranged after the amplification phase T_A. The sampling circuit not shown here for the differential outputs Vop and Von may be implemented by any signal sampling design. The gain, G, of the dynamic amplifier 100 is gm.Math.Vcm/(I.sub.1I.sub.2.Math.Tb/T_A), where gm is the transconductance of each transistor of the input pair 102. In comparison with a conventional dynamic amplifier providing a gain of gm.Math.Vcm/I.sub.1 without the bypass design, the dynamic amplifier 100 provides a higher gain by the simple bypass design.

(14) In some exemplary embodiments, the current sources 106 and 108 are variable current sources each providing a variable bypass current I.sub.2. In some exemplary embodiments, the bypass period Tb covers the whole amplification phase T_A if a slow charging speed of the load capacitors C1 and C2 is acceptable by the designer. When the bypass period Tb covers the whole amplification phase T_A, the dynamic amplifier 100 has a gain of gm.Math.Vcm/(I.sub.1I.sub.2), which is greater than the limited gain, gm.Math.Vcm/I.sub.1, provided by a conventional dynamic amplifier.

(15) FIG. 3 depicts a dynamic amplifier 300 in accordance with another exemplary embodiment of the disclosure. In comparison with the dynamic amplifier 100 of FIG. 1, the common mode terminal connecting the load capacitors C1 and C2 in FIG. 3 is the power source terminal VDD. FIG. 4 shows waveforms of the control signals CS_R, CS_A and CSb and depicts the changes of the differential outputs Vop and Von with respect to the dynamic amplifier 300. By the control signal CS_R being enabled during the reset phase T_R, the differential outputs Vop and Von are both connected to the power source level (also labeled by VDD). During the amplification phase T_A, currents flow through the load capacitors C1 and C2 to charge the load capacitors C1 and C2 and the voltage levels of the differential outputs Vop and Von are pulled down. In the amplification phase T_A, the current flowing through each load capacitor (C1 or C2) before the bypass period Tb is I1. Within the bypass period Tb, the current flowing through each load capacitor (C1 or C2) is decreased to (I.sub.1I.sub.2). The amplification phase ends when the predetermined common mode voltage difference Vcm for the common mode voltage of the differential outputs Vop and Von is achieved. The sample phase T_S is arranged after the amplification phase T_A. The gain, G, of the dynamic amplifier 300 is effectively improved by the bypass design (referring to the bypass currents I.sub.2).

(16) FIG. 5 depicts a dynamic amplifier 500 in accordance with another exemplary embodiment of the disclosure. Instead of being discharged, the load capacitors C1 and C2 connected at a common mode terminal GND are pre-charged in the reset phase and discharged in the amplification phase. FIG. 6 shows waveforms of the control signals CS_R, CS_A and CSb and depicts the changes of the differential outputs Vop and Von with respect to the dynamic amplifier 500. By the control signal CS_R enabled during the reset phase T_R, the load capacitors C1 and C2 are pre-charged and the differential outputs Vop and Von are both connected to the power source level VDD. In the amplification phase T_A, discharging currents are provided to discharge the load capacitors C1 and C2 and the voltage levels of the differential outputs Vop and Von drops. Before the bypass period Tb, the discharging current for each load capacitor (C1 or C2) is I.sub.1. In the bypass period Tb, the discharging current for each load capacitor (C1 or C2) is decreased to (I.sub.1I.sub.2). The amplification phase T_A ends when the predetermined common mode voltage difference Vcm for the common mode voltage of the differential outputs Vop and Von is achieved. The sample phase T_S is arranged after the amplification phase T_A. The gain, G, of the dynamic amplifier 500 is effectively improved by the bypass design (referring to the bypass currents I.sub.2).

(17) Any dynamic amplifiers using a bypass design for the pair of load capacitors in the amplification phase are considered within the scope of the disclosure.

(18) Note that the dynamic amplifiers of the disclosure use switch components and connect the common mode connection terminal to VDD or GND to remove the unnecessary static currents.

(19) The pair of load capacitors C1 and C2 forming a load circuit may be replaced by other circuits. Any circuit coupled to the common mode terminal and capable of providing the pair of differential outputs Vop and Von can be used to replace the pair of load capacitors C1 and C2 to form the load circuit.

(20) The current source for amplification (e.g. 104) forming a driver may be replaced by other circuits capable of providing driving capability for signal amplification.

(21) The pair of bypass current sources 106 and 108 forming a bypassing circuit may be replaced by other circuits. Any circuit operative to decrease currents of the load circuit can be used to replace the pair of bypass current sources 106 and 108 to form the bypassing circuit.

(22) FIG. 7 depicts a chip 700 comprising a dynamic amplifier 702 in accordance with an exemplary embodiment of the disclosure. The dynamic amplifier 702 uses the bypass design of the disclosure. The chip 700 further comprises a front-stage circuit 704 and a back-stage circuit 706. The front-stage circuit 704 transmits the differential inputs Vip and Vin to the dynamic amplifier 702. The back-stage circuit 706, receiving the differential outputs Vop and Von from the dynamic amplifier 702.

(23) The chip 700 further comprises a register R_i2 for setting variable bypass currents I.sub.2 provided by the bypass current sources of the dynamic amplifier 702. The chip 700 further comprises a register R_Tb for setting the bypass period Tb arranged in the dynamic amplifier 702.

(24) While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.