Dynamic correction of gain error in current-feedback instrumentation amplifiers

Abstract

A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a chopping modulator circuit that continuously swaps tail current sources between the transconductors. This tail current swapping reduces the contribution to the CFIA's gain error caused by random mismatch between the tail currents of the input and feedback transconductors. The modulator circuit operates on a clock cycle to periodically swap the tail current sources. As a result, even if the tail currents are mismatched, on average the tail currents (transconductor gains) will approximately equal out, and the contribution of the tail current difference to the gain error is canceled out.

Claims

1. A method for gain error correction in a current-feedback instrumentation amplifier, said method comprising the steps of: providing an input transconductor comprising a first differential pair of transistors, first degeneration resistors coupled to the first differential pair of transistors, and a first tail current source; providing a feedback transconductor comprising a second differential pair of transistors, second degeneration resistors coupled to the second differential pair of transistors, and a second tail current source; and providing a modulator circuit coupled between the first and second tail current sources, and the first and second degeneration resistors; controlling the modulator circuit by alternating first and second phase signals; wherein during the first phase signal comprises the steps of coupling the first tail current source to the first degeneration resistors and the second tail current source to the second degeneration resistors with the modulator circuit; and wherein during the second phase signal comprises the steps of coupling the first tail current source to the second degeneration resistors, and the second tail current source to the first degeneration resistors with the modulator circuit.

2. The method according to claim 1, wherein gain error caused by a difference between the first and second tail current sources is averaged out during the first and second phases.

3. The method according to claim 1, further comprising the steps of: coupling the input and feedback transconductors to an amplifier; and coupling a feedback network between an output of the amplifier and inputs of the feedback transconductor.

4. The method according to claim 3, wherein the feedback network determines gain of the current-feedback instrumentation amplifier.

5. A current-feedback instrumentation amplifier having gain error correction, comprising: an input transconductor comprising a first differential pair of transistors, first degeneration resistors coupled to the first differential pair of transistors, and a first tail current source; a feedback transconductor comprising a second differential pair of transistors, second degeneration resistors coupled to the second differential pair of transistors, and a second tail current source; and a modulator circuit coupled between the first and second tail current sources, and the first and second degeneration resistors; wherein during a first phase state the modulator circuit couples the first tail current source to the first degeneration resistors and the second tail current source to the second degeneration resistors; and wherein during a second phase state the modulator circuit couples the first tail current source to the second degeneration resistors, and the second tail current source to the first degeneration resistors.

6. The current-feedback instrumentation amplifier according to claim 5, wherein gain error caused by a difference between the first and second tail current sources is averaged out during the first and second phases.

7. The current-feedback instrumentation amplifier according to claim 5, further comprising: an amplifier having inputs coupled to outputs from the input and feedback transconductors; and a feedback network coupled between an output of the amplifier and inputs of the feedback transconductor.

8. The current-feedback instrumentation amplifier according to claim 7, wherein the feedback network comprises: a first feedback resistor; a second feedback resistor; and a voltage reference; the first and second feedback resistors and the voltage reference are connected in series; a first input of the feedback transconductor is coupled to a node between the second feedback resistor and the voltage reference; a second input of the feedback transconductor is coupled to a node between the first feedback resistor and the second feedback resistor; and the output of the amplifier is coupled to the first feedback resistor; wherein gain is determined by a ratio of resistance values of the first and second feedback resistors.

9. The current-feedback instrumentation amplifier according to claim 5, wherein the input transconductor has a positive input and a negative input.

10. The current-feedback instrumentation amplifier according to claim 5, wherein the modulator circuit comprises: a first switch coupled between the first tail current source and the first degeneration resistors; a second switch coupled between the first tail current source and the second degeneration resistors; a third switch coupled between the second tail current source and the first degeneration resistors; and a fourth switch coupled between the second tail current source and the second degeneration resistors; wherein the first and fourth switches are closed and the second and third switches are open on a first phase state control signal; and the second and third switches are closed and the first and fourth switches are open on a second phase state control signal.

11. The current-feedback instrumentation amplifier according to claim 10, wherein the first and second phase state control signals are from a clock generator, wherein the first control signal is at a first logic level and the second control signal is at a second logic level.

12. The current-feedback instrumentation amplifier according to claim 10, wherein the first, second, third and fourth switches are metal oxide semiconductor field effect transistors (MOSFETs).

13. The current-feedback instrumentation amplifier according to claim 12, wherein the MOSFETs are P-channel MOSFETs.

14. The current-feedback instrumentation amplifier according to claim 12, wherein the MOSFETs are N-channel MOSFETs.

15. The current-feedback instrumentation amplifier according to claim 5, further comprising transistors at inputs and outputs of the modulator circuit for providing low impedance nodes to maintain substantially equal electrical potentials thereon regardless of input voltages to the input and feedback transconductors.

16. The current-feedback instrumentation amplifier according to claim 5, wherein the input and feedback transconductors are fabricated on an integrated circuit die.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:

(2) FIG. 1 illustrates a schematic diagram of a prior art current-feedback instrumentation amplifier that uses preamplifiers;

(3) FIG. 2 illustrates a schematic diagram of a prior art current-feedback instrumentation amplifier with degenerated differential pairs;

(4) FIG. 3 illustrates a schematic diagram of a current-feedback instrumentation amplifier comprising a tail current source modulator circuit, according to a specific example embodiment of this disclosure;

(5) FIG. 4A illustrates a schematic diagram of the current-feedback instrumentation amplifier shown in FIG. 3 in a first phase state;

(6) FIG. 4B illustrates a schematic diagram of the current-feedback instrumentation amplifier shown in FIG. 3 in a second phase state;

(7) FIG. 5A illustrates a schematic diagram of a current-feedback instrumentation amplifier comprising a tail current source modulator circuit placed between low-impedance nodes, according to another specific example embodiment of this disclosure;

(8) FIG. 5B illustrates a schematic diagram of an example modulator circuit for use in the current-feedback instrumentation amplifiers of FIGS. 3 and 5A;

(9) FIG. 6 illustrates a schematic diagram of a current-feedback instrumentation amplifier comprising modulator circuits and split tail current sources, according to yet another specific example embodiment of this disclosure;

(10) FIG. 7 illustrates a schematic diagram of a current-feedback instrumentation amplifier without degeneration resistors and comprising a tail current source modulator circuit, according to still another specific example embodiment of this disclosure;

(11) FIG. 8 illustrates a schematic diagram of a current-feedback instrumentation amplifier comprising a tail current source modulator circuit, according to another specific example embodiment of this disclosure; and

(12) FIG. 9 illustrates a schematic diagram of a current-feedback instrumentation amplifier comprising a tail current source modulator circuit placed between low-impedance nodes, according to still yet another specific example embodiment of this disclosure.

(13) While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the forms disclosed herein.

DETAILED DESCRIPTION

(14) In accordance with some embodiments of the disclosed subject matter, the present disclosure provides a current feed-back instrumentation amplifier (CFIA) fabricated on an integrated circuit die and comprising a circuit architecture that is based on a differential pair with degeneration. The present CFIA includes a modulator circuit that reduces the contribution to the CFIA's gain error of random mismatch between the tail currents of the input and feedback transconductors. The modulator circuit operates on a clock cycle to periodically swap the tail currents of each transconductor with each other. As a result, even if the tail currents are mismatched, on average the tail currents (related to the transconductor gain) will be approximately equal, and the contribution of the tail current difference to the gain error is canceled out.

(15) The present disclosure is directed toward an architecture for a CFIA comprising differential pair transistors with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The present architecture employs chopping (e.g., dynamic correction) of the tail current sources for each transconductor to average out the tail current values in each transconductor, reducing mismatch and improving overall gain error and linearity. To dynamically correct the tail currents, the device includes a modulator circuit electrically coupled between the tail currents to input and feedback transconductors. The modulator circuit may include a circuit comprising four switches that operate in two phases controlled by a clock signal: in phase 1, the switches allow the corresponding tail current to flow into each transconductor; in phase 2, the switches operate to swap the tail currents, so that the previous input tail current flows into the feedback transconductor and the previous feedback tail current flows into the input transconductor.

(16) Referring now to the drawings, the details of example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower-case letter suffix.

(17) Referring now to FIG. 2, depicted is a schematic diagram of a prior art current-feedback instrumentation amplifier. An example current-feedback instrumentation amplifier (CFIA), generally represented by the numeral 200, may use a differential pair with degeneration architecture. The CFIA 200 includes an input transconductor G.sub.m,IN that operates on differential input voltages V.sub.INP and V.sub.INN, and a feedback transconductor G.sub.m,FB that operates on feedback voltages V.sub.FBN and V.sub.FBP. Each transconductor (G.sub.m,IN and G.sub.m,FB) has a tail current source I.sub.TAIL,IN and I.sub.TAIL,FB, respectively. Each transconductor (G.sub.m,IN and G.sub.m,FB) includes degeneration resistors R.sub.D,IN, and R.sub.D,FB, respectively. A first pair of transistors M.sub.1a and M.sub.1b (for G.sub.m,IN), and a second pair of transistors M.sub.1c and M.sub.1d (for G.sub.m,FB). Both transconductors (G.sub.m,IN and G.sub.m,FB) are coupled together and output a signal to an amplifier AR as shown in FIG. 2.

(18) The gain of the CFIA may be defined as Gain=G.sub.m,IN/G.sub.m,FB*(1+R.sub.1/R.sub.2) and the Gain error=G.sub.m,IN/G.sub.m,FB1, where it is assumed the matching between the external resistors R.sub.1 and R.sub.2 is much better than the match between G.sub.m,IN and G.sub.m,FB. For the CFIA 200,

(19) $G_{m,\mathrm{IN}}=\frac{g_{m1\mathrm{ab}}}{2+g_{m1\mathrm{ab}}{R}_{D,\mathrm{IN}}}\mathrm{and}{G}_{m,\mathrm{FB}}=\frac{g_{m1\mathrm{cd}}}{2g_{m1\mathrm{cd}}{R}_{D,\mathrm{FB}}},$
where g.sub.m1ab is the transconductance of transistors M.sub.1a and M.sub.1b, and g.sub.m1cd is the transconductance of transistors M.sub.1b and M.sub.1d, and R.sub.D,IN and R.sub.D,FB have already been defined above. For simplicity, it is assumed there is no mismatch between M.sub.1a and M.sub.1b and they have the same transconductance, g.sub.m1ab. Likewise, it is assumed there is no mismatch between M.sub.1c and M.sub.1d and they have the same transconductance g.sub.m1cd. For convenience, one usually choses g.sub.m1ab=g.sub.m1cd, and R.sub.D,IN=R.sub.D,FB, such that the ratio G.sub.m,IN/G.sub.m,FB may be unity. For transistors operating in the sub-threshold region

(20) $g_{m1\mathrm{ab}}=\frac{I_{\mathrm{TAIL},\mathrm{IN}}}{2n_{\mathrm{ab}}{V}_{T,\mathrm{ab}}}\mathrm{and}{g}_{m1\mathrm{ab}}=\frac{I_{\mathrm{TAIL},\mathrm{FB}}}{2n_{\mathrm{cd}}{V}_{T,\mathrm{cd}}},$
where I.sub.TAIL,IN and I.sub.TAIL,FB are the tail currents of G.sub.m,IN and G.sub.m,FB, respectively; n.sub.ab and n.sub.cd are the sub-threshold constants of transistors M.sub.1a and M.sub.1b, and M.sub.1c and M.sub.1d, respectively; and V.sub.T,ab and V.sub.T,cd the thermal voltages of M.sub.1a and M.sub.1b, and M.sub.1c and M.sub.1d, respectively. The gain error will therefore depend on the matching between R.sub.D,IN and R.sub.D,FB, I.sub.TAIL,IN and I.sub.TAIL,FB, n.sub.ab and n.sub.cd, and V.sub.T,ab and V.sub.T,cd. In the ideal case, R.sub.D,IN=R.sub.D,FB, I.sub.TAIL,IN=I.sub.TAIL,FB, n.sub.ab=n.sub.cd, V.sub.T,ab=V.sub.T,cd, and the gain error is zero This disclosure addresses the contribution of the mismatch between the two I.sub.TAIL currents to the overall gain error.

(21) Although the above description was based on the assumption that the transistors M.sub.1a, M.sub.1b, M.sub.1c and M.sub.1d operate in the sub-threshold (or weak inversion) region, this invention is not limited to this particular region, e.g., it is equally valid for transistors operating in the saturation region.

(22) Referring now to FIG. 3, depicted is a schematic diagram of a current-feedback instrumentation amplifier comprising a tail current source modulator circuit, according to a specific example embodiment of this disclosure. A CFIA, generally represented by the numeral 300, may use the circuit architecture shown in FIG. 3 to minimize or substantially eliminate the contribution of mismatch between I.sub.TAIL,IN and I.sub.TAIL,FB to the CFIA gain error. In some embodiments, the CFIA 300 may comprise the CFIA 200 architecture shown in FIG. 2 and a modulator circuit 302 disposed between the tail current sources I.sub.TAIL,IN and I.sub.TAIL,FB and the degeneration resistors R.sub.D,IN and R.sub.D,FB. The modulator circuit 302 implements dynamic correction of the tail current mismatch by periodically swapping tail current sources I.sub.TAIL,IN and I.sub.TAIL,FB. In some embodiments, the modulator circuit 302 may operate based on input received as one or more regulated signals phi1 and phi2, e.g., provided by a clock or another regulating circuit. In an example implementation, the regulated signals phi1 and phi2 alternately switch between low and high logic levels every half clock cycle, swapping the tail current sources between transconductors G.sub.m,IN and G.sub.m,FB twice every clock cycle. This approach allows the portion of the gain error contributed by mismatched tail currents to be continuously corrected during operation of the CFIA 300.

(23) Referring to FIGS. 4A and 4B, depicted are schematic diagrams of the current-feedback instrumentation amplifier shown in FIG. 3 in first and second phase states, respectively. The modulator circuit 302 of FIG. 3, may include four switches 302A-302D that may be adapted to alternately connect each tail current, I.sub.TAIL,IN and I.sub.TAIL,FB, in the transconductors G.sub.m,IN and G.sub.m,FB. The regulated signals phi1 and phi2 may be provided from a clock signal and are shown to be in opposite phase, such that phi1 is low when phi2 is high, and vice-versa. As shown in FIG. 4A, when phi1 is low and phi2 is high, the outer switches 302A and 302D are closed, and the inner switches 302B and 302C are open. As shown in FIG. 4B, when the desired period (e.g., a clock cycle, clock half-cycle, etc.) elapses the values of the regulated signals phi1, phi2 flip; whereby phi1 is high and phi2 is low, the outer switches 302A and 302D are open, and the inner switches 302B and 302C are closed.

(24) To illustrate how the current invention corrects the effect of tail current mismatch to gain error, it may be assumed that the tail current of G.sub.m,IN, I.sub.TAIL,IN has a nominal value of I.sub.TAIL, while the tail current of transconductor G.sub.m,FB suffers from a random mismatch denoted by such that its value is I.sub.TAIL,FB=I.sub.TAIL+*I.sub.TAIL. During a first phase (phi1 low and phi2 highsee FIG. 4A) the baseline current I.sub.TAIL flows into the input transconductor G.sub.m,IN and the mismatched tail current (1+)*I.sub.TAIL flows into the feedback transconductor G.sub.m,FB. The transconductance of transistors M.sub.1a and M.sub.1b, g.sub.m1ab will have a nominal value equal to g.sub.m, while the transconductance of M.sub.1c and M.sub.1d will suffer from an equal mismatch, , g.sub.m1cd=g.sub.m+*g.sub.m; G.sub.m,IN will be equal to a nominal value G.sub.m, while G.sub.m,FB will be approximately equal to G.sub.m(1+). Therefore, during this phase, the gain error will be approximately . Then in the second phase (phi1 high and phi2 lowsee FIG. 4B) the modulator circuit 302 switches the tail current sources, and the baseline current I.sub.TAIL flows into the feedback transconductor G.sub.m,FB and the mismatched tail current (1+)*I.sub.TAIL flows into the input transconductor G.sub.m,IN. During this cycle, G.sub.m,IN will be G.sub.m(1+), G.sub.m,FB will be equal to G.sub.m, and the gain error will be approximately +. If during one half clock cycle, the gain error is , and during the other half clock cycle +, over a complete clock cycle the gain error will be on average zero. Thus, the modulator circuit 302 provides a continuous correction of the gain error during CFIA 300 operation.

(25) Additionally, the implemented architecture provides other operative advantages, including without limitation: low noise-to-power ratio, substantially no effect of temperature or process variation on functionality; no post-production trimming of components required; reduced test time and cost; area-efficient architecture, requiring as new components only four switches comprising the modulator circuit, using existing infrastructure such as oscillators and ripple filters for offset voltage (caused by swapping tail currents) correction, and not needing additional memory (e.g., non-volatile memory to store trimming values).

(26) Additionally, various embodiments of the present CFIA architecture are suitable for high-voltage designs, even when the difference between the common-mode voltage on the input pins V.sub.INP and V.sub.INN, and the common-mode voltage on the feedback pins V.sub.FBP and V.sub.FBN is large (e.g., over five (5) volts).

(27) Referring to FIG. 5A, depicted is a schematic diagram of a current-feedback instrumentation amplifier comprising a tail current source modulator circuit placed between low-impedance nodes, according to another specific example embodiment of this disclosure. In the CFIA architecture, generally represented by the numeral 500, a modulator circuit 502 swaps tail current sources between transconductors G.sub.m,IN and G.sub.m,FB in accordance with the description of the circuit architecture shown in FIG. 3.

(28) Referring to FIG. 5B, depicted is a schematic diagram of an example modulator circuit for use in the current-feedback instrumentation amplifiers of FIGS. 3 and 5A. As shown in FIGS. 5A and 5B, the modulator circuit 502 may be placed between low-impedance nodes (e.g., between transistors M.sub.4a and M.sub.4ca, and M.sub.4b and M.sub.4cb) that carry the tail currents of the respective transconductors. For example, switch 502A may be disposed between transistors M.sub.4a and M.sub.4ca, switch 502B may be disposed between transistors M.sub.4a and M.sub.4cb, switch 502C may be disposed between transistors M.sub.4b and M.sub.4ca, and switch 502D may be disposed between transistors M.sub.4b and M.sub.4cb; to control the flow of the tail currents as described above with respect to the modulator circuit 302 of FIGS. 3A and 3B. The low-impedances between the transistors M.sub.4a and M.sub.4ca, and M.sub.4b and M.sub.4cb may be maintained at substantially equal electrical potentials regardless of the common mode voltages of nodes V.sub.INP and V.sub.INN, and V.sub.FBP and V.sub.FBN on the respective transconductors. In one embodiment, substantially equal potentials may be maintained through the operation of cascode transistors M.sub.4ca and M.sub.4cb on both the input and output sides of the modulator circuit 502. The switches 502 may be transistors 502A-502D, and these transistors may be metal oxide semiconductor field effect transistors (MOSFETs). Likewise, transistors M.sub.4a, M.sub.4ca, M.sub.4b and M.sub.4cb may be MOSFETs.

(29) Referring to FIG. 6, depicted is a schematic diagram of a current-feedback instrumentation amplifier comprising modulator circuits and split tail current sources, according to yet another specific example embodiment of this disclosure. A CFIA, generally represented by the numeral 600, may use the circuit architecture shown to minimize or substantially eliminate the CFIA gain error from the mismatches between the tail currents to the transconductor G.sub.m,IN, and the transconductor G.sub.m,FB. Instead of using one tail current source for each of the transconductors, and splitting (dividing by two through resistors R.sub.D/2) the current from each tail current source to the differential transistor pairs, two tail current sources for each transconductor, one for each of the differential pair transistors of a transconductor may be provided.

(30) The modulator circuits 602 and 604 implement dynamic correction, as more fully described in FIGS. 3, 4A and 4B above, of the tail current mismatch by periodically swapping each of tail current sources of the input transconductor and the feedback transconductor; thus, during one period the baseline tail currents I.sub.TAIL,IN/2 flow into each of the transistors comprising the input transconductor G.sub.m,IN and the mismatched tail currents I.sub.TAIL,FB flow into each of the transistors comprising the feedback transconductor G.sub.m,FB, then the modulator circuits 602 and 604 switch the tail current sources, and during the next period the baseline currents I.sub.TAIL,IN/2 flow into each of the transistors comprising the feedback transconductor G.sub.m,FB and the mismatched tail currents I.sub.TAIL,FB flow into each of the transistors comprising the input transconductor G.sub.m,IN. In some embodiments, the modulator circuits 602 and 604 may operate based on inputs received as one or more regulated signals phi1 and phi2, e.g., provided by a clock or another regulating circuit. In an example implementation, the regulated signals phi1 and phi2 alternately switch between low and high logic levels every half clock cycle, swapping the tail current sources between transconductors G.sub.m,IN and G.sub.m,FB twice every clock cycle; during one half clock cycle, the gain error will be roughly equal to , and during the other half clock cycle, the gain error will be roughly equal to +, so that the gain error over a complete clock cycle averages out to zero. This approach allows the portion of the gain error contributed by mismatched tail currents to be continuously corrected during operation of the CFIA 600.

(31) Referring to FIG. 7, depicted is a schematic diagram of a current-feedback instrumentation amplifier without degeneration resistors and comprising a tail current source modulator circuit, according to still another specific example embodiment of this disclosure. Tail current swapping can be effective for reducing gain error even without the degeneration resistors used in the CFIAs 300, 500 and 600. Operation of the CFIA 700 shown in FIG. 7 operates in substantially the same fashion as the CFIA 300 described hereinabove, but is configured without degeneration resistors R.sub.D (FIG. 3).

(32) Referring to FIG. 8, depicted is a schematic diagram of a current-feedback instrumentation amplifier comprising a tail current source modulator circuit, according to another specific example embodiment of this disclosure. The CFIA 800 shown in FIG. 8 is configured and operates in substantially the same fashion as the CFIA 300 described hereinabove, but its architecture comprises N-channel MOSFETS instead of P-channel MOSFETS (FIG. 3).

(33) Referring to FIG. 9, depicted is a schematic diagram of a current-feedback instrumentation amplifier comprising a tail current source modulator circuit placed between low-impedance nodes, according to still yet another specific example embodiment of this disclosure. The CFIA 900 shown in FIG. 9 is configured and operates in substantially the same fashion as the CFIA 500 described hereinabove, but its architecture comprises N-channel MOSFETS instead of P-channel MOSFETS (FIG. 5).

(34) The present invention has been described in terms of one or more preferred embodiments, and it should be appreciated that many equivalents, alternatives, variations, and modifications, aside from those expressly stated (e.g., methods of manufacturing, product by process, and so forth), are possible and within the scope of the invention.