Apparatus for mitigating wandering spurs in a fractional-N frequency synthesizer

Abstract

The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L error feedback modulator (EFM) stages, wherein the jth EFM stage is configured to receive as an input the sum of the error of the preceding EFM stage and a high amplitude dither signal derived from the error of the kth EFM stage, where 1≤j≤k≤L.

Claims

1. A fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise shaping (MASH) digital delta-sigma modulator comprising L Error Feedback Modulator (EFM) stages, wherein a jth EFM stage is configured to receive as an input a sum of an error of a preceding EFM stage and a high amplitude dither signal, wherein the high amplitude dither signal comprises an integer dither signal derived from an error of a kth EFM stage, where 1≤j≤k≤L.

2. The fractional-N frequency synthesizer of claim 1, wherein the MASH digital delta-sigma modulator comprises a MASH digital delta-sigma modulator with additive first-order shaped dither.

3. The fractional-N frequency synthesizer of claim 1, wherein the MASH digital delta-sigma modulator comprises a MASH 1-1-1 architecture.

4. The fractional-N frequency synthesizer of claim 1, wherein each of the L EFM stages comprises a first-order error feedback modulator (EFM).

5. A fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L Error Feedback Modulator (EFM) stages, wherein a jth EFM stage is configured to receive as an input a sum of an error of a preceding EFM stage and a high amplitude dither signal derived from an error of a kth EFM stage, where 1≤j≤k≤L, wherein the high amplitude dither signal comprises a dither signal which is obtained by passing the error of the kth EFM stage through a filter block with a dither transfer function DT(z).

6. The fractional-N frequency synthesizer of claim 5, wherein the dither transfer function is DT(z)=z.sup.−2.

7. The fractional-N frequency synthesizer of claim 5, wherein the dither transfer function is DT(z)=−z.sup.−1+2z.sup.−2.

8. The fractional-N frequency synthesizer of claim 5, wherein the dither transfer function is DT(z)=−2z.sup.−1+2z.sup.−2.

9. The fractional-N frequency synthesizer of claim 5, wherein the dither transfer function is DT(z)=2z.sup.−2−2z.sup.−3.

10. The fractional-N frequency synthesizer of claim 5, wherein the MASH digital delta-sigma modulator comprises a MASH digital delta-sigma modulator with additive first-order dither.

11. The fractional-N frequency synthesizer of claim 5, wherein the MASH digital delta-sigma modulator comprises a MASH 1-1-1 architecture, and wherein each of the L EFM stages comprises a first-order error feedback modulator (EFM).

12. The fractional-N frequency synthesizer of claim 5, wherein j=3.

13. A fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising a MASH 1-1-1 architecture with additive first-order dither comprising a first EFM stage, a second EFM stage and a third EFM stage, and wherein the third EFM stage of the MASH architecture is configured to receive as an input a sum of an error of the second EFM stage and a high amplitude dither signal derived from passing an error of the third EFM stage through a filter block.

14. The fractional-N frequency synthesizer of claim 13, wherein the high amplitude dither signal is filtered in accordance with the equation:
Y(z)=(1/M)*[X(z)+(1−z.sup.−1)D.sub.1(z)+(1−z.sup.−1).sup.3E.sub.3(z)+(1−z.sup.−1).sup.2DT(z)E.sub.3(z)] where Y corresponds to a Z-transform of an output signal of the MASH 1-1-1 architecture; X corresponds to the Z-transform of an input signal to the MASH 1-1-1 architecture; D.sub.1 corresponds to the Z-transform of an additive first-order dither signal; DT(z) corresponds to a dither transfer function of the filter block; and E.sub.3 corresponds to the Z-transform of the error of the third EFM stage of the MASH 1-1-1 architecture.

15. The fractional-N frequency synthesizer of claim 14, wherein the dither transfer function is DT(z)=z.sup.−2.

16. The fractional-N frequency synthesizer of claim 14, wherein the dither transfer function is DT(z)=−z.sup.−1+2z.sup.−2.

17. The fractional-N frequency synthesizer of claim 14, wherein the dither transfer function is DT(z)=−2z.sup.−1+2z.sup.−2.

18. The fractional-N frequency synthesizer of claim 14, wherein the dither transfer function is DT(z)=2z.sup.−2−2z.sup.−3.

19. The fractional-N frequency synthesizer of claim 13, wherein the second EFM stage of the MASH 1-1-1 architecture is configured to receive as an input a sum of an error of the first EFM stage and a binary dither signal.

20. The fractional-N frequency synthesizer of claim 13, wherein each EFM stage comprises a first-order error feedback modulator (EFM).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure will be more clearly understood from the following description of an embodiment thereof, given by way of example only, with reference to the accompanying drawings, in which:—

(2) FIG. 1 shows a block diagram of a conventional fractional-N frequency synthesizer;

(3) FIG. 2 shows a block diagram of a conventional divider controller based on a Multi stAge noise SHaping (MASH) digital delta-sigma modulator with shaped additive dither;

(4) FIG. 3 shows a block diagram of a conventional Error Feedback Modulator (EFM);

(5) FIG. 4 shows a block diagram of a conventional additive LSB-dithered MASH 1-1-1 divider controller with first-order shaped additive dither;

(6) FIG. 5 is a spectrogram showing a typical manifestation of wandering spurs in the frequency domain in a fractional-N frequency synthesizer with a MASH 1-1-1 divider controller architecture;

(7) FIG. 6 shows a block diagram of a MASH 1-1-1 divider controller with first-order shaped dither and externally sourced additive high amplitude dither;

(8) FIG. 7A shows simulated spectrograms of the distorted accumulated error of the MASH 1-1-1 divider controller of FIG. 4;

(9) FIG. 7B shows simulated spectrograms of the distorted accumulated error of the MASH 1-1-1 divider controller with externally sourced additive high amplitude dither of FIG. 6;

(10) FIG. 8 shows a block diagram of an embodiment of a high amplitude dithered MASH divider controller in accordance with the present disclosure, where the high amplitude dither signal is derived from the error of the kth EFM stage and is added to the input of the jth EFM stage;

(11) FIG. 9 shows a block diagram of an embodiment of a high amplitude dithered MASH 1-1-1 divider controller in accordance with the present disclosure, where the high amplitude dither signal is derived from the error of the third EFM stage;

(12) FIG. 10A shows simulated spectrograms of the distorted accumulated error signal of the MASH 1-1-1 divider controller of FIG. 4;

(13) FIG. 10B shows simulated spectrograms of the distorted accumulated error signal of a first embodiment of a high amplitude dithered MASH 1-1-1 divider controller in accordance with the present disclosure;

(14) FIG. 11A shows simulated spectrograms of the distorted accumulated error signal of the MASH 1-1-1 divider controller of FIG. 4;

(15) FIG. 11B shows simulated spectrograms of the distorted accumulated error signal of a third embodiment of a high amplitude dithered MASH 1-1-1 divider controller in accordance with the present disclosure;

(16) FIG. 12A shows simulated spectrograms of the distorted accumulated error signal of the MASH 1-1-1 divider controller of FIG. 4;

(17) FIG. 12B shows simulated spectrograms of the distorted accumulated error signal of a fourth embodiment of a high amplitude dithered MASH 1-1-1 divider controller in accordance with the present disclosure;

(18) FIG. 13A shows simulated spectra of the accumulated error signal for the MASH 1-1-1 divider controller of FIG. 4 and two described embodiments of the high amplitude dithered divider controller of the present disclosure with second-order noise shaping; and

(19) FIG. 13B shows simulated spectra of the accumulated error signal for the MASH 1-1-1 divider controller of FIG. 4 and two described embodiments of the high amplitude dithered divider controller of the present disclosure with third-order noise shaping.

DETAILED DESCRIPTION

(20) The present disclosure provides a fractional-N frequency synthesizer which reduces the effect of wandering spurs exhibited by the synthesizer when operating with a higher resolution DDSM-based divider controller. The present disclosure will now be described in conjunction with FIG. 8 onwards.

(21) Wandering spurs are caused by interaction between the signal injected by a DDSM-based divider controller and a synthesizer's phase-locked loop.

(22) FIG. 8 shows one embodiment of the present disclosure where the DDSM incorporated into the synthesizer comprises a modified MASH divider controller. The MASH divider controller comprises a cascade of L number of first-order Error Feedback Modulators (EFM). The MASH is known to suffer from limit cycles. Therefore, a binary dither signal, denoted d.sub.1, is added to e.sub.1 and the sum is applied as input to the second EFM stage to mitigate limit cycle behavior. The MASH divider controller is further modified by adding a high-amplitude dither to the input of the jth EFM stage of the MASH architecture, where j≥1. The high amplitude dither signal is produced by passing the error signal from the kth EFM stage through a filter with transfer function DT(z), where j≤k≤L.

(23) FIG. 9 shows one embodiment of the present disclosure where the DDSM incorporated into the synthesizer comprises a modified MASH 1-1-1 divider controller. The MASH 1-1-1 divider controller comprises a cascade of three first-order Error Feedback Modulators (EFM). Firstly, a binary dither signal, denoted d.sub.1, is added to e.sub.1 and the sum is applied as input to the second EFM stage to mitigate limit cycle behavior.

(24) The MASH 1-1-1 divider controller is further modified by adding a high-amplitude dither to the input of the third EFM stage of the MASH architecture.

(25) The dither signal d.sub.2 is obtained by passing the error of the third EFM stage e.sub.3 through a filter block with a dither transfer function DT(z), as shown in FIG. 9, where j=3, k=3, and
D.sub.2(z)=DT(z)E.sub.3(z).

(26) In one embodiment, the dither transfer function is DT(z) is a polynomial in z.sup.−1 of the form

(27) $DT\left(z\right)=\underset{k-1}{\overset{P}{.Math.}}{a}_k{z}^{-k},$

(28) where each coefficient a.sub.k is a real number and P≥1 is an integer.

(29) This dither signal is second-order high pass filtered when it appears at the output. In the z domain,

(30) $\begin{array}{c}Y\left(z\right)={\left(1/M\right)}^{*}\left[X\left(z\right)+\left(1-z^{-1}\right)D_1\left(z\right)-{\left(1-z^{-1}\right)}^3{E}_3\left(z\right)+{\left(1-z^{-1}\right)}^2{D}_2\left(z\right)\right]\\ ={\left(1/M\right)}^{*}\left[X\left(z\right)+\left(1-z^{-1}\right)D_1\left(z\right)-{\left(1-z^{-1}\right)}^3{E}_3\left(z\right)+{\left(1-z^{-1}\right)}^2\mathrm{DT}\left(z\right)E_3\left(z\right)\right]\\ ={\left(1/M\right)}^{*}\left[X\left(z\right)+\left(1-z^{-1}\right)D_1\left(z\right)+{\left(1-z^{-1}\right)}^2\left(-1+z^{-1}+\mathrm{DT}\left(z\right)\right)E_3\left(z\right)\right],\end{array}$

(31) where Y, X, D.sub.1, D.sub.2 and E.sub.3 are the Z-transforms of y, x, the dither signals d.sub.1 and d.sub.2, and the error of the third EFM stage, and DT(z) is the transfer function of the filter block in FIG. 9.

(32) The dither transfer function can be chosen to shape the additional noise introduced by adding DT(z)E.sub.3(z) to e.sub.2 and applying the sum as input to the third EFM stage.

(33) In a first embodiment, the dither transfer function is DT(z)=z.sup.−2.

(34) In a second embodiment, the dither transfer function is DT(z)=−z.sup.−1+2z.sup.−2.

(35) In a third embodiment, the dither transfer function is DT(z)=−2z.sup.−1+2z.sup.−2.

(36) In a fourth embodiment, the dither transfer function is DT(z)=2z.sup.−2−2z.sup.−3.

(37) When DT(z)=z.sup.−2 and DT(z)=−z.sup.−1+2z.sup.−2, the additional noise is second-order shaped. When DT(z)=−2z.sup.−1+2z.sup.−2 and DT(z)=2z.sup.−2−2z.sup.−3 the additional noise is third-order shaped. Choosing coefficients a.sub.k of the dither transfer function that are positive or negative powers of two simplifies the realization of DT(z) in hardware.

(38) The wandering spur phenomenon is caused by a chirp signal that is produced at the input to the VCO. This chirp has its origin in the DDSM. By adding high amplitude dither to the input of the jth EFM stage of the MASH divider controller where j≥1, it swamps the chirp signal and eliminates the wandering spur.

(39) FIG. 10A shows simulated spectrograms of the distorted accumulated error signal of the MASH 1-1-1 divider controller of FIG. 4 and FIG. 10B shows simulated spectrograms of the distorted accumulated error signal of the high amplitude dithered MASH 1-1-1 divider controller of FIG. 9 for the first embodiment of the dither transfer function where DT(z)=z.sup.−2 after passing through a piecewise-linear nonlinearity with 8% mismatch (x=2 and M=2.sup.20). By comparison with FIG. 10A, it can be seen from FIG. 10B that the addition of the dither signal D.sub.2(z)=z.sup.−2E.sub.3(z) results in the elimination of wandering spurs in the spectrogram of the distorted signal.

(40) FIG. 11A shows simulated spectrograms of the distorted accumulated error signal of the MASH 1-1-1 divider controller of FIG. 4 and FIG. 11B shows simulated spectrograms of the distorted accumulated error signal of the high amplitude dithered MASH 1-1-1 divider controller of FIG. 9 for the third embodiment of the dither transfer function where DT(z)=−2z.sup.−1(1−z.sup.−1) after passing through a piecewise-linear nonlinearity with 8% mismatch (x=1 and M=2.sup.20). By comparison with FIG. 11A, it can be seen from FIG. 11B that the addition of the dither signal D.sub.2(z)=−2z.sup.−1(1−z.sup.−1) E.sub.3(z) results in the elimination of wandering spurs in the spectrogram of the distorted signal.

(41) FIG. 12A shows simulated spectrograms of the distorted accumulated error signal of the MASH 1-1-1 divider controller of FIG. 4 and FIG. 12B shows simulated spectrograms of the distorted accumulated error signal of the high amplitude dithered MASH 1-1-1 divider controller of FIG. 9 for the fourth embodiment of the dither transfer function where with DT(z)=2z.sup.−2(1−z.sup.−1) after passing through a piecewise-linear nonlinearity with 8% mismatch (M=2.sup.20 and x=M/2). By comparison with FIG. 12A, it can be seen from FIG. 12B that the addition of the dither signal D.sub.2(z)=2z.sup.−2(1−z.sup.−1) E.sub.3(z) results in the elimination of wandering spurs in the spectrogram of the distorted signal.

(42) The addition of a high amplitude dither signal d.sub.2 increases the spectral envelope of the noise introduced into a frequency synthesizer by the DDSM. FIG. 13A shows spectra for the MASH 1-1-1 of FIG. 4 and the high amplitude dithered divider controller of the present disclosure of FIG. 9 for the first embodiment where DT(z)=z.sup.−2 and for the second embodiment where DT(z)=−z.sup.−1+2z.sup.−2. FIG. 13B shows spectra for the MASH 1-1-1 of FIG. 4 and the high amplitude dithered divider controller of the present disclosure of FIG. 9 for the third embodiment where DT(z)=−2z.sup.−1(1−z.sup.−1), and for the fourth embodiment where DT(z)=2z.sup.−2(1−z.sup.−1).

(43) When incorporated in a frequency synthesizer with nonlinear distortion, the modified MASH 1-1-1 divider controller does not exhibit wandering spurs. Furthermore, the dither signal d.sub.2 is produced by scaling and combining current and past samples of the error signal using a filter with transfer function DT(z). This obviates the need for an additional random signal source to provide the dither signal d.sub.2 and thus represents a saving in hardware and power.

(44) Thus, it will be appreciated that the fractional-N frequency synthesizer of the present disclosure provides a divider controller signal which is less prone to produce wandering spurs than a frequency synthesizer that uses a conventional dithered digital delta-sigma modulator. Through the mitigation of wandering spurs, it enables the frequency synthesizer to generate cleaner carriers for a range of applications including communications, radar and instrumentation.

(45) In the specification the terms “comprise, comprises, comprised and comprising” or any variation thereof and the terms include, includes, included and including” or any variation thereof are considered to be totally interchangeable and they should all be afforded the widest possible interpretation and vice versa.

(46) The present disclosure is not limited to the embodiments hereinbefore described but may be varied in both construction and detail.