Integrated High Voltage Capacitor

Abstract

A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

Claims

1. A semiconductor device, comprising: a semiconductor die; a build-up interconnect structure including an integrated capacitor formed over the semiconductor die, wherein the integrated capacitor includes a plurality of interdigitated fingers; and a high voltage input coupled to the integrated capacitor.

2. The semiconductor device of claim 1, further including a transimpedance amplifier formed in the semiconductor die.

3. The semiconductor device of claim 2, further including an avalanche photodiode disposed adjacent to the semiconductor die and electrically connected to the integrated capacitor.

4. The semiconductor device of claim 3, further including a conductive epoxy disposed between the avalanche photodiode and semiconductor die.

5. The semiconductor device of claim 1, wherein the plurality of interdigitated fingers are interdigitated vertically and horizontally.

6. The semiconductor device of claim 1, further including a guard ring formed around the integrated capacitor.

7. The semiconductor device of claim 1, further including an integrated resistor formed over the semiconductor die, wherein the integrated capacitor is coupled to the high voltage input through the integrated resistor.

8. A semiconductor device, comprising: a semiconductor die; and an integrated capacitor formed over the semiconductor die, wherein the integrated capacitor is configured to receive a high voltage signal.

9. The semiconductor device of claim 8, wherein the integrated capacitor includes a first conductive layer comprising a first plurality of interdigitated fingers.

10. The semiconductor device of claim 9, wherein the integrated capacitor includes a second conductive layer comprising a second plurality of interdigitated fingers formed over the first conductive layer.

11. The semiconductor device of claim 10, further including a conductive via formed between a first finger of the first plurality of interdigitated fingers and a second finger of the second plurality of interdigitated fingers.

12. The semiconductor device of claim 8, further including an integrated resistor formed over the semiconductor die, wherein the capacitor is configured to receive the high voltage signal through the integrated resistor.

13. The semiconductor device of claim 8, further including: a transimpedance amplifier formed in the semiconductor die; and a photodiode disposed adjacent to the semiconductor die.

14. The semiconductor device of claim 13, further including a conductive epoxy or solder disposed between the semiconductor die and photodiode.

15. A method of making a semiconductor device, comprising: providing a semiconductor die; forming an integrated capacitor over the semiconductor die; and coupling the integrated capacitor to a high voltage input of the semiconductor device.

16. The method of claim 15, further including forming the integrated capacitor by: forming a first conductive layer over the semiconductor die; and patterning the first conductive layer to include, a first bus bar, a second bus bar oriented parallel to the first bus bar, a first plurality of fingers extending from the first bus bar toward the second bus bar, and a second plurality of fingers extending from the second bus bar toward the first bus bar.

17. The method of claim 16, further including patterning the first conductive layer to include a guard ring around the first bus bar, second bus bar, first plurality of fingers, and second plurality of fingers.

18. The method of claim 16, further including: forming a second conductive layer over the first conductive layer; and patterning the second conductive layer to include a third plurality of fingers.

19. The method of claim 15, further including: providing a contact pad coupled to the integrated capacitor; forming an insulating layer over the contact pad; forming an opening in the insulating layer over the contact pad; and disposing a photodiode over the opening with a conductive material between the contact pad and photodiode.

20. The method of claim 19, further including forming a bond wire from the photodiode to the semiconductor die.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 illustrates a receiver optical sub-assembly in a can package;

[0015] FIG. 2 illustrates a photodetector circuit diagram with an avalanche photodiode, transimpedance amplifier, and 5 GHz RC filter;

[0016] FIG. 3 illustrates an implementation of the photodetector circuit in a can package where the filter is formed with a discrete component;

[0017] FIGS. 4a-4c illustrate a metal-insulator-metal capacitor formed in conductive layers over the transimpedance amplifier semiconductor die;

[0018] FIGS. 5a-5f illustrate metal-oxide-metal capacitor options;

[0019] FIGS. 6a and 6b illustrate the transimpedance amplifier with integrated high voltage capacitor in a stacked configuration with an avalanche photodiode;

[0020] FIG. 7 illustrates the transimpedance amplifier with integrated high voltage capacitor in a side-by-side configuration with the avalanche photodiode; and

[0021] FIGS. 8a-8c illustrate a stacked configuration with the APD connected to the high voltage input through a contact pad on the bottom of the APD.

DETAILED DESCRIPTION OF THE DRAWINGS

[0022] The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, those skilled in the art will appreciate that the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and the claims' equivalents as supported by the following disclosure and drawings.

[0023] FIG. 4a illustrates a cross-sectional view of TIA package 50 from FIG. 3. TIA package 50 includes a semiconductor die 60 having TIA 30 formed in active surface 61. A plurality of contact pads 62 are formed on active surface 61 to provide ohmic contact to TIA 30. A plurality of oxide or insulating layers 66 and conductive layers or redistribution layers (RDL) 68 are vertically interleaved over semiconductor die 60 to route electrical signals as necessary, in what may be referred to as a build-up interconnect structure. The top conductive layer 68, conductive layer 68b in FIG. 4a, includes a plurality of contact pads 71 for connection of bond wires 16.

[0024] While only two conductive layers 68a and 68b are illustrated, any suitable number of routing layers can be formed over semiconductor die 60, with the top conductive layer 68 including contact pads 71 for connection by bond wires 16, solder bumps, stud bumps, or another interconnect structure. The top insulating layer, insulating layer 66c in FIG. 4a, is formed over the contact pads of conductive layer 68b as a solder resist or passivation layer. In some embodiments, insulating layer 66c comprises a plurality of passivation layers formed over conductive layer 68b. Openings are formed in insulating layer 66c for electrical interconnect of bond wires 16 to contact pads 71.

[0025] FIG. 4b illustrates TIA package 69 with high voltage capacitor 40 implemented as a metal-insulation-metal (MIM) high voltage capacitor 40a. MIM capacitor 40a is formed as part of conductive layers 68 over APD die 60. Any desired number of conductive layers are formed over semiconductor die 60 to route the electrical signals. As part of the top conductive layer, conductive layer 68b in FIG. 4b, a bottom capacitor plate 70 is formed. Bottom capacitor plate 70 is a plane of conductive material deposited as part of conductive layer 68b that has a suitable shape for a capacitor plate. Bottom capacitor plate 70 is coupled to a ground voltage node through conductive layers 68 and bond wires 16.

[0026] Insulating layer 66c is formed over conductive layer 68b as in FIG. 4a. Openings are formed in insulating layer 66c over contact pads 71 for the connection of bond wires 16. However, insulating layer 66c is left to fully cover bottom capacitor plate 70. A top capacitor plate 72 is formed on insulating layer 66c over bottom capacitor plate 70. Top capacitor plate 72 can be formed by the same process and of the same material as conductive layers 68, or other suitable materials and processes can be used. A bond wire 16 is bonded onto top plate 72 to couple capacitor 40a to high voltage source 26 via an optional resistor 42. In one embodiment, a bond wire 16 is formed on bottom plate 70 in an opening of insulating layer 66c outside a footprint of top plate 72. In some embodiments, insulating layer 66c is the first of a plurality of passivation layers formed over conductive layer 68b, and additional passivation layers are formed over top plate 72.

[0027] Capacitor plates 70 and 72 form capacitor 40a as a MIM capacitor integrated over TIA die 60. Plate 70 is coupled to ground, while plate 72 is coupled to a high voltage source. In one embodiment, conductive layers 68, including bottom plate 70, are formed from copper, and top plate 72 is formed from aluminum. In another embodiment, the top conductive layer 68, including bottom plate 70, is also formed from aluminum while all underlying conductive layers 68 are copper. In addition to operating as the plate of a capacitor, bottom plate 70 is connected to ground and helps shield the areas of semiconductor die 60 under plate 70 from EMI. Bottom plate 70 coupled to ground also reduces interference caused by the high voltage on top plate 72 being in close proximity to semiconductor die 60.

[0028] Insulating layer 66c, which can be the top insulating layer of the build-up interconnect structure stack or a first of one or more passivation layers, operates as the capacitor's dielectric, and can be any suitable oxide or nitride. In designing MIM capacitor 40a, calculations are made to determine that insulating layer 66c between plates 70 and 72 will have a breakdown voltage sufficient for the maximum expected voltage potential of high voltage source 26.

[0029] FIG. 4c illustrates an alternative method of forming high voltage capacitor 40 as MIM capacitor 40b in TIA package 79. A bottom capacitor plate 70 is formed as part of conductive layer 68b in much the same manner as above. A dielectric layer 80 is formed on bottom capacitor plate 70 from any suitable capacitor dielectric material, e.g., an oxide or nitride material. Dielectric layer 80 is confined to the area of bottom capacitor plate 70, rather than being formed over the entire device as illustrated with insulating layer 66c in FIG. 4b. Having dielectric layer 80 formed specifically as a capacitor dielectric allows better customization of the material and thickness of the dielectric layer. Dielectric layer 80 can be formed from materials and at thicknesses that may not be suitable for passivation layer 66c.

[0030] A top capacitor plate 82 is formed over bottom plate 70 and dielectric layer 80. Top capacitor plate 82 is similar to top plate 72 in FIG. 4b. Insulating layer 66c is formed over conductive layer 68b, dielectric layer 80, and top capacitor plate 82 as a protective covering. Insulating layer 66c covers the edges of top plate 82, which helps protect the MIM capacitor from physical damage and reduces the likelihood that the MIM capacitor layers will peel. Openings are formed in insulating layer 66c over top capacitor plate 82 and contact pads 71 for connection by bond wires 16.

[0031] FIGS. 5a-5f illustrate various embodiments of high voltage capacitor 40 formed as a metal-oxide-metal (MOM) capacitor. FIG. 5a shows MOM capacitor 40c formed within conductive layers 68 over TIA die 60 as with the MIM capacitor embodiments in FIGS. 4b and 4c. However, rather than being formed as two vertically aligned plates, MOM capacitor 40c is formed from a plurality of interdigitated fingers. FIG. 5a illustrates a top-down or plan view of a single conductive layer 68 formed into a portion of MOM capacitor 40c. A pair of bus bars 90a and 90b is formed in parallel. Bus bar 90a has a plurality of fingers 92a extending toward bus bar 90b. Bus bar 90b has a plurality of fingers 92b extending toward bus bar 90a. Each finger 92a is formed between a pair of fingers 92b, and vice versa, without physically contacting each other, to increase capacitance between the two sides.

[0032] Bus bar 90a and fingers 92a form one plate of the high voltage MOM capacitor 40c, while bus bar 90b and fingers 92b form the second plate. One bus bar 90a or 90b is coupled to ground, while the second bus bar is coupled to the high voltage input. Insulating layers 66 are formed under, over, and between bus bars 90 and fingers 92 as the capacitor's dielectric. Openings can be formed in insulating layer 66 over bus bars 90a and 90b for connection of subsequent conductive layers 68 or for bond wires 16 from capacitor 40c to ground and the high voltage source. The bus bar 90 coupled to ground can also be coupled to TIA die 60 through conductive layers 68.

[0033] FIG. 5b illustrates a perspective view of multiple conductive layers 68 stacked to increase the capacitance of MOM capacitor 40c. Each individual conductive layer 68 includes fingers 92a and 92b interdigitated as illustrated in FIG. 5a. Each successive conductive layer 68a through 68c includes fingers 92a aligned over the underlying conductive layer's fingers 92b, and fingers 92b over the underlying conductive layer's fingers 92a. Each conductive layer 68 includes a bus bar 90a connected to fingers 92a, and a bus bar 90b connected to fingers 92b. The bus bars 90 of subsequent conductive layers are coupled to each other vertically by conductive vias 94 or other interconnect structures formed through insulating layers 66.

[0034] In FIG. 5b, only three conductive layers 68 are illustrated, and each conductive layer only includes three fingers 92. In practice, any desired number of conductive layers 68 can be stacked with vertically alternating fingers 92a and 92b, and with any desired number of fingers per conductive layer to achieve a desired capacitance value. All of the fingers 92a of each conductive layer 68 are electrically coupled to each other as one side of MOM capacitor 40c, and all of the fingers 92b of each conductive layer 68 are electrically coupled to each other as the other side of the MOM capacitor 40c.

[0035] The fingers 92 are interdigitated vertically and horizontally so that each high voltage finger 92 is directly adjacent to as many as four fingers at ground potential, and vice versa. In one embodiment, MOM capacitor 40c is built up over nine conductive layers using 0.1 micrometer (?m) finger spacing. In other embodiments, a MOM capacitor is formed by stacking fingers over each other perpendicularly instead of parallel as illustrated in FIG. 5b. MOM capacitor 40c is normally formed beginning from the first metal layer over semiconductor die 60. In other embodiments, a ground plane is formed in the first conductive layer 68a between MOM capacitor 40c and the underlying portion of semiconductor die 60, and MOM capacitor 40c is manufactured starting with the second conductive layer 68b. Lower conductive layers are normally preferred because the fabrication process includes smaller conductive traces at lower conductive layers, which satisfies the desired sizing of a MOM capacitor. However, a MOM capacitor can be formed in any combination of conductive layers.

[0036] In FIG. 5b, fingers 92a are vertically stacked directly over or under fingers 92b, so that each finger 92 is above or below a finger of opposite polarity. The vertical interleaving of fingers 92 increases the capacitance per volume of the MOM capacitor but creates some problems for higher voltage potentials. MOM capacitor 40c is suitable for up to around 35-40 volts, but leakage between the vertically interleaved stacked fingers 92 above 35 volts reduces the performance of capacitor 40c.

[0037] FIG. 5c illustrates MOM capacitor 40d, without vertical interleaving. In MOM capacitor 40d, each finger 92 is stacked vertically over fingers of the same polarity, i.e., all fingers 92a are vertically aligned over or under other fingers 92a, and fingers 92b are vertically aligned with other fingers 92b. MOM capacitor 40d without vertical interleaving of fingers 92 is suitable for higher voltages, up to 60-90 volts, which is typically the upper limits of ROSA high voltage inputs.

[0038] Fingers 92 are typically made 0.1 ?m wide. For 60 volts, the typical horizontal spacing between fingers 92 is 0.3 ?m but may be decreased for lower voltages and increased for higher voltages. The vertical space between adjacent conductive layers 68 is typically 0.17 ?m. The target capacitance for capacitor 40 is conventionally 200 picofarads (pF). However, 180 pF is considered to be a safe design choice, and values as low as 100 pF provide adequate protection. A manufacturer can standardize on one finger spacing, e.g., 0.3 ?m, so that qualification can be done just once for a given process technology. Thereafter, a specific chip is designed with an increased or reduced footprint or height of capacitor 40 to customize the capacitor for a given input voltage or desired capacitance value.

[0039] Conductive vias 94 connect each layer of MOM capacitors 40c and 40d to each other via the layers' respective bus bars 90. With fingers 92 of the same polarity being vertically aligned as in FIG. 5c, additional conductive vias can be formed directly connecting fingers 92 to each other. FIG. 5d illustrates MOM capacitor 40e with conductive vias 96 formed between vertically aligned fingers 92. Conductive vias 96 generate additional capacitance for capacitor 40e by building a conductive wall in the vertical plane, effectively adding extra vertically oriented fingers 92 to the MOM stack.

[0040] FIG. 5e illustrates an optional guard ring 97 formed around MOM capacitor 40c. A separate guard ring 97 is formed as part of each conductive layer 68 around the plates of capacitor 40c in that respective conductive layer to reduce the effects induced by the high voltage into surrounding circuitry. Conductive vias 94 can be formed to connect each guard ring 97 of each conductive layer 86. Typically, a gap of about 10 ?m is provided between MOM capacitor 40c and other surrounding circuitry, and conductive ring 97 is formed in the gap. In other embodiments, the 10 ?m gap can be larger or smaller depending on design constraints and desires. Guard rings 97 can be formed as part of conductive layers 68 around any of the above or below described MOM or MIM capacitor embodiments.

[0041] Besides having a square-shaped footprint as illustrated above, MOM capacitors can be formed in any arbitrary footprint. FIG. 5f illustrates MOM capacitor 40f with an exemplary footprint. The shape is accommodated by using multiple bus bars 90 in parallel. Each bus bar 90 can have a different length depending on the length of the footprint of MOM capacitor 40f at the particular location. Bus bars alternate vertically between bus bars 90a and 90b. The number of bus bars 90 is customized to the desired width of capacitor 40f. Each bus bar 90a includes fingers 92a extending toward each adjacent bus bar 90b. For internally located bus bars 90a, fingers 92a extend in two different directions perpendicular to the length of the bus bar because there are two adjacent bus bars 92b. Similarly, bus bars 90b can have fingers 92b extending in two different directions from the bus bar. For bus bars 90 on the edge of the MOM capacitor 40f footprint, fingers 92 only extend in toward the middle of the capacitor.

[0042] FIGS. 6a and 6b illustrate a ROSA device including an APD 20 stacked on a TIA package 100. FIG. 6a illustrates a perspective view, and FIG. 6b illustrates a top-down view. Five legs of the can package extend through the bottom of the can as ground node 28, high voltage input 26, low voltage input 36, and output signal 38. In the illustrated embodiment, output 38 is a balanced output with two signals 38a and 38b.

[0043] TIA package 100 includes a high voltage capacitor 40, formed as a MOM capacitor, MIM capacitor, or another integrated passive device (IPD) technology. The high voltage input 26 is coupled to TIA package 100 by a bond wire 16, either directly or through a discrete resistor 42. Conductive layers of TIA package 100 route the high voltage source to one side of the integrated high voltage capacitor 40, and another bond wire 16 connects the high voltage signal to APD die 20. High voltage capacitor 40 has a second side coupled to ground to filter 5 GHz interference via another bond wire 16 and conductive layers 68.

[0044] In some embodiments, resistor 42 is formed as an IPD on TIA package 100 along with capacitor 40. Resistor 42 may be formed from polysilicon deposited over the semiconductor die or within the build-up interconnect structure comprised of insulating layers 66 and conductive layers 68. The poly resistor 42 connects the high voltage pad of TIA package 100 to the high voltage plate of capacitor 40. Precautions may need to be taken to ensure that resistor 42 is capable of withstanding electro-static discharge (ESD) events. Guard rings and ground planes can be formed around or under resistor 42 to reduce the impact of ESD events on the semiconductor die. Sufficient spacing between high voltage components, e.g., resistor 42 and capacitor 40, and the lower voltage circuit components improves the ability to limit damage during an ESD event. In one embodiment, resistor 42 is a 500 Ohm resistor. In other embodiments, resistor 42 has a value anywhere from 0 to 5,000 Ohms. Larger resistors can be used if suitable for a given situation.

[0045] APD die 20 is stacked on TIA package 100 in FIGS. 6a and 6b, which reduces the overall system footprint. Total interconnect length, and therefore inductance, is reduced by eliminating superfluous components that would otherwise have to be connected by bond wires 16. Interconnect length is further reduced by orienting contact pads of APD 20 near contact pads of TIA 100 to reduce the length of bond wires 16. FIG. 6b illustrates an optional passive component 52 used to filter the low voltage power signal 36. The high voltage passive components in package 44 are still eliminated due to integration on TIA package 100. In some embodiments, the low voltage passive components 52 are integrated on TIA package 100 as well.

[0046] FIG. 7 illustrates a configuration with APD die 20 disposed on the bottom of can 10 adjacent to TIA package 100. Again, a high voltage capacitor is integrated onto TIA package 100 to reduce the number of components required, and the overall size of components. APD die 20 is disposed with contact pads oriented toward TIA package 100 to reduce interconnect length.

[0047] FIGS. 8a-8c illustrate an embodiment with the high voltage node coupled from TIA 100 to APD 20 through a contact pad on the bottom of the APD. In FIG. 8a, a pair of openings is formed through the top insulating layer 66 to expose a contact pad 110 of the top conductive layer 68. The top insulating layer 66 forms an oxide bridge between the two exposed portions of contact pad 110. The openings over contact pad 110 are preferably rectangular shaped and form a square in combination. However, any other suitable shape is used in other embodiments. Having the opening over contact pad 110 split into two sections reduces physical stress on the semiconductor die of APD 20, relative to one large hole, which could reduce performance. Two smaller holes, rather than one large hole, also provides improved support to the APD due to the viscosity of conductive epoxy which is typically used.

[0048] Contact pad 110 is coupled directly to the high voltage side of capacitor 40 formed on TIA 100, and coupled to high voltage input 26 through resistor 42. Contact pad 110 allows an APD to be directly connected to the high voltage input using surface-mount or flip-chip technology rather than a bond wire. Contact pad 110 can be a direct extension from a bus bar 90 or upper plate 72, or capacitor 40 can be located remotely from capacitor 40 and connected by a conductive trace of a conductive layer 68.

[0049] FIG. 8b illustrates APD 20 disposed on TIA package 100 over high voltage contact pad 110. The cathode of APD 20 is connected to the high voltage input through a contact pad on the bottom of the APD, and the anode of APD 20 is connected by a bond wire 16 to an input pad of TIA 100. A plurality of bond wires in parallel is used to connect the anode of APD 20 to TIA 100 in other embodiments. FIG. 8c shows a cross-section of TIA 100 with bus bars 90a and 90b and fingers 92a. Fingers 92b are interleaved horizontally with fingers 92a and appear in other cross-sections. The top bus bar 90b includes pad 110 extending from the bus bar.

[0050] In one embodiment, pad 110 is formed directly above capacitor 40 in an overlying conductive layer 68, rather than, off to the side in the same conductive layer. A grounded RF shield can be formed in one of the conductive layers 68 between capacitor 40 and APD 20 to reduce interference. Conductive epoxy 112, solder paste, solder bump, or other suitable interconnect structure is used to electrically couple contact pad 114 of the APD to contact pad 110. An optional adhesive 116 is used between APD 20 and TIA 100 for physical support. In some embodiments, the body of APD 20 is either at the voltage potential of the cathode, or left floating to reduce leakage through the body of the APD.

[0051] Integrating high voltage capacitor 40 on TIA package 100 reduces cost by eliminating a part from the ROSA package bill-of-materials, simplifies manufacturing by requiring fewer parts and fewer bond wires, improves immunity from Wi-Fi interference relative to using a discrete capacitor due to the removed bond wire, and improves optics by allowing more flexibility in placement of APD 20. Integrating a high voltage capacitor 40 works with any TIA device and any APD/TIA circuit topology.

[0052] While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.