In pixel time amplifier for LIDAR applications

Abstract

Techniques, systems, architectures, and methods for amplifying the time difference between events detected on a focal plane array, allowing greater resolution than that afforded by a reference clock are herein disclosed.

Claims

1. An imaging system, the imaging system comprising: a sensor array comprising at least one sensor; and a time amplifier configured to amplify a time difference between events energizing the at least one sensor; wherein the time amplifier comprises a comparator comprising an input, a reference voltage, and an output configured to fire upon a voltage at the input reaching the reference voltage, and a switching module disposed between said input of said comparator and a first current source configured to charge the comparator and a second current source configured to discharge the comparator, wherein the switching module is configured to alternately charge the comparator input using the first current source and to discharge the comparator input using the second current source, dependent on an input signal and reference clock inputs; wherein the input signal corresponds to activity on the at least one sensor in operative communication with said switching module; and further comprising: a reference clock in operative communication with said switching module; a counter comprising a counter input and a counter output, the counter input being in operative communication with said reference clock and configured to increment upon cycling of the reference clock; a first latch in operative communication with the counter output and with the input signal, said first latch being configured to latch a counter value associated with the receipt of a predetermined input signal by the first latch; and a second latch in operative communication with the counter output and with said output of said comparator, said second latch being configured to latch the a counter value associated with the firing of the output of the comparator.

2. The imaging system of claim 1, wherein the switching module is configured to connect the second current source to the input of the comparator and disconnect the first current source from the input of the comparator upon the receipt of the predetermined input signal, thereby discharging the comparator.

3. The imaging system of claim 1, wherein the switching module, after connecting the second current source to the input of the comparator and disconnecting the first current source from the input of the comparator upon the receipt of the predetermined input signal, is further configured to connect the first current source to the input of the comparator and disconnect the second current source from the input of the comparator upon receiving a signal from the reference clock indicating the start of a new period.

4. The imaging system of claim 1, wherein the ratio of the first current source and the second source second current is programmable.

5. The imaging system of claim 1, wherein the current flow of the first current source and the second current source is programmable.

6. The imaging system of claim 1, wherein the current flow of the first current source and the second current source is adjustable.

7. The imaging system of claim 1, wherein the current flow of the first current source and the second current source is adjustable during use.

8. The imaging system of claim 1, wherein the array is a focal plane array.

9. The imaging system of claim 1, wherein the at least one sensor is a photodetector.

10. The imaging system of claim 1, wherein the at least one sensor is a pixel.

11. The imaging system of claim 1, wherein the at least one sensor is a Time-of-Flight detector.

12. The imaging system of claim 1, wherein the sensor array is a focal plane array.

13. The imaging system of claim 1, wherein the sensor array is configured to record a time at which or over which a sensor is triggered.

14. An imaging system, the imaging system comprising: a sensor array comprising at least one sensor; a time amplifier configured to amplify a time difference between events energizing the at least one sensor; an input signal corresponding to activity on the at least one sensor in operative communication with said switching module; a reference clock in operative communication with said switching module; a counter comprising a counter input and a counter output, the counter input being in operative communication with said reference clock and configured to increment upon cycling of the reference clock; a first latch in operative communication with the counter output and with the input signal, said first latch being configured to latch a counter value associated with the receipt of a predetermined input signal by the first latch; and a second latch in operative communication with the counter output and with an output of a comparator, said second latch being configured to latch a counter value associated with the firing of the output of the comparator, wherein the time amplifier comprises the comparator comprising an input, a reference voltage, and the output configured to fire upon a voltage at the input reaching the reference voltage, and a switching module disposed between said input of said comparator and a first current source configured to charge the comparator and a second current source configured to discharge the comparator, and wherein the switching module is configured to alternately charge the comparator input using the first current source and to discharge the comparator input using the second current source, dependent on the input signal and reference clock inputs.

15. The imaging system of claim 14, wherein the switching module is configured to connect the second current source to the input of the comparator and disconnect the first current source from the input of the comparator upon the receipt of the predetermined input signal, thereby discharging the comparator, and wherein the switching module, after connecting the second current source to the input of the comparator and disconnecting the first current source from the input of the comparator upon the receipt of the predetermined input signal, is further configured to connect the first current source to the input of the comparator and disconnect the second current source from the input of the comparator upon receiving a signal from the reference clock indicating the start of a new period.

16. An imaging system, the imaging system comprising: a sensor array comprising at least one sensor; a time amplifier configured to amplify a time difference between events energizing the at least one sensor; an input signal corresponding to activity on the at least one sensor in operative communication with said switching module; a reference clock in operative communication with said switching module; a counter comprising a counter input and a counter output, the counter input being in operative communication with said reference clock and configured to increment upon cycling of the reference clock; a first latch in operative communication with the counter output and with the input signal, said first latch being configured to latch a counter value associated with the receipt of a predetermined input signal by the first latch; and a second latch in operative communication with the counter output and with an output of a comparator, said second latch being configured to latch a counter value associated with the firing of the output of the comparator, wherein the time amplifier comprises the comparator comprising an input, a reference voltage, and the output configured to fire upon a voltage at the input reaching the reference voltage, and a switching module disposed between said input of said comparator and a first current source configured to charge the comparator and a second current source configured to discharge the comparator, wherein the switching module is configured to alternately charge the comparator input using the first current source and to discharge the comparator input using the second current source, dependent on the input signal and reference clock inputs, wherein the switching module is configured to connect the second current source to the input of the comparator and disconnect the first current source from the input of the comparator upon the receipt of the predetermined input signal, thereby discharging the comparator, and wherein the switching module, after connecting the second current source to the input of the comparator and disconnecting the first current source from the input of the comparator upon the receipt of the predetermined input signal, is further configured to connect the first current source to the input of the comparator and disconnect the second current source from the input of the comparator upon receiving a signal from the reference clock indicating the start of a new period.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic showing a prior art in-pixel time-to-digital converter;

(2) FIG. 2 is a graph describing the behavior of the prior art, in-pixel time-to-digital converter of FIG. 1;

(3) FIG. 3 is a schematic showing a time amplifier circuit, in accordance with embodiments of the present disclosure;

(4) FIG. 4 is time amplifier schematic showing a more detailed view of the time amplifier of FIG. 3, in accordance with embodiments of the present disclosure;

(5) FIG. 5 is a graph describing the behavior of a pixel comprising the time amplifier circuit of FIGS. 3 and 4, in accordance with embodiments of the present disclosure; and

(6) FIG. 6 is graph describing the behavior of the time amplifier circuit of FIGS. 3 and 4, in accordance with embodiments of the present disclosure.

(7) These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. The accompanying drawings are not intended to be drawn to scale. For purposes of clarity, not every component may be labeled in every drawing.

DETAILED DESCRIPTION

(8) With new image sensor technology enabling sensitivity down to single photons and providing, practically speaking, unlimited gain, detection of time resolution down to a fraction of a nanosecond is now possible. Event detection at such a fine resolution requires a very fast clock, or multiple fast clocks.

(9) A Time Amplifier (TA) 300 used on a focal plane array, in accordance with embodiments of the present disclosure, allows event detection at a higher resolution than a reference clock 106 alone, increasing the accuracy of a design or reducing its power requirements (due to the ability to maintain performance while using a slower reference clock 106). The downsides of this technique are that it requires some amount of time following detection of time amplified signals, which is herein referred to as dead time, before a subsequent event can be detected, and that area must be devoted to the TA 300 circuit. For applications where such dead time and additional circuit space can be accommodated, however, embodiments of the present disclosure provide better performance with less complexity and power usage compared to current, high-resolution systems and methods.

(10) A specific, exemplary embodiment is shown in FIG. 3, with a more detailed view of the Time Amplifier (TA) 300 shown therein being provided in FIG. 4. More specifically, FIG. 3 depicts a reference clock in electrical communication with a counter input and in further electrical communication with a first input of a TA; a second input of the TA is in electrical communication with an input signal. An output of the TA is further routed to a first input of a latch having a second input in electrical communication with an output of the counter, the latch being used for resolving a fine count by latching a counter value of the time-amplified difference between the event and reference clocks. Lastly, the system shown in FIG. 3 includes a second latch (hereinafter, a coarse latch), which uses the input signal and counter outputs as inputs.

(11) In embodiments, a TA of a different design, as would be known to one of ordinary skill in the art, is used.

(12) In embodiments, the counter is a 10-bit counter 102.

(13) In embodiments, the latches are 10-bit latches 302.

(14) In embodiments, the TA 300 comprises a comparator 402, current sources configured to charge and discharge the comparator (in embodiments, I.sub.2/I.sub.1, respectively), a switching module 400 configured to control the flow of current from the current sources (I.sub.2/I.sub.1) into the comparator using switches, and a threshold voltage (V.sub.TH) input to the comparator 402, which is also herein referred to as a reference voltage (V.sub.TH). In embodiments, the current sources (V.sub.TH) comprise two current sources (I.sub.2/I.sub.1) controlled by a switching module 400 that controls switches configured to allow the flow of current from one or the other of the two current sources (I.sub.2/I.sub.1) into or out of the comparator 402, resulting in the current sources (I.sub.2/I.sub.1), respectively, alternately charging and discharging the comparator.

(15) More specifically, in embodiments, the switching module 400, in response to the detection of an event (in embodiments, indicated by the switching module 400 receiving a predetermined input signal 104, which may be a signal over a certain voltage or a digital signal in the form of a 0 or 1) is configured to first discharge the comparator 402 by leaving open a switch between I.sub.1 and an input node of the comparator, the switch hereinafter being referred to as the reference clock switch, while closing a switch between I.sub.2 and the input node of the comparator, the switch hereinafter being referred to as the input signal switch, thereby allowing current to flow out of the comparator 402 input, discharging it. In embodiments, a counter value, in embodiments incremented by the reference clock 106, that is associated with the moment the comparator input begins being discharged by I.sub.2 is latched and used to provide a coarse count, which may be considered a rough estimate of the time at which an event occurred. This switch configuration is herein referred to as the baseline or steady state configuration and results in a downward slew rate of voltage on the comparator input, which is dependent on I.sub.2.

(16) At a next reference clock 106 edge, the switching module 400 triggers the reference clock switch to close, allowing current to flow from I.sub.1 into the comparator 402, and, substantially simultaneously, opens the input signal switch, causing the comparator 402 to cease discharging therethrough. This results in an upward slew rate of voltage on the comparator input, which is dependent on I.sub.1. Once the voltage on the comparator input reaches the reference voltage (V.sub.TH), the comparator 402 is configured to fire, in embodiments latching a second counter value that can be considered a fine count. Since the coarse event detection time is known, the amount of comparator 402 discharge is dependent on the size of I.sub.2 and the time to the next reference clock 106 edge from the coarse event detection time, and the time for voltage on the comparator input to reach Vth depends on I.sub.1, with the total gain of such a system described by the ratio of I.sub.2 to I.sub.1 (i.e. I.sub.2/I.sub.1), which is known, the distance of the coarse count value from a reference clock 106 edge can be very accurately extrapolated, allowing the timing of the event to be more accurately discerned than the reference clock 106 rate would otherwise allow.

(17) Moreover, since the rate of charge by I.sub.1 and discharge by I.sub.2 can be adjusted, the gain of such a system may be adjusted over a very wide range, with high gain providing very accurate timestamping, but increasing dead time following the detection of an event and vice-versa. In embodiments, the gain is programmable. In embodiments, the gain is adjustable during use.

(18) The behavior of the embodiment shown in FIGS. 3 and 4 can be characterized using Equation (1), below:

(19) $\mathrm{Complete}\mathrm{calculation}\mathrm{of}\mathrm{when}\mathrm{event}\mathrm{happened}$$\begin{array}{cc}{T}_{\mathrm{event}}=T_{\mathrm{start}}+{\mathrm{count}}_{\mathrm{coarse}}*{\mathrm{period}}_{\mathrm{ref}}+(\left(1-\frac{\left({\mathrm{count}}_{\mathrm{fine}}-{\mathrm{count}}_{\mathrm{coarse}}\right)}{\mathrm{gain}}\right)*{\mathrm{period}}_{\mathrm{ref}}-T_{\mathrm{static}}& \mathrm{Equation}\left(1\right)\end{array}$

(20) This behavior is also graphically depicted in FIGS. 5 and 6. More specifically, Equation (1) provides the time difference between the edge of the reference clock 106 and the edge of the input signal 104. Even more specifically, the coarse count depicted in FIG. 5 would equal “N” and the fine count would equal (N+3)−N=3. FIG. 6 elaborates on the behavior depicted in FIG. 5, with reference to the TA 300 depicted in FIGS. 3 and 4.

(21) More specifically, FIG. 5 shows: 1. When an input signal 104 is received by switching module 400, a latch 302 latches a counter value 102 (quick slew rate, discharge); 2. At a next reference clock 106 edge, switch I.sub.1 closes and switch I.sub.2 opens, leading to an increasing slew rate of voltage on the comparator input; 3. When voltage on the comparator input returns to steady state (i.e. V.sub.th, threshold voltage, an output of the TA 300 fires; and 4. The output of the TA 300 latches a counter 102 value, which can be compared to the counter 102 value obtained in step 1 and used to extrapolate the time at which an event occurred more precisely than a reference clock 106 alone would be able to, as mathematically described below.

(22) The gain of the TA 300 shown in FIG. 4 is defined by the ratio of I.sub.1 and I.sub.2, as shown in Equation (2), below:

(23) $\begin{array}{cc}\mathrm{Gain}=\frac{I_2}{I_1}& \mathrm{Equation}\left(2\right)\end{array}$

(24) The foregoing description of the embodiments of the present disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto.

(25) A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the scope of the disclosure. Although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.