Method and apparatus of processing a digitally encoded radio signal

Abstract

A method of processing a digitally encoded radio signal (102) comprising a bit to be determined is disclosed. The method comprises correlating a first bit sequence (103) comprising the bit with a plurality of predetermined filters (104a-h) to create a first set of filter coefficients (110a-h); calculating (120) a first likelihood data set (124) comprising a likelihood of said bit having a given value for each bit position from the first set of filter coefficients. A second bit sequence (103) comprising the bit at a different position is then correlated with the filters to create a second set of filter coefficients (10a-h), from which a second likelihood data set (124) is calculated. A soft output bit (26) comprising a probability weighted bit value from data corresponding to the bit at a first and second bit positions from the first and second likelihood data sets respectively is then calculated.

Claims

1. A method comprising: receiving a digitally encoded radio signal comprising a bit to be determined; correlating a first bit sequence comprising the bit with a plurality of predetermined filters to create a first set of filter coefficients; calculating a first likelihood data set comprising a likelihood of said bit having a given value for each bit position from the first set of filter coefficients; correlating a second bit sequence comprising the bit with the plurality of predetermined filters to create a second set of filter coefficients; calculating a second likelihood data set comprising a likelihood of said bit having a given value for each bit position from the second set of filter coefficients; and calculating a soft output bit comprising a probability weighted bit value from data corresponding to the bit at a first bit position from the first likelihood data set and the bit at a second bit position from the second likelihood data set, wherein said first and second bit positions are different.

2. The method as claimed in claim 1, further comprising using a decoder to determine a value for the bit using the soft output bit.

3. The method as claimed in claim 1, further comprising: correlating an additional bit sequence comprising the bit with the plurality of predetermined filters to create an additional set of filter coefficients; calculating an additional likelihood data set comprising a likelihood of said bit having a given value for each bit position from the additional set of filter coefficients; and calculating the soft output bit from data corresponding to the bit at the first bit position from the first likelihood data set, the bit at the second bit position from the second likelihood data set, and the bit at an additional bit position from the additional likelihood data set wherein each of said bit positions is different.

4. The method as claimed in claim 1, wherein said bit sequences comprise a plurality of bits.

5. The method as claimed in claim 4, comprising carrying out correlations with each of the predetermined filters for bit sequences corresponding to the bit being at each possible position in the sequences.

6. The method as claimed in claim 1, comprising calculating the soft output bit by summing data corresponding to said first, second and optionally additional, bit positions.

7. The method as claimed in claim 1, comprising calculating the soft output bit by taking a maximum of data corresponding to said first, second and optionally additional, bit positions.

8. The method as claimed in claim 1, wherein the predetermined filters comprise each possible bit sequence.

9. The method as claimed in claim 1, comprising storing the maximum likelihood data sets for later use.

10. A digital radio receiver arranged to receive a digitally encoded radio signal comprising a bit to be determined, said digital radio receiver being arranged to perform a method, comprising: correlating a first bit sequence comprising the bit with a plurality of predetermined filters to create a first set of filter coefficients; calculating a first likelihood data set comprising a likelihood of said bit having a given value for each bit position from the first set of filter coefficients; correlating a second bit sequence comprising the bit with the plurality of predetermined filters to create a second set of filter coefficients; calculating a second likelihood data set comprising a likelihood of said bit having a given value for each bit position from the second set of filter coefficients; and calculating a soft output bit comprising a probability weighted value from data corresponding to the bit at a first bit position from the first likelihood data set and the bit at a second bit position from the second likelihood data set wherein said first and second bit positions are different.

11. The digital radio receiver as claimed in claim 10, further comprising a decoder arranged to determine a value for the bit using the soft output bit.

12. The digital radio receiver as claimed in claim 10, wherein the digital radio receiver is further arranged to: correlate an additional one or more bit sequence(s) comprising the bit with a plurality of predetermined filters to create an additional one or more set(s) of filter coefficients; calculate an additional one or more likelihood data set(s) comprising a likelihood for each bit position from the additional one or more set(s) of filter coefficients; and calculate a soft output bit from data corresponding to the bit at a first bit position from the first likelihood data set, the bit at a second bit position from the second likelihood data set, and the bit at an additional bit position from the additional one or more likelihood data set(s) wherein each of said bit positions is different.

13. The digital radio receiver as claimed in claim 10, wherein said bit sequences comprise a plurality of bits.

14. The digital radio receiver as claimed in claim 13, arranged to carry out correlations with each of the predetermined filters bit sequences corresponding to the bit being at each possible position in the sequences.

15. The digital radio receiver as claimed in claim 10, arranged to calculate the soft output bit by summing data corresponding to said first, second and optionally additional, bit positions.

16. The digital radio receiver as claimed in claim 10, arranged to calculate the soft output bit by taking a maximum of data corresponding to said first, second and optionally additional, bit positions.

17. The digital radio receiver as claimed in claim 10, wherein the predetermined filters comprise each possible bit sequence.

18. The digital radio receiver as claimed in claim 10, arranged to store the maximum likelihood data sets for later use.

Description

(1) Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

(2) FIG. 1 shows schematically part of a prior art digital radio receiver arranged to generate a hard output bit;

(3) FIG. 2 shows schematically part of a digital radio a receiver arranged to generate a soft output bit in accordance with an embodiment of the present invention;

(4) FIG. 3 shows another embodiment of the present invention; and

(5) FIG. 4 shows a further embodiment of the present invention.

(6) FIG. 1 shows schematically part of an exemplary prior art receiver, described for reference purposes only, arranged to generate a hard output bit 14. In this arrangement, in-phase (I) and quadrature (Q) bitstream signals from a previous stage such as an amplifier or a filter (not shown) are stored in a shift register 2. In this arrangement, the shift register 2 has a width of three bits, i.e. it stores a current bit from the received bitstream and the two previous most recent bits from the received bitstream.

(7) The shift register 2 produces a shift register output 3 of the three bits that it currently has stored. The shift register output 3 is passed to a set of eight correlators 4a-h corresponding to the eight different possible values that the three bit shift register output 3 may take. Each of the correlators 4a-h is arranged to convolve the shift register output 3 with a different bit sequence as indicated in order to produce a respective correlator match coefficient 10a-h.

(8) Each of the correlator match coefficients 10-h produced has a numerical value for a given v alue of the shift register output 3, which is updated on every clock cycle when the shift register performs a logic shift operation to provide a new output 3 which includes the next new bit and discards the oldest one.

(9) The correlator match coefficients 10a-h are provided to a decision block 6 which produces an observation output 12 that identifies which of the correlators 4a-h produced the strongest (i.e. the highest value) correlator match coefficient 10a-h. The winning correlator therefore provides, through its associated sequence, an estimate of the three bits observed,

(10) Since the shift register 2 is three bits wide, any given incoming bit from the bitstream is observed three times, once in each position (left, middle, right) in the sequence. There are therefore three observation outputs 12 that have information about a given received bit. A voting block 8 determines from these three observations the value (i.e. digital 0 or 1) that each bit was seen to have at each observation as it traversed through this three bit sliding window (i.e. in the leftmost, central, and rightmost bit positions). The voting block 8 then produces a hard decision output 14 that takes the definite value of either 0 or 1 for each received bit, depending on the digital value that was assigned to the bit most often (i.e. twice or all three times).

(11) By contrast FIG. 2 shows part of a digital receiver arranged to generate a soft output bit in accordance with an embodiment of the present invention. In common with the arrangement described with reference to FIG. 1, in-phase and quadrature bitstream signals from a previous stage such as an amplifier or a filter (not shown) are stored in a shift register 102. It will be appreciated of course that the incoming bitstream is not necessarily quadrature modulated and thus the invention is by no means limited to working with I and Q signals.

(12) The shift register 102 has a width of three bits as before, however it will be appreciated that the principles of the invention described herein apply to shift registers of any width greater than or equal to two. In order to accommodate wider shift registers (and thus more samples of the incoming bitstream), more correlators would of course be needed, i.e. for an n-bit wide shift register, 2.sup.n correlators will be needed if all possible bit combinations are to be covered.

(13) As previously described, a set of eight correlators 104a-h produce correlator match coefficients 110a-h that correspond to how well the shift register output 103 at each clock cycle matches the bit sequence assigned to the correlator. However, rather than being subsequently processed by a decision block which simply provides the best match, the correlator match coefficients 110a-h are passed to an evaluation block 120 described below.

(14) The evaluation block 120 is arranged to produce a likelihood metric 124 as an output based on the correlator match coefficients 110a-h. In the present case of a three bit sliding window (i.e. the shift register is three bits wide meaning there are eight correlators), the likelihood metric 124 corresponding to the k.sup.th received bit comprises a 31 matrix as per Equation 1 below:

(15) $\mathrm{Equation}1\text{:}\mathrm{Likelihood}\mathrm{metric}124\left[\begin{array}{c}{S}_{0,k}\\ S_{1,k}\\ S_{2,k}\end{array}\right]=\left[\begin{array}{c}{m}_{1,0}-m_{0,0}\\ m_{1,1}-m_{0,1}\\ m_{1,2}-m_{0,2}\end{array}\right]$

(16) wherein: m.sub.1,0=MAX(110c, 110d, 110e, 110f) m.sub.0,0=MAX(110a, 110b, 110g, 110h) m.sub.1,1=MAX(110e, 110f, 110g, 110h) m.sub.1,3=MAX(110a, 110b, 100c, 110d) m.sub.1,2=MAX(110b, 110d, 110f, 110h) m.sub.0,2=MAX(110a, 110c, 110e, 110g)

(17) Taking the first entry in the matrix, m.sub.1,0 is the maximum correlator match score of those correlators that assign a value of 1 to the bit in the zeroth (i.e. leftmost) position in the sequence. These are: the correlator 104c corresponding to the sequence [1 0 0] having the match coefficient 110c; the correlator 104d corresponding to the sequence [1 0 1] having the match coefficient 110d; the correlator 104e corresponding to the sequence [1 1 0] having the match coefficient 110e; and the correlator 104f corresponding to the sequence [1 1 1] having the match coefficient 110f.

(18) Similarly m.sub.0,0 is the maximum correlator match score of the other correlators, which assign a value of 0 to the bit in the same (zeroth or leftmost) position in the sequence. These are: the correlator 104a corresponding to the sequence [0 0 0] having the match coefficient 110a; the correlator 104b corresponding to the sequence [0 0 1] having the match coefficient 210b; the correlator 104g corresponding to the sequence [0 1 0] having the match coefficient 110g; and the correlator 104h corresponding to the sequence [0 1 1] having the match coefficient 110h.

(19) The first entry in the matrix is the difference between these two maximum correlator match scores. The second entry in the matrix is derived from carrying out the same analysis for the next (middle) position in the sequence and the third entry in the matrix is derived from carrying out the same analysis for the final (rightmost) position in the sequence

(20) Thus it will be seen from Equation 1 above that the likelihood metric 124 is calculated from a difference in probabilities between the maximum correlator match scores 110a-h corresponding to a 1 and a 0 in each bit position within each element of the 31 matrix. These likelihood metric matrices 124 are generated and stored every clock cycle, and thus for every received bit within the bitstream, there are three stored likelihood metric matrices 124 that contain information regarding an observation of that particular bit.

(21) The likelihood metric matrices 124 are fed to a summation block 122. The summation block 122 performs a summation operation on the stored matrices 124 to produce a soft output bit b.sub.k as per Equation 2 below, which is then provided as the output 126. This might be used for example in a Viterbi algorithm (such algorithms being well documented in the art per se) wherein the output 126 may be used as the branch metrics that are used by a Viterbi decoder when deciding what is the most likely bit sequence for a given set of observations.
Equation 2: Summation block 122
b.sub.k=SUM(S.sub.0,k,S.sub.L,k-1,S.sub.2,k-2)

(22) Thus it will be seen from Equation 2 that the output 126 corresponds to a sum of the likelihood values corresponding to the k.sup.th bit after it has been observed three times i.e. it is the sum of the likelihood metrics for when a given bit was in the leftmost, central, and rightmost positions during three subsequent observations. Thus the output 126 is a soft bit, i.e. it has a non-integer value rather than a hard 0 or 1 assigned to it. It should be appreciated that the term sum is not strictly limited to simply adding the likelihood values, and it may in some instances be useful to perform a weighted sum, average or other combination. For instance, the result of the sum may in this case be divided by a scaling constant to obtain a scaled likelihood value. For example, the scaling constant may be chosen to be three in order to provide a mean likelihood value which would be particularly useful in cases where each of the elements within the likelihood metric matrix 124 has a value between 0 and 1 (thus making the sum have a value between 0 and 3)dividing by three thus ensures the soft output bit is within the range of possible bit values. However, there may be other reasons to scale the likelihood valuese.g. in order to meet saturation and quantisation constraints that may be imposed by the system when physically implemented.

(23) FIG. 3 shows another embodiment of the present invention. In common with the previous embodiment described with reference to FIG. 2 above, there is provided a three bit shift register 102, eight correlators 104a-h, and an evaluation block 120 which operate in the same manner as described hereinbefore. However, in this embodiment, the likelihood matrix value 124 is provided as an input to a maximisation block 132. The maximisation block 132 operates to generate the soft output bit b.sub.k as per Equation 3 below.
b.sub.k=MAX(S.sub.0,k,S.sub.L,k-1,S.sub.2,k-2)Equation 3: Maximisation block 132

(24) Thus it will be seen from Equation 3 that the output 136 corresponds to the maximum of the likelihood values corresponding to the k.sup.th bit after it has been observed three times.

(25) FIG. 4 shows a further embodiment of the present invention. In common with the previous embodiments described with reference to FIGS. 2 and 3 respectively, there is provided a three bit shift register 102 and eight correlators 104a-h which operate in the same manner as described hereinbefore.

(26) However the evaluation block 420 of this embodiment is arranged to store two likelihood metric matrices 412a, 412b as per Equations 4 and 5 below:

(27) $\mathrm{Equation}4\text{:}\mathrm{Likelihood}\mathrm{metric}412a\left[\begin{array}{c}{U}_{0,k}\\ U_{1,k}\\ U_{2,k}\end{array}\right]=\left[\begin{array}{c}{m}_{1,0}\\ m_{1,1}\\ m_{1,2}\end{array}\right]\mathrm{Equation}5\text{:}\mathrm{Likelihood}\mathrm{metric}412b\left[\begin{array}{c}{V}_{0,k}\\ V_{1,k}\\ V_{2,k}\end{array}\right]=\left[\begin{array}{c}{m}_{0,0}\\ m_{0,1}\\ m_{0,2}\end{array}\right]$

(28) wherein the values m.sub.i,j are defined in the same manner as described with reference to Equation 1.

(29) The evaluation block 420 of this arrangement retains separate likelihood metric matrices 412a, 412b containing the correlator match score 110a-h of the correlators 104a-h that produce the highest correlator match score for a 1 or 0 in each bit position respectively. Each of these likelihood metric matrices 412a, 412b are then passed through separate maximisation blocks 408a, 408b which produce maximum high and maximum low metrics 418a, 418b as per Equations 6 and 7.
Equation 6: Maximum high metric 418a (b.sub.k,upper) produced by maximisation block 408a
b.sub.k,upper=MAX(U.sub.0,k,U.sub.1,k-1,U.sub.2,k-2)
Equation 7: Maximum low metric 418b (b.sub.k,lower) produced by maximisation block 408b
b.sub.k,lower=MAX(V.sub.0,k,V.sub.1,k-1,V.sub.2,k-2)

(30) The resulting maximum high and low metrics 418a, 418b are then passed to a subtractor 416 that computes the difference between these metrics i.e. the difference between the metrics corresponding to the k.sup.th bit being a 1 and a 0 respectively, so as to generate a soft output bit b.sub.k 414.

(31) Thus it will be seen that an improved method of and apparatus for determining a value of a bit within an input signal and that provides a soft bit output suitable for use with e.g. a Viterbi decoder has been described herein. Although particular embodiments have been described in detail, it will be appreciated by those skilled in the art that many variations and modifications are possible using the principles of the invention set out herein.