Cell layout utilizing boundary cell with mixed poly pitch within integrated circuit

Abstract

A cell layout includes a first cell having a plurality of first poly lines extending along a first direction, a second cell having a plurality of second poly lines extending along the first direction, and a boundary cell contiguous with the first cell. The first poly lines have a first uniform poly pitch and the second poly lines have a second uniform poly pitch. The second uniform poly pitch is smaller than the first uniform poly pitch. The boundary cell includes n stripes of first dummy poly lines and m stripes of second dummy poly lines extending along the first direction. The first dummy poly lines have the first uniform poly pitch and the second dummy poly lines have the second uniform pitch.

Claims

1. A device, comprising: an integrated circuit comprising: a first cell comprising a plurality of first poly lines extending along a first direction, wherein said plurality of first poly lines has a first uniform poly pitch and a first uniform poly line width; a second cell being spaced apart from said first cell, said second cell comprising a plurality of second poly lines extending along said first direction, wherein said plurality of second poly lines has a second uniform poly pitch and a second uniform poly line width, wherein said second uniform poly pitch is smaller than said first uniform poly pitch; and a boundary cell being contiguous with said first cell, said boundary cell comprising n stripes of first dummy poly lines and m stripes of second dummy poly lines extending along said first direction, wherein said n stripes of first dummy poly lines have said first uniform poly pitch and said m stripes of second dummy poly lines have said second uniform poly pitch, wherein n and m are both integers, and wherein n and m are both greater than or equal to 2.

2. The device according to claim 1, wherein said first dummy poly lines and said second dummy poly lines are arranged successively along a second direction that is perpendicular to said first direction.

3. The device according to claim 1, wherein said first cell is a standard cell chosen from a library of common cells.

4. The device according to claim 1, wherein said first cell comprises a logic cell.

5. The device according to claim 1, wherein said second cell is a macro.

6. The device according to claim 1, wherein said macro comprises an analog macro or a memory macro.

7. The device according to claim 1, wherein said boundary cell has cell boundaries including a common cell boundary commonly shared with said first cell.

8. The device according to claim 1, wherein said integrated circuit comprises a portion of an application specific integrated circuit (ASIC) or a system on chip (SoC).

9. The device according to claim 1, wherein said first uniform poly pitch is 100 nm and said second uniform poly pitch is 90 nm.

10. The device according to claim 1, wherein said first uniform poly line width is selected from a group consisting of 20, 22, 24, or 28 nm, and said second uniform poly line width is 24 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

(2) FIG. 1 illustrates an exemplary embodiment of the present invention, wherein a cell layout composed a layout of a cell C1, a layout of a cell C2, and a layout of a boundary cell BC are shown;

(3) FIG. 2 is an enlarged plan view of an exemplary boundary cell according to one embodiment of the invention;

(4) FIG. 3 illustrates another embodiment of the present invention, wherein a cell layout composed an L-shaped cell C and a layout of a boundary cell BC are shown; and

(5) FIG. 4 is a schematic layout diagram showing an exemplary boundary cell placement according to another embodiment of the invention.

DETAILED DESCRIPTION

(6) Embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The features may not be drawn to scale, and some details may be exaggerated relative to other elements for clarity. Like numbers refer to like elements throughout.

(7) The description proposed herein is just a preferable example for the purpose of illustration only, not intended to limit the scope of the disclosure, so it would be understood that other equivalents and modifications could be made thereto without departing from the spirit and scope of the disclosure.

(8) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(9) Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be enlarged relative to other layers and regions for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device or layout and are not intended to limit the scope of the invention.

(10) Throughout the description, the terms standard cell and macro refer to the pre-designed cells that have been laid out. Also, the terms standard cell and macro are used interchangeably, while the term standard cell is generally used to refer to small cells, and the term macro is generally used to refer to large cells with more functions. The standard cells and macros are stored in circuit libraries, which may be in the form of a database.

(11) In advanced semiconductor processing, the use of restricted design rules (RDRs) to improve the yield of the manufactured devices is known. One RDR used at the 32 nm node and beyond is that polysilicon pattern, the lowest conductor layer in the IC fabrication, is restricted to be placed in a unitary direction. That is, all of the polysilicon conductors are required to be parallel to one another and running in only the vertical, or only the horizontal, direction. Also, the polysilicon layer is further restricted to be of a uniform width and poly pitch. These restrictions insure more uniform results over process variations, that is, the devices manufactured with these restricted layout rules will have less process sensitivity. However, in some applications, it is desirable to design integrated circuits with mixed poly pitch without violation in the design rule check. The present invention addresses this issue.

(12) FIG. 1 illustrates an exemplary embodiment of the present invention, wherein a cell layout 1 composed a layout of a cell C.sub.1, a layout of a cell C.sub.2, and a layout of a boundary cell BC are shown. The cell layout 1 may be a portion of an application specific integrated circuit (ASIC) or a system on chip (SoC), but not limited thereto. It is understood that the figure illustrates in a very simplified plan view of three neighboring cells. For the sake of simplicity, only poly lines are shown in each cell. It is understood that other elements, such as ion wells, diffusion regions, power rails, or metal layers, may be arranged in each cell depending upon design requirements.

(13) As shown in FIG. 1, the cell C.sub.1, which may be a standard cell that maybe chosen from a library of common cells, has cell boundaries 101 that define the bounds and dimension of the cell C.sub.1. For example, the cell C1 may be a logic cell including, but not limited to, a PMOS transistor and an NMOS transistor. According to the embodiment of the invention, a plurality of polysilicon lines (hereinafter poly lines) 10 is disposed within the cell C.sub.1. For the sake of simplicity, only four of the poly lines 10 are illustrated. According to the embodiment of the invention, the poly lines 10 are arranged in parallel with one another. According to the embodiment of the invention, the poly lines 10 are the lowest conductor layer in the IC fabrication, which is restricted to be all extended in a unitary direction at the 32 nm node and beyond. In FIG. 1, the poly lines 10 extend along a first direction such as a reference y-axis direction (uni-directional).

(14) According to the embodiment of the invention, the poly lines 10 in the cell C.sub.1 have a uniform poly pitch P.sub.1 and uniform ploy line width L.sub.1. The poly pitch P.sub.1 is the combination of the poly line width L.sub.1 and the spacing S.sub.1 between two neighboring poly lines 10. According to the embodiment of the invention, the poly line width L.sub.1 may be 20, 22, 24, or 28 nm, but not limited thereto. According to the embodiment of the invention, the poly pitch P.sub.1 may be 100 nm, but not limited thereto.

(15) According to the embodiment of the invention, the cell C.sub.2, which is spaced apart from the cell C.sub.1, has cell boundaries 102 that define the bounds and dimension of the cell C.sub.2. For example, the cell C.sub.1 may be a macro including, but not limited to, an analog macro or a memory macro such as Static Random Access Memory (SRAM) macro, a Dynamic Random Access Memory (DRAM) macro, or the like. The SRAM macro or the DRAM macro includes SRAM cells or DRAM cells forming an array, and may include supporting circuits for supporting the operation of the memory array. The supporting circuits may include row decoders, sense amplifier, power gating circuitry, and level shifter circuitry, for example.

(16) According to the embodiment of the invention, a plurality of poly lines 20 is disposed within the cell C.sub.2. For the sake of simplicity, only three of the poly lines 20 are illustrated. According to the embodiment of the invention, the poly lines 20 are arranged in parallel with one another. According to the embodiment of the invention, the poly lines 20 are the lowest conductor layer in the IC fabrication, which is restricted to be all extended in a unitary direction at the 32 nm node and beyond. In FIG. 1, the poly lines 20 extend along the reference y-axis direction (uni-directional) .

(17) According to the embodiment of the invention, the poly lines 20 in the cell C.sub.2 have a uniform poly pitch P.sub.2 and uniform ploy line width L.sub.2. The poly pitch P.sub.2 is the combination of the poly line width L.sub.2 and the spacing S.sub.2 between two neighboring poly lines 20. According to the embodiment of the invention, the poly line width L.sub.2 may be 20, 22, 24, or 28 nm, but not limited thereto. According to the embodiment of the invention, the poly pitch P.sub.2 may be 90 nm, but not limited thereto. According to the embodiment of the invention, the poly pitch P.sub.2 is smaller than the poly pitch P.sub.1.

(18) The use of the uniform pitch and width of the polysilicon portions, and restricting the layout to a uni-direction in the polysilicon layer, has benefits in increasing the tolerance of the finished devices to process variations and critical dimension (CD) tolerance.

(19) According to the embodiment of the invention, the boundary cell BC is contiguous with the cell C.sub.1. The boundary cell BC has cell boundaries 103 that define the bounds and dimension of the boundary cell BC and has a common cell boundary 131 that is commonly shared with the cell C.sub.1. According to the embodiment of the invention, the boundary cell BC comprises n stripes of first dummy poly lines 30 and m stripes of second dummy poly lines 40, wherein n and m are both integers. According to the embodiment of the invention, preferably, n and m are both integers greater than or equal to 2. In the illustrated embodiment, as shown in FIG. 1, three first dummy poly lines 30a, 30b, 30c and two second dummy poly lines 40a and 40b are demonstrated. However, it is understood that other numbers of the first dummy poly lines 30 and second dummy poly lines 40 may be employed, depending upon the design requirements.

(20) According to the embodiment of the invention, the first dummy poly lines 30 and second dummy poly lines 40 extend along the first direction (i.e. reference y-axis direction). According to the embodiment of the invention, the first dummy poly lines 30 may have fixed or flexible poly line width L.sub.3. For example, the poly line width L.sub.3 may be 20, 22, 24, or 28 nm, but not limited thereto. According to the embodiment of the invention, the second dummy poly lines 40 may have fixed poly line width L.sub.4, for example, L.sub.4=20 nm.

(21) According to the embodiment of the invention, the parallel first dummy poly lines 30 and the second dummy poly lines 40 are arranged successively along a second direction (i.e. the reference x-axis direction) that is perpendicular to the first direction. According to the embodiment of the invention, the first dummy poly lines 30 may have the poly pitch P.sub.1 and the second dummy poly lines may have the poly pitch P.sub.2. In FIG. 1, the left-most first dummy poly line 30a is disposed in close proximity to the right-most poly line 10 in the cell C.sub.1 with the poly pitch P.sub.1. The common cell boundary 131 is disposed between the left-most first dummy poly line 30a and the right-most poly line 10. Therefore, the poly lines 10 in the cell C.sub.1 and the first dummy poly lines 30 in the boundary cell BC have the same poly pitch P.sub.1.

(22) According to the embodiment of the invention, the left-most second dummy poly line 40a is disposed in close proximity to the right-most first dummy poly line 30c in the boundary cell BC with the poly pitch P.sub.1. The other second dummy poly line 40b is disposed in close proximity to the second dummy poly line 40a in the boundary cell BC with the poly pitch P.sub.2. According to the embodiment of the invention, the second dummy poly lines 40 may have a shorter length than the first dummy poly lines 30. For example, the second dummy poly lines 40 may have a length along the first direction or the reference y-axis direction that is about 60%70% of the length of the first dummy poly lines 30.

(23) It is advantageous to use the present invention because by introducing the boundary cells, the cell layouts within the integrated circuits, which comprise at least two different poly pitches, can be implemented in the IC design stage without the violation of design rule check.

(24) FIG. 2 is an enlarged plan view of an exemplary boundary cell BC according to one embodiment of the invention, wherein additional components such as power rails, ion well, and diffusion regions are illustrated in addition to the dummy poly lines, wherein like numeral numbers designate like elements, regions, or layers. The regions or boundaries illustrated in the FIG. 2 are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device or layout and are not intended to limit the scope of the invention.

(25) As shown in FIG. 2, the exemplary boundary cell BC may further comprise an N well 310 on a P type semiconductor substrate (not explicitly shown). The exemplary boundary cell BC may further comprise diffusion regions 320 and 330. For example, the diffusion regions 320 may be P.sup.+ regions and the diffusion regions 330 may be N.sup.+ region, but not limited thereto. The exemplary boundary cell BC may further comprise middle end metal patterns 380 between the first dummy poly lines 30a, 30b, and 30c. The exemplary boundary cell BC may further comprise power rails 350 and 360. For example, the power rail 350 may be V.sub.DD power rail and the power rail 360 may be V.sub.SS power rail, but not limited thereto. The power rails 350 and 360 may extend laterally into the neighboring cell C.sub.1.

(26) FIG. 3 illustrates another embodiment of the present invention, wherein a cell layout 2 composed an L-shaped cell LC and a layout of a boundary cell BC are shown. The cell layout 2 may be a portion of an application specific integrated circuit (ASIC) or a system on chip (SoC), but not limited thereto. It is understood that the figure illustrates in a very simplified plan view of two neighboring cells. For the sake of simplicity, only poly lines are shown in each cell.

(27) As shown in FIG. 3, the L-shaped cell LC has cell boundaries 501 that define the bounds and dimension of the L-shaped cell LC. The L-shaped cell LC may be a standard cell that may be chosen from a library of common cells. For example, the L-shaped cell LC may be a logic cell including, but not limited to, a PMOS transistor and an NMOS transistor. According to the embodiment of the invention, a plurality of poly lines 50 is disposed within the L-shaped cell LC. For the sake of simplicity, only poly lines 50a50g are illustrated. According to the embodiment of the invention, the poly lines 50a50g are arranged in parallel with one another. According to the embodiment of the invention, the poly lines 50a50g are the lowest conductor layer in the IC fabrication, which is restricted to be all extended in a unitary direction at the 32 nm node and beyond. In FIG. 3, likewise, the poly lines 50a50g extend along the first direction (reference y-axis direction) . According to the embodiment of the invention, the poly lines 50e50g are arranged in a lower area of the L-shaped cell LC and have a shorter ploy length than the poly lines 50a50d.

(28) According to the embodiment of the invention, the poly lines 50a50g in the L-shaped cell LC have a uniform poly pitch P.sub.1 and uniform ploy line width L.sub.1. The poly pitch P.sub.1 is the combination of the poly line width L.sub.1 and the spacing S.sub.1 between two neighboring poly lines 50a50g. According to the embodiment of the invention, the poly line width L.sub.1 may be 20, 22, 24, or 28 nm, but not limited thereto. According to the embodiment of the invention, the poly pitch P.sub.1 may be 100 nm, but not limited thereto. The use of the uniform pitch and width of the polysilicon portions, and restricting the layout to a uni-direction in the polysilicon layer, has benefits in increasing the tolerance of the finished devices to process variations and critical dimension (CD) tolerance.

(29) According to the embodiment of the invention, the boundary cell BC is contiguous with the L-shaped cell LC. The boundary cell BC has cell boundaries 503 that define the bounds and dimension of the boundary cell BC and may have two common cell boundaries 531 and 532 that are commonly shared with the L-shaped cell LC. Likewise, the boundary cell BC comprises n stripes of first dummy poly lines 30 and m stripes of second dummy poly lines 40, wherein n and m are both integers. According to the embodiment of the invention, preferably, n and m are both integers greater than or equal to 2. In the illustrated embodiment, as shown in FIG. 3, three first dummy poly lines 30a, 30b, 30c and two second dummy poly lines 40a and 40b are demonstrated. However, it is understood that other numbers of the first dummy poly lines 30 and second dummy poly lines 40 may be employed, depending upon the design requirements.

(30) According to the embodiment of the invention, the first dummy poly lines 30 and second dummy poly lines 40 extend along the first direction (i.e. reference y-axis direction). According to the embodiment of the invention, the first dummy poly lines 30 may have fixed or flexible poly line width L.sub.3. For example, the poly line width L.sub.3 may be 20, 22, 24, or 28 nm, but not limited thereto. According to the embodiment of the invention, the second dummy poly lines 40 may have fixed poly line width L.sub.4, for example, L.sub.4=20 nm. According to the embodiment of the invention, the poly lines 50e50g may be aligned with the first dummy poly lines 30a30c, respectively. A distance t between one distal end of the first dummy poly lines 30 and one distal end of the poly lines 50e50g may range between 206 nm and 1256 nm, but not limited thereto.

(31) According to the embodiment of the invention, the parallel first dummy poly lines 30 and the second dummy poly lines 40 are arranged successively along a second direction (i.e. the reference x-axis direction) that is perpendicular to the first direction. According to the embodiment of the invention, the first dummy poly lines 30 may have the poly pitch P.sub.1 and the second dummy poly lines may have the poly pitch P.sub.2 (P.sub.2<P.sub.1). In FIG. 3, the left-most first dummy poly line 30a is disposed in close proximity to the poly line 50d in the L-shaped cell LC with the poly pitch P.sub.l. The common cell boundary 531 is disposed between the left-most first dummy poly line 30a and the poly line 50d. Therefore, the poly lines 50a50g in the L-shaped cell LC and the first dummy poly lines 30 in the boundary cell BC have the same poly pitch P.sub.1.

(32) FIG. 4 is a schematic cell layout 3 showing an exemplary boundary cell placement according to another embodiment of the invention. As shown in FIG. 4, the cell layout 3 comprises an array of standard cells C arranged in a central region. The array of standard cells C may be surrounded by a plurality of boundary cells BC. Some of the boundary cells BC, for example, the boundary cell 103a is disposed at a corner of a specific standard cell, for example, standard cell 101a and the boundary cell 103b is disposed at a corner of a specific standard cell, for example, standard cell 101b. A boundary cell 103c is disposed next to the standard cell 101a along the left side of the standard cell 101a. It is understood that the boundary cells BC may be placed along perimeters or sides of the standard cells in the array or may be disposed at the corners of some of the standard cells in the array.

(33) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.