Semiconductor device including a microelectromechanical structure and an associated integrated electronic circuit

Abstract

An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

Claims

1. An integrated inertial sensor, comprising: a substrate including semiconductor material; a microelectromechanical system (MEMS) structure at a first surface of the substrate, the MEMS structure including a suspended inertial mass; an application-specific integrated circuit (ASIC) electronic circuit electrically coupled to the MEMS structure, at a second surface of the substrate, and opposite to the first surface in a direction transverse to respective planes of extension of the first surface and the second surface; electrically conductive interconnection structures extending through the substrate and having a first end at the first surface and a second end at the second surface, the interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit, and each interconnection structure includes a conductive connection portion surrounded by an insulation structure that electrically insulates the conductive connection portion from the substrate, the insulation structure has a ring conformation and includes a conductive core and an insulating coating that encloses the conductive core and electrically insulates the conductive core from the conductive connection portion, the conductive core and insulating coating together forming an insulation capacitor that electrically insulates the conductive connection portion from the substrate; a covering coupled to the MEMS structure; and a supporting layer coupled to the covering.

2. The integrated inertial sensor of claim 1, wherein the ASIC electronic circuit includes at least one conductive element and the MEMS structure includes at least one conductive element.

3. The integrated inertial sensor of claim 2, further comprising: a first conductive path between the second end of at least one of the interconnection structures and the at least one conductive element of the ASIC electronic circuit; and a second conductive path between the first end of at least one of the interconnection structures and the at least one conductive element of the MEMS structure.

4. The integrated inertial sensor of claim 1, wherein the ASIC electronic circuit includes a transistor that includes conductive regions extending into the substrate from the second surface of the substrate, a gate insulation layer that extends on the second surface of the substrate, and a conductive gate that extends on the gate insulation layer.

5. The integrated inertial sensor of claim 4, further comprising: a conductive path extending through the gate insulation layer and electrically coupling one of the interconnection structures to a conductive element of the ASIC electronic circuit.

6. An integrated inertial sensor, comprising: a substrate having a first surface and a second surface opposite to the first surface; a microelectromechanical system (MEMS) structure on the first surface of the substrate, the MEMS structure having a suspended inertial mass; an application-specific integrated circuit (ASIC) electrically coupled to the MEMS structure and on the second surface of the substrate; a first contact pad on the ASIC being in electrical communication with the ASIC; electrically conductive interconnection structures extending from the first surface to the second surface through the substrate electrically coupling the MEMS structure to the ASIC; a covering coupled to the MEMS structure; a supporting layer coupled to the covering; a second contact pad on the supporting layer; a molding compound on the supporting layer, on the first contact pad, and on the second contact pad; and a bonding wire extending through a molding compound layer and electrically coupling the first contact pad to the second contact pad.

7. The integrated inertial sensor of claim 6, wherein the interconnection structures include a conductive connection portion surrounded by an insulation structure that electrically insulates the conductive connection portion from the substrate.

8. The integrated inertial sensor of claim 7, wherein the insulation structure has a ring conformation and includes a conductive core and an insulating coating that encloses the conductive core and electrically insulates the conductive core from the conductive connection portion, the conductive core and insulating coating together forming an insulation capacitor that electrically insulates the conductive connection portion from the substrate.

9. The integrated inertial sensor of claim 6, wherein the ASIC includes a metallization layer connected to the first contact pad.

10. The integrated inertial sensor of claim 6, wherein the MEMS structure further comprising a plurality of through openings that extend through the MEMS structure.

11. The integrated inertial sensor of claim 6, wherein a molding layer is on the supporting layer and is around the MEMS structure, the ASIC, the covering, and the bonding wire.

12. The integrated inertial sensor of claim 6, further comprising a plurality of anchorage elements extending from the MEMS structure to the substrate, the plurality of anchorage elements coupling the MEMS structure to the substrate.

13. The integrated inertial sensor of claim 6, wherein: the first contact pad is at a first side of the supporting layer; and the supporting layer further includes a third contact pad on a second side opposite to the first side of the supporting layer, the third contact pad is in electrical communication with the first contact pad.

14. The integrated inertial sensor of claim 6, wherein the molding compound is on respective sidewalls of the substrate and the covering.

15. An integrated inertial sensor, comprising: a substrate having a first surface, a second surface opposite to the first surface, and a first sidewall transverse to the first and second surfaces; a microelectromechanical system (MEMS) structure on the first surface of the substrate, the MEMS structure having a second sidewall transverse to the first and second surfaces and the second sidewall being substantially flush with the first sidewall, the MEMS structure having a suspended inertial mass; a covering coupled to the MEMS structure and spaced apart from the first surface of the substrate by the MEMS structure; a supporting layer coupled to the covering, the supporting layer including a first contact pad; an application-specific integrated circuit (ASIC) electrically coupled to the MEMS structure and on the second surface of the substrate, the ASIC having a third sidewall transverse to the first and second surfaces and the third sidewall being substantially flush with the first sidewall, the ASIC including a second contact pad facing away from the substrate; an anchorage element extending from the MEMS structure to the first surface of the substrate, the anchorage element coupling the MEMS structure to the substrate, the anchorage element having a fourth sidewall substantially flush with the first sidewall; and a bonding wire coupling the first contact pad to the second contact pad.

16. The integrated inertial sensor of claim 15, further comprising a molding layer on the supporting layer and around the ASIC, the MEMS structure, the anchorage element, and the bonding wire.

17. The integrated inertial sensor of claim 15, wherein the MEMS structure further including a plurality of through openings extending through the MEMS structure adjacent to the suspended inertial mass.

18. The integrated inertial sensor of claim 15, further comprising a molding compound on the supporting layer and encasing the bonding wire.

19. The integrated inertial sensor of claim 18, wherein the molding compound is on respective sidewalls of the substrate and the covering.

20. The integrated inertial sensor of claim 15, wherein: the first contact pad is at a first side of the supporting layer; and the supporting layer further includes a third contact pad on a second side opposite to the first side of the supporting layer, the third contact pad is in electrical communication with the first contact pad.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein:

(2) FIG. 1 is a schematic cross-sectional view of an integrated semiconductor device of a known type;

(3) FIG. 2 is a schematic cross-sectional view of a further integrated semiconductor device of a known type;

(4) FIGS. 3a-3m are schematic cross-sectional views of an integrated semiconductor device in successive steps of a manufacturing process according to a first embodiment of the present solution;

(5) FIGS. 4a and 4b are schematic cross-sectional views of a package of the integrated semiconductor device;

(6) FIGS. 5a-5l are schematic cross-sectional views of an integrated semiconductor device in successive steps of a manufacturing process according to a second embodiment of the present solution;

(7) FIGS. 6a and 6b are schematic cross-sectional views of a package of the integrated semiconductor device;

(8) FIGS. 7a-7j are schematic cross-sectional views of an integrated semiconductor device in successive steps of a manufacturing process according to a third embodiment of the present solution; and

(9) FIG. 8 is a schematic cross-sectional view of a further variant of the integrated semiconductor device.

DETAILED DESCRIPTION

(10) As will be discussed in detail, one aspect of the present solution generally envisages integrating a MEMS structure and an ASIC electronic circuit in a same processed substrate (or wafer), including semiconductor material and compatible with CMOS or high-speed CMOS (HCMOS) techniques, while maintaining substantially separate and distinct the manufacturing processes of the MEMS structure and the ASIC electronic circuit, so that no particular arrangements or modifications are required to the same processes to prevent mutual negative effects during the corresponding steps.

(11) In particular, the MEMS structure and the ASIC electronic circuit are provided at vertically opposite surfaces of the substrate (or wafer) being processed, and interconnection structures are formed through the substrate for electrical connection between the MEMS structure and the ASIC electronic circuit. During manufacture, thanks to the interposition of the substrate, the process steps carried out to obtain the MEMS structure thus do not affect the ASIC electronic circuit, and, likewise, the process steps carried out to obtain the ASIC electronic circuit do not affect the MEMS structure.

(12) The processes used for providing the MEMS structure and the ASIC electronic circuit may thus be, taken by themselves, of a substantially standard type, without particular modifications being required for integration in the same substrate.

(13) With reference first to FIG. 3A a first embodiment of a process for manufacturing an integrated semiconductor device according to the present solution is now described.

(14) An initial step of the manufacturing process envisages providing a substrate 20, having a first surface 20a and a second surface 20b opposite to one another in a vertical direction (transverse to a main horizontal plane of extension of the first and second surfaces 20a, 20b).

(15) The substrate 20, in this embodiment of an SOI (Silicon-On-Insulator) type, in this case includes: an active layer 21a, of silicon, for example having a thickness of 50-80 μm; an insulating layer 21b, for example of silicon dioxide; and a structural layer 21c, which is also made of silicon, for example with a thickness of 500-600 μm.

(16) Through a surface portion of the substrate 20, starting from the first surface 20a, in this case throughout the whole thickness of the active layer 21a, interconnection structures 22 are then provided, the so-called vias, as shown in FIG. 3B.

(17) These interconnection structures 22 may, for example, be made, as described in U.S. Pat. No. 6,838,362, which is incorporated herein by reference in its entirety.

(18) Each interconnection structure 22 is in this case constituted by a connection portion 22a, here made of silicon, surrounded by an insulation portion 22b, which electrically insulates the connection portion 22a from the remaining substrate 20.

(19) In particular, the insulation portion 22b, having for example a ring conformation, is in turn formed by a conductive core 23, for example of polysilicon, enclosed in an insulating coating 24, for example of silicon oxide, defining an insulation capacitor for electrically insulating the connection portion 22a from the substrate 20.

(20) The manufacturing process then proceeds with manufacturing steps (in themselves known) for the formation of a MEMS structure (designated by 26 in the subsequent FIG. 3K) on the first surface 20a of the substrate 20. The MEMS structure 26 may, for example, define an accelerometer or a gyroscope or a different sensor. In particular, as illustrated in FIG. 3C, manufacture of the MEMS structure 26 envisages in this case formation of a permanent insulation layer 27, on the first surface 20a of the substrate 20 (thus on the active layer 21a of the same substrate 20), and of conductive portions 28, made, for example, of polysilicon, through the permanent insulation layer 27, in contact with the connection portions 22a of the interconnection structures 22.

(21) Conductive elements 29 are further formed on the permanent insulation layer 27, which are also for example of polysilicon (designed to form electrodes and conductive paths of the MEMS structure 26). In particular, some of these conductive elements 29 contact respective conductive portions 28.

(22) A sacrificial insulation layer 30 is then formed over the conductive elements 29 and the permanent insulation layer 27. The sacrificial insulation layer 30 is, for example, made of silicon oxide and may have a thickness of 1.6-1.8 μm.

(23) Through the thickness of the sacrificial insulation layer 30 anchorage elements 31 are then provided, for example, made of polysilicon, which extend vertically to contact respective conductive elements 29.

(24) An epitaxial layer 32 is then grown on the sacrificial insulation layer 30, for example having a thickness comprised between 20 and 60 μm.

(25) According to an aspect of the present solution, an oxide layer 33 is then formed on the epitaxial layer 32, as illustrated in FIG. 3D; this oxide layer 33, as described hereinafter, is designed for providing a fusion bonding. The oxide layer 33 is further subjected to a planarization surface treatment.

(26) Next, as shown in FIG. 3E, a first service wafer 34, for example, of silicon and having a thickness of 600 μm, is bonded on the oxide layer 33. The first service wafer 34 is designed exclusively for functions of handling of the substrate 20 during its processing.

(27) The coupled assembly of the first service wafer 34 and substrate 20 is then subjected to the so-called flip-wafer operation (FIG. 3F) so that the second surface 20b of the substrate 20, and thus the structural layer 21c, is accessible for the subsequent processing steps.

(28) As shown in FIG. 3G, the structural layer 21c is then removed (for example, by lapping, stopping at the insulating layer 21b), and the insulating layer 21b is subsequently removed, for example by chemical etching for rendering accessible a working surface 20b′ of the active layer 21a, vertically opposite to the first surface 20a.

(29) The process then proceeds with CMOS process steps, of a per se known type, for obtaining, within the active layer 21a of the substrate 20, on the aforesaid working surface 20b′, an ASIC electronic circuit (designated by 36 in the subsequent FIG. 3H), designed to be operatively coupled to the MEMS structure 26 of the integrated semiconductor device.

(30) It should be noted that these process steps are independent of the previous steps for obtaining the MEMS structure 26, and may be carried out without repercussions on the elements previously formed of the same MEMS structure 26, which is arranged in fact vertically opposite and separated by the thickness of the active layer 21a of the substrate 20.

(31) In particular, as shown schematically in FIG. 3H, in a per se known manner, the steps of the CMOS process envisage, among others, formation of: functional regions 37 within the active layer 21a starting from the working surface 20b′ (by way of example, doped source and drain regions of a MOSFET are illustrated, obtained by diffusion of dopant, for example of an N type in the case where the active layer 21a has a doping of a P type); an insulation layer 38, which defines, in particular, the gate oxide of the aforesaid MOSFET, over the working surface 20b; electrode elements 39, over the insulation layer 38, including, for example, a gate electrode of the same MOSFET; and, subsequently, a CMOS multilayer 40 on the working surface 20b′, constituted by a stack of metallization layers 40a and interposed dielectric layers 40b, with interconnection elements 40c that electrical connect, in an appropriate way, metallization layers 40a arranged on top of one another. The last metallization layer 40a further defines a top surface of the CMOS multilayer 40.

(32) As illustrated in the same FIG. 3H, during the same processing steps the electrical contacts between the ASIC electronic circuit 36 and the MEMS structure 26, via the interconnection structures 22, are further defined.

(33) In particular, the conductive portions 22a of the interconnection structures 22 are connected to respective electrode elements 39 by conductive elements 41 formed through the insulation layer 38. These conductive elements 41, by a respective interconnection element 40c, are further connected to respective portions of the first metallization layer 40a of the CMOS multilayer 40 (in this way, being appropriately connected to one or more components of the ASIC electronic circuit 36, for example to the aforesaid gate electrode of the MOSFET).

(34) The manufacturing process then proceeds (FIG. 3I), with formation on the multilayer 40 of an oxide layer 43 and then with fusion bonding of a second service wafer 44, for example of silicon and having a thickness of 600 μm, on the aforesaid oxide layer 43. Also this second service wafer 44 is designed exclusively for functions of handling of the substrate 20 being processed.

(35) It should be noted that also this bonding, like the previous one, thus does not create problems of reliability as regards operation of the device, being in fact designed only for handling operations.

(36) Then, a further flip-wafer operation is carried out, following upon which the first service wafer 34 is accessible for processing (the second service wafer 44 instead constituting the handling base).

(37) The above first service wafer 34, as illustrated in FIG. 3K, is then removed (for example, by lapping, stopping at the oxide layer 33), and the oxide layer 33 is subsequently removed, for example by chemical etching, for making the epitaxial layer 32 accessible for subsequent processing.

(38) At this point, the manufacturing of the MEMS structure 26 is completed with final processing steps, which are also in themselves known.

(39) In particular (FIG. 3K), through openings 46 are first formed through the entire thickness of the epitaxial layer 32, through which a chemical etch is carried out for removal of the sacrificial insulating layer 30.

(40) This removal, as shown in the same FIG. 3K, entails in particular release of suspended elements 47, which are arranged above the active layer 21a of the substrate 20, constrained to the same active layer 21a by the anchorage elements 31. In a per se known manner, these suspended elements 47 may, for example, constitute inertial masses of the MEMS structure 26.

(41) Then, a covering 48 is coupled on the epitaxial layer 32, which covers the MEMS structure 26 and the through openings 46 (FIG. 3L). The covering 48 is bonded to the epitaxial layer 32, for example with the glass-frit bonding technique, by bonding regions 49, which define an empty space above the same epitaxial layer 32.

(42) The manufacturing process envisages at this point final steps for providing a package for the MEMS structure 26 and the corresponding ASIC electronic circuit 36. In particular, a further flip-wafer operation is carried out, following upon which the second service wafer 44 is available for processing, and subsequently the service wafer 44 is removed, for example via lapping.

(43) As illustrated in FIG. 3M, a passivation layer 50 is formed on the oxide layer 43, having functions of protection for the underlying ASIC electronic circuit 36, and contact openings 51 are then formed through the same oxide layer 44 and passivation layer 50.

(44) Then contact pads 52 are formed within these contact openings, in electrical contact with respective portions of the last metallization layer 40a, designed to enable electrical contacting of the ASIC electronic circuit 36 from outside the package of the integrated semiconductor device.

(45) FIG. 4A shows a possible embodiment of a package 54, of a standard land grid array (LGA) type, for the integrated semiconductor device, here designated as a whole by 55.

(46) The package 54 includes a supporting layer 56, on which the covering 48 is bonded, for example using adhesive, and a molding 57, which coats the supporting layer 56 and the stack formed by the MEMS structure 26 and by the corresponding ASIC electronic circuit 36, made starting from the same substrate 20. A top surface of the aforesaid molding 57 in this case constitutes a top surface of the package 54, in contact with the external environment.

(47) Electrical bonding wires 58 electrically connect the contact pads 52 to further contact pads 59 carried by the supporting layer 56, via the wire-bonding technique.

(48) The aforesaid further contact pads 59 are further connected by electrical through vias (here not illustrated), which traverse the entire thickness of the supporting layer 56, to electrical-contact elements 60 carried by the bottom surface of the supporting layer 56 (which in this case constitutes the bottom base of the package 54, in contact with the external environment).

(49) FIG. 4B shows a further embodiment of the package 54 of the integrated semiconductor device 55, of a ball grid array (BGA) type without molding.

(50) In this case, the covering 48 itself defines a surface of the package 54, in contact with the external environment, and the passivation layer 50 that overlies the CMOS multilayer 40 of the ASIC electronic circuit 46 defines, itself, the outer opposite surface of the package 54 (which thus does not comprise any additional supporting or molding layer).

(51) The electrical-contact elements 60, in this case in the form of conductive bumps, electrically contact the contact pads 52 on the outer surface of the package 54.

(52) A second embodiment of the present solution is now described, which differs in that it envisages a different process for manufacturing the MEMS structure 26, which is also of a per se known type (the MEMS structure 26 defines in this case, for example, a pressure sensor). No substantial modifications are, instead, envisaged in the flow of integration of the MEMS structure 26 with the associated ASIC electronic circuit 36 in the same substrate 20.

(53) As shown in FIG. 5A, the process starts once again with the provision of the substrate 20, of an SOI type.

(54) In this case, elements constituting the pressure sensor defined by the MEMS structure 26 are provided in the active layer 21a of the substrate 20.

(55) In particular, as shown in FIG. 5B, at least one buried cavity 60 is first provided within the active layer 21a, separated from the first top surface 20a of the substrate 20 by a membrane 61. Further provided are surface diffusions for formation of piezoresistor elements 62 in a surface portion of the membrane 61.

(56) As described previously, interconnection structures 22 are formed through the active layer 21a, in this case laterally with respect to the arrangement of the buried cavity 60 and the membrane 61.

(57) The manufacturing process then proceeds, as described previously, with: formation of the oxide layer 33 on the first surface 20a of the substrate 20 (FIG. 5C); subsequent bonding of the first service wafer 34 on the oxide layer 33 (FIG. 5D); wafer flipping (FIG. 5E); removal of the supporting layer 21c and of the insulating layer 21b of the substrate 20 (FIG. 5F); and subsequent CMOS process to obtain the ASIC electronic circuit 36 starting from the working surface 20b′ of the active layer 21a of the same substrate 20, and also to obtain electrical contacts between the ASIC electronic circuit 36 and the MEMS structure 26 through the interconnection structures 22 (FIG. 5G); subsequent bonding of the second service wafer 44 on the oxide layer 43 previously formed on the CMOS multilayer 40 (FIG. 5H); and wafer flipping, and removal of the oxide layer 43 and second service wafer 44 for processing of the first surface 20a of the substrate 20 (FIG. 5I).

(58) The manufacturing process then envisages the steps of completion of the MEMS structure 26 integrated in the substrate 20, which include in this case (FIG. 5J): formation of a surface insulation layer 64, for example of TEOS (Tetraethyl Orthosilicate); deposition and definition of a conductive layer 65 on the surface insulation layer 64 and within trenches that traverse the same surface insulation layer 64 to contact the piezoresistor elements 62 and also the connection portions 22a of the interconnection structures 22; and formation of a passivation layer 66 on the conductive layer 65.

(59) In a way similar to what has been described previously, the manufacturing process then proceeds (FIG. 5K) with coupling of the covering 48, in this case on the passivation layer 66, through which in this case access openings 68 are provided for enabling pressure waves coming from the external environment to reach the MEMS structure 26 integrated in the substrate 20.

(60) At this point (FIG. 5L), the structure being processed is flipped, the second service wafer 44 is removed, and the contact pads 52 for contacting the respective portions of the last metallization layer of the CMOS multilayer 40 are formed.

(61) The package 54 of the integrated semiconductor device 55 also in this case (as described in detail previously) may be, for example, of a standard LGA type, as illustrated in FIG. 6A, or else of a BGA type without molding as illustrated in FIG. 6B.

(62) With reference first to FIG. 7A, a third embodiment of the present solution is now described, which differs from the one illustrated previously in that it starts from a standard substrate, for example with a doping of a P type, instead of an SOI composite substrate. As regards formation of the MEMS structure 26, this further embodiment does not differ, instead, from the first embodiment previously described.

(63) As shown in FIG. 7B, in a surface portion of the substrate 20 at the first surface 20a, designated by 21a by analogy with what has been discussed previously, the interconnection structures 22 are provided, here formed by the connection portion 22a electrically insulated from the substrate 20 by the insulation portion 22b (here constituted by a simple vertical structure of silicon oxide or other insulating material that extends in depth throughout the thickness of the surface portion 21a).

(64) On the first surface 20a of the substrate 20, the permanent insulation layer 27 is then formed, as discussed previously, with the conductive portions 28 that traverse the permanent insulation layer 27 to contact the connection portions 22a of the interconnection structures 22 (FIG. 7B).

(65) The manufacturing process then proceeds, as described previously, with the steps of formation of the MEMS structure 26 (FIG. 7C), which envisages also in this case formation of: the conductive elements 29 on the permanent insulation layer 27; the sacrificial insulation layer 30, on the conductive elements 29 and on the permanent insulation layer 27; the anchorage elements 31 through the thickness of the sacrificial insulation layer 30; and the epitaxial layer 32 on the sacrificial insulation layer 30.

(66) The oxide layer 33 is then formed on the first surface 20a of the substrate 20 and the first service wafer 34 is then bonded on the same oxide layer 33.

(67) Next (FIG. 7D), the wafer is flipped and an etch of the substrate 20 is performed starting from the second surface 20b, until the surface portion 21a and the interconnection structures 22 are reached, thus defining the working surface 20b′, starting from which the CMOS processing steps will then be carried out.

(68) As illustrated previously, the manufacturing process then proceeds with: the CMOS process steps for providing the ASIC electronic circuit 36 starting from the aforesaid working surface 20b′, and also electrical contacts between the ASIC electronic circuit 36 and the MEMS structure 26 through the interconnection structures 22 (FIG. 7E); subsequent bonding of the second service wafer 44 on the oxide layer 43 previously formed on the CMOS multilayer 40 (FIG. 7F); and flipping of the wafer, and removal of the oxide layer 43 and the second service wafer 44 (FIG. 7G).

(69) The last processing steps are thus performed leading to formation of the MEMS structure 26, as illustrated in FIG. 7H, and to subsequent coupling with the covering 48 (FIG. 7I).

(70) The structure being processed is then flipped again for removing the second service wafer 44 and defining the contact pads 52 for contacting the respective portions of the last metallization layer of the CMOS multilayer 40 (FIG. 7J).

(71) In a way not illustrated herein, the process proceeds with formation of the package 54 of the integrated semiconductor device 55, in a way altogether similar to what has been discussed previously.

(72) The advantages of the solution proposed emerge clearly from the previous description.

(73) In particular, the solution described makes it possible to obtain a marked reduction in the horizontal dimensions (in the plane) and in the vertical dimension (out of the plane) of the resulting integrated semiconductor device 55.

(74) The MEMS structure 26 and the CMOS electronic circuit 36 are provided in a same substrate 20 and may possibly be manufactured in a same production environment.

(75) In general, the solution described affords an evident advantage in terms of manufacturing costs.

(76) Moreover, further advantages are obtained in terms of performance, thanks to the reduction of the (capacitive and inductive) parasitic components in the electrical connection between the MEMS structure 26 and the ASIC electronic circuit 36, and to the consequent reduction of the noise generated, as well as in terms of reliability, thanks to the fact that the electrical connection between the MEMS structure 26 and the ASIC electronic circuit 36 is obtained with planar techniques at the front-end level, instead of being obtained with bonding techniques.

(77) Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure.

(78) In particular, it is evident that the process described may find advantageous application also in the case where different technologies are used for manufacturing the MEMS structure 26 and/or the associated ASIC electronic circuit 36.

(79) It is likewise evident that further types of package 54 may be envisaged for housing the MEMS structure 26 and the ASIC electronic circuit 36, integrated starting from the same substrate 20.

(80) Furthermore, different embodiments may be envisaged for the interconnection structures 22, through the substrate 20, designed to enable connection between the MEMS structure 26 and the associated ASIC electronic circuit 36.

(81) For instance, as illustrated in FIG. 8, the connection portion 22a of the interconnection structures 22, electrically insulated from the substrate 20 by the insulation portion 22b (obtained once again by a simple vertical structure of silicon oxide or other insulating material that extends in depth through the thickness of the surface portion 21a) may include a vertical column of conductive material, in the example polysilicon. In this case, the electrical contact with the first metallization layer 40a of the multilayer 40 of the CMOS structure of the ASIC electronic circuit 36 may be defined directly by the connection structure 22 and by an interconnection element 40c, which extends between a terminal end of the same interconnection structure 22, at the working surface 20b′, and the first metallization layer 40a (as shown once again in FIG. 8); advantageously, this electrical contact is of an ohmic type.

(82) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.