Method of DC voltage—pulse voltage conversion

Abstract

In a method of DC voltagepulse voltage conversion, DC voltage is provided; a succession of controlling square pulses having adjustable pulse ratio is generated; an inductive load is periodically connected to outputs of a source of the DC voltage using the succession of the controlling square pulses; pulse current flowing through the inductive load is generated; a predefined value of resistance of an electronically-controlled resistor included in a circuit of the pulse current flowing through the inductive load is formed, and the pulse current is adjusted by the electronically-controlled resistor, whereby adjusting the level of pulse electromagnetic noise radiated to the environment is achieved.

Claims

1. A method of DC voltagepulse voltage conversion comprising the steps of: providing DC voltage; generating a succession of controlling square pulses having adjustable pulse ratio; periodically connecting an inductive load to outputs of a source of said DC voltage using said succession of said controlling square pulses; generating pulse current flowing through said inductive load; adjusting said pulse current; and forming adjustable pulse voltage, wherein a predefined value of resistance of an electronically-controlled resistor included in a circuit of said pulse current flowing through said inductive load is formed, and said adjusting said pulse current is performed by said electronically-controlled resistor, to thereby adjust the level of pulse electromagnetic noise radiated to the environment.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The above and other features and advantages of the proposed method are described in the specification below with the reference to accompanying drawings where

(2) FIG. 1 is an example of a functional circuit of a DC voltagepulse voltage converter embodying a method of the present proposal, and

(3) FIG. 2 shows time diagrams illustrating the operation of the converter of FIG. 1.

DETAILED DESCRIPTION

(4) According to FIG. 1, the DC voltagepulse voltage converter comprises specifically: a high DC voltage source 1; an inductive load 2 made as a winding on a magnetic conductor and including a primary winding 3 of a transformer 4 using a ferromagnetic core 5 and a secondary winding 6 connected to a rectifier 7 with its load (not shown), the inductive load 2 being connected via one of terminals thereof (first), 8, to a positive terminal 9 of the high DC voltage source 1; a controllable switch 10, including, e.g., a MOS transistor 11, connected via a first (main) terminal 12 thereof (drain of the MOS transistor 11) to another (second) terminal 13 of the inductive load 2; a controllable square wave generator 14 connected by an output 15 thereof to a control input 16 of the controllable switch 10 (gate of the MOS transistor 11 thereof); a first control voltage driver 17 including, e.g., a DC voltage source 18 and a potentiometer 19, a first terminal 20 of the potentiometer 19 being connected to a positive terminal 21 of the DC voltage source 18, a second terminal 22 of the potentiometer 19 being connected to a negative terminal 23 of the DC voltage source 18 (which terminal 23 is a first terminal 24 of the first control voltage driver 17), a third terminal (a slider) 25 of the potentiometer 19 (which terminal 25 is a second output 26 of the first control voltage driver 17) being connected to a control input 27 of the controllable square wave generator 14; a low DC voltage source 28, a positive terminal 29 of the source 28 being connected to a first power input 30 of the controllable square wave generator 14, a negative terminal 31 of the source 28 being connected to a negative terminal 32 of the high DC voltage source 1; a limiting resistor 33 connected via a terminal 34 thereof to an output 35 of the controllable switch 10 (to source of the MOS transistor 11); an electronically controlled resistor (ECR) 36 connected by a first terminal 37 thereof to another terminal 38 of the limiting resistor 33, the ECR comprising, e.g., a MOS transistor 39 (drain of the MOS transistor 39 being the first terminal 37 of the ECR 36), an additional resistor 40 (a first terminal 41 of the additional resistor 40 being connected to the drain of the MOS transistor 39, a second terminal 42 of the additional resistor 40 being connected to source of the MOS transistor 39 and to a second terminal 43 of the ECR 36), an operational amplifier (OA) 44 (an output 45 of the OA 44 being connected to gate of the MOS transistor 39), an offset voltage source (OVS) 46 (a positive terminal of the OVS 46 being connected to a non-inverting (+) input 48 of the OA 44, a negative terminal 49 of the OVS 46 being connected to the second terminal 43 of the ECR 36), a first resistor 50, and a second resistor 51 (the first 50 and second 51 resistor being connected to each other and jointly defining transmission efficiency of the OA 44, a terminal 52 of the first resistor 50 being connected to the output 45 of the OA 44, a terminal 53 of the second resistor 51 being a control input 54 of the ECR 36, a point of connection of the first 50 and second 51 resistors being connected to an inverting () input 55 of the OA 44; a second driver 56 of control voltage (called further below a second control voltage driver 56), a first input 57 of the second control voltage driver 56 being connected to a first output 58 of the rectifier 7, a first output 59 of the second control voltage driver 56 being connected to a second output 60 of the rectifier 7, a second input 61 of the second control voltage driver 56 being connected to the positive terminal 29 of the low DC voltage source 28, a second output 62 of the second control voltage driver 56 being connected to the control input of the ECR 36, and a third output 63 of the second control voltage driver 56 being connected to the first terminal 24 of the first control voltage driver 17, to a second power input 64 of the controllable square wave generator 14, to a second terminal 43 of the ECR 36, and to the negative terminal 32 of the high voltage DC voltage source 1.

(5) With the above in view, the second control voltage driver 56 can comprise a first current setting resistor 65, a second current setting resistor 66, a third current setting resistor 67, a voltage-stabilized current regulator 68, a optocoupler 69, and a resistor 70, the first current setting resistor 65 being connected to the second current setting resistor 66, the second current setting resistor 66 being connected to the third current setting resistor 67, a first terminal of the first current setting resistor 65 being connected to a first input 72 of the optocoupler 69, a point of connection of the first current setting resistor 65 and the second current setting resistor 66 being the first input 57 of the second control voltage driver 56, a point of connection of the second current setting resistor 66 and the third current setting resistor 67 being connected to a control input 73 of the voltage-stabilized current regulator 68, a first terminal 74 of the voltage-stabilized current regulator 68 being connected to a second input 75 of the optocoupler 69, a second terminal 76 of the third current setting resistor 67 being connected to a second terminal 77 of the voltage-stabilized current regulator 68 and being the first output 59 of the second control voltage driver 56. At the same time, a first output 78 of the optocoupler 69 is connected to a first terminal 79 of the resistor 70 and is the second output 62 of the second control voltage driver 56, whereas a second terminal 80 of the resistor 70 is the second input 61 of the second control voltage driver 56.

(6) The time diagrams presented in FIG. 2 show:

(7) 2aoutput voltage U.sub.o of the high voltage DC voltage source 1;

(8) 2bpulses U.sub.ctr at the control input 16 of the controllable switch 10;

(9) 2cramp-up current flowing through the inductive load 2 supply circuit at the maximal resistance of the ECR 36 and reaching the minimal value I.sub.o min by the end of the pulse of U.sub.ctr;

(10) 2dhigh pulse voltage U.sub.min between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36 at the maximal resistance of the ECR 36;

(11) 2eramp-up current flowing through the inductive load 2 supply circuit at the minimal resistance of the ECR 36 and reaching the maximal value I.sub.o max by the end of the pulse of U.sub.ctr;

(12) 2fhigh pulse voltage U.sub.max between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36 at the minimal resistance of the ECR 36.

(13) The way the proposed method is implemented is discussed below as exemplified in the operation of the converter of FIG. 1 embodying the method.

(14) As DC voltage from the terminals of the low DC voltage source 28 is applied to the power inputs 30 and 64 of the controllable square wave generator 14, the latter starts generating square pulses (FIG. 2b), the pulse ratio of the square pulses being defined by the value of the control voltage applied from the output 26 of the first control voltage driver 17 to the control input 27 of the controllable square wave generator 14.

(15) Changing the control voltage at the output 26 of the first control voltage driver 17 can be realized, for example, by moving the slider 25 of the potentiometer 19 connected by the terminals 20 and 22 thereof to the positive 21 and negative 23 terminals of the DC voltage source 18, respectively. In this way, generating a succession of control square pulses with regulated pulse ratio takes place.

(16) The square pulses from the output 15 of the controllable square wave generator 14 arrive at the control input 16 of the controllable switch 10 (at the gate of the MOS transistor 11), resulting in opening the controllable switch 10. Pulse current starts flowing through the controllable switch 10 in the circuit: the positive terminal 9 of the high DC voltage source 1 (FIG. 2a)the first terminal 8 of the inductive load 2the second terminal 13 of the inductive load 2the controllable switch 10the limiting resistor 33the ECR 36the second terminal 43 of the ECR 36the negative terminal 32 of the high DC voltage source 1.

(17) In such a way, the succession of the control pulses periodically connects the inductive load 2 to the terminals of the high DC voltage source 1, has the pulse current through the inductive load 2 generated, and limits the same by means of the limiting resistor 33.

(18) A self-inductance emf brought about in the inductive load 2 as this takes place prevents the current in the circuit from changing instantly. As a result of this, the current ramps up linearly during the square pulse (FIGS. 2c and 2e) and reaches, by the end of the square pulse, a preset value of I.sub.o (either I.sub.o min for FIG. 2c, or I.sub.o max for FIG. 2e). At this, the value of high pulse voltage between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36 is proportional to the value of I.sub.o. The value of I.sub.o, however, is defined by resistance of all the elements of the above circuit, i.e.
I.sub.o=K.sub.l/(R.sub.l+R.sub.tr+R.sub.lim+R.sub.ECR)(1),
where K.sub.l is a proportionality coefficient,

(19) R.sub.lactive resistance of the inductive load 2,

(20) R.sub.trresistance of the open controllable switch 10 (resistance of the open MOS transistor 11),

(21) R.sub.limresistance of the limiting resistor 33,

(22) R.sub.ECRresistance of the ECR 36.

(23) Due to smallness R.sub.l<<R.sub.lim and R.sub.tr<<R.sub.lim, the formula (1) can be reduced to
I.sub.oK.sub.1/(R.sub.lim+R.sub.ECR)(2)

(24) Thus, the value of I.sub.o and, consequently, the value of the high pulse voltage between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36 can be set by changing the resistance of the ECR 36.

(25) Such a change is achieved by means of changing output voltage of the rectifier 7 between the first, 58, and second, 60, outputs thereof (for example, due to the change of rectifier 7 load resistance). This changing voltage is applied to the first input 57 of the second control voltage driver 56 and is transferred, via the first current setting resistor 65, to the first input 72 of the optocoupler 69. Therefore, changing current flows via the optocoupler 69, the value of the current depending on the voltage at the first input 72 of the optocoupler 69 and on the parameters of the second current setting resistor 66, third current setting resistor 67, and voltage-stabilized current regulator 68. Accordingly, changing voltage appears also at the output 78 of the optocoupler 69 and at the first terminal 79 of the resistor 70, whose second terminal 80 is connected to the positive terminal 29 of the low DC voltage source 28 via the second input 61 of the second control voltage driver 56. This changing voltage is applied to the second output 62 of the second control voltage driver 56.

(26) As voltage at the second output 62 of the second control voltage driver 56 changes, control voltage (arriving from the second output 62 of the second control voltage driver 56 to the control input 54 of the ECR 36) is applied via the second resistor 51 to the inverting () input 55 of the OA 44 acting as a DC voltage amplifier. In that, the operation mode of the OA 44 is set by the voltage at the positive output 47 of the offset voltage source 46, the voltage being applied to the non-inverting (+) input 48 of the OA 44. Thus, a control signal (whose value is defined by correlation of resistance of the first, 50, and second, 51, resistors setting transmission ratio of the OA 44) is generated at the output 45 of the OA 44 and directed to the gate of the MOS transistor 39. When the control signal is zero, the MOS transistor 39 is closed and has no effect on resistance R.sub.add of the additional resistor 40. Therefore, the resistance of the ECR 36 is maximal and amounts to
R.sub.ECR=R.sub.add(3),
whereas I.sub.o is minimal and equals to
I.sub.o min=K.sub.l/(R.sub.lim+R.sub.add)(4)

(27) It is the minimal value of high pulse voltage between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36 (FIG. 2d) and the minimal level of pulse electromagnetic noise radiated to the environment that correspond to the minimal current I.sub.o min flowing through the inductive load 2 at R.sub.ECR=R.sub.add (FIG. 2c).

(28) While the output voltage of the second control voltage driver 56 changes (which can be the case, for example, when lowering the output voltage of the rectifier 7), the control signal arriving to the gate of the MOS transistor 39 increases and opens the MOS transistor 39. Current starts flowing through the MOS transistor 39, and the through resistance of the MOS transistor starts decreasing and shunting R.sub.add of the additional resistor 40. Thus, the resultant resistance of the ECR 36 starts decreasing. At the extreme, where the signal arriving to the gate of the MOS transistor 39 is so large that the MOS transistor 39 is completely open, it fully shunts the additional resistor 40, resistance of the ECR 36 nears zero, and I.sub.o becomes maximal and equal to
I.sub.o max=K.sub.l/R.sub.lim(5).

(29) It is the maximal value of high pulse voltage between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36 (FIG. 2f) and the maximal level of pulse electromagnetic noise radiated to the environment that correspond to the maximal current I.sub.o max flowing through the inductive load 2 at R.sub.ECR=0 (FIG. 2e).

(30) Thus, changing the resistance of the ECR 36 at changing the output voltage of the second control voltage driver 56 makes it possible in the proposed method to change the current flowing in the above-discussed circuit within limits from I.sub.o min to I.sub.o max. In this manner the value of the high pulse voltage between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36 is set.

(31) In the prior art, the prototype including, the pulse ratio is changed (for example by means of the first control voltage driver 17 and controllable square wave generator 14). However, as the pulse ratio changes, I.sub.o remains unchanged and equal to I.sub.o max. Consequently, the value of high pulse voltage between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36 remains unchanged.

(32) Occurring with that is radiation to the environment, during the existence of the pulse, of a portion of pulse power
P.sub.rad=K.sub.2I.sub.o max.sup.2(6),
where K.sub.2 is the second coefficient of proportionality.

(33) Radiating a portion of the pulse power to the environment gives rise to pulse electromagnetic noise interfering with the operation of closely adjacent radio electronics and negatively affecting their efficiency. Additionally, electromagnetic radiation to the environment results in worsening ecology in the human environment.

(34) To the contrary, it is suggested in the proposed technical solution to change I.sub.o within the limits between I.sub.o min and I.sub.o max by means of controlling resistance of the ECR 36. Therefore, the electromagnetic noise of maximum value P.sub.rad=K.sub.2I.sub.o max.sup.2 takes place only at the nominal value of the high pulse voltage between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36. As I.sub.o decreases, the power of pulse electromagnetic noise falls as the square of the I.sub.o, and due to that the influence of the noise on the efficiency of the closely adjacent radio electronics and the ecology in the human environment lowers.

(35) Hence, the converter implementing the proposed method performs same functions when compared with converters embodying prior art methods. Its circuitry differs from that used in the prior art converters by making it possible to change not only the pulse ratio of the control square pulses, but also the value of the high pulse voltage between the terminal 13 of the inductive load 2 and the terminal 43 of the ECR 36, whereby the declared technical result is attained.

(36) The functional units making the above-described converter can be realized in various ways.

(37) For example, the controlled square wave generator 14 can include a microchip functioning as a pulse-width modulator (e.g., UCC2813QDR-5Q1 of Texas Instruments (TI)), or a microchip fulfilling the function of a pulse-frequency modulator (e.g. FAN-6300H of ON Semiconductor), or any other circuitry providing the pulse ration change in a succession of square pulses.

(38) The first control voltage driver 17 can be realized as shown in FIG. 1 or using any other way of converting a control action to a control voltage, including a feedback loop.

(39) The second control voltage driver 56 can be realized either as shown in FIG. 1 or employing conventional sources of reference voltage and operational amplifiers, or by using any other way of converting a control action to voltage controlling the ECR.

(40) Microchip TL431 of TI or its analogs can be used as the voltage-stabilized current regulator shown in FIG. 1.

(41) The transistor of the controllable switch 10 can be of a bipolar, or of a MOS, or of an IGBT-type. The switch itself can comprise additional circuitry improving its performance.

(42) Low voltage sources 18, 28, and 46in the converter as a whole and in the first control voltage driver 17 and the ECR 36 can be realized as one low voltage source provided with relevant resistive dividers.

(43) The ECR 36 can be used as shown in FIG. 1, or employ circuitry disclosed in ABC of transistor circuitry by A. Petrov, R L, 1994 (http://zpostbox.ru/az0.htm, Ch. 11, Synchronous rectifiers), or use any other circuitry making it possible to change the resistance of a portion of a circuit from nearly zero to the value comparable with the resistance Rum.

(44) All the other components of the converter are well known and disclosed in various sources dealing with pulse technique and radio electronics.

(45) In any of the above implementations, changing current flowing through the inductive load and, thus, changing output pulse voltage is made possible, to thereby decrease the level of pulse electromagnetic noise radiated to the environment and, in this way, achieve the technical result of the present method of DC voltage to pulse voltage conversion.