Switching power supply circuit having a switching circuit and a coil current emulation circuit

Abstract

A switching power supply circuit, which keeps an output voltage constant highly accurately by a buck-boost action, is provided. The switching power supply circuit comprises: a switching circuit formed by combining four switching elements with a coil in the shape of H; a coil current emulation circuit for generating an output voltage VC similar to a coil current; and a control circuit which, based on a feedback voltage representing an output voltage VO of the switching circuit, and the output voltage VC, performs on-off control of the switching circuit. The coil current emulation circuit has a CR integration circuit to generate the output voltage VC similar to the coil current. One of three voltages is applied to one terminal of the CR integration circuit, while a voltage proportional to the output voltage VO is applied to the other terminal of the CR integration circuit. The three voltages are a voltage proportional to an input voltage VIN, a ground voltage, and a voltage proportional to the sum of the input voltage VIN and the output voltage VO.

Claims

1. A switching power supply circuit, comprising: a switching circuit having a first switching element connected between an input terminal, where an input voltage is applied, and one terminal of a coil; a second switching element or a first diode connected between a ground potential and the one terminal; a third switching element connected between the ground potential and another terminal of the coil; and a fourth switching element or a second diode connected between an output terminal and the other terminal; a coil current emulation circuit for generating an output voltage similar to a coil current flowing through the coil; and a control circuit which, based on a feedback voltage representing an output voltage being a voltage of the output terminal, and the output voltage of the coil current emulation circuit, performs on-off control of the switching circuit to have the switching circuit carry out a predetermined buck-boost action so that the output voltage generated at the output terminal of the switching circuit becomes a predetermined set voltage, wherein the coil current emulation circuit has a CR integration circuit, and provides an output terminal, between a capacitor and a resistor constituting the CR integration circuit, for outputting the output voltage similar to the coil current, one of three voltages is applied to one terminal of the CR integration circuit by selection associated with an on/off action of switch means, while a voltage proportional to the output voltage is applied to another terminal of the CR integration circuit, and the three voltages are a voltage proportional to the input voltage, a ground voltage, and a voltage proportional to a sum of the input voltage and the output voltage, and on/off control of the switch means is performed by a control signal which is outputted by the control circuit in accordance with a state of the one terminal and the other terminal of the coil, wherein the control circuit comprises: an error amplification circuit for comparing a predetermined reference voltage with the feedback voltage, and amplifying an error representing a difference between the reference voltage and the feedback voltage to generate an error voltage; a valley detection circuit for detecting a valley, where the coil current is minimal, based on the output voltage similar to the coil current, the error voltage, and the reference voltage, to generate a valley detection signal representing the valley; and a switch control unit which generates a switching signal for performing changeover control of the switching element based on the valley detection signal and a predetermined timing representing passage of a preset time, thereby performing the predetermined buck-boost action via the switching circuit; and performs the on/off control of the switch means by the control signal, and wherein the valley detection circuit comprises: a summing circuit for adding the output voltage similar to the coil current to the error voltage to generate an addition output voltage, and a valley detecting comparison circuit for comparing the addition output voltage with the reference voltage to detect the valley.

2. The switching power supply circuit according to claim 1, wherein the predetermined timing is defined based on the output voltage, the input voltage, or the reference voltage.

3. A switching power supply circuit, comprising: a switching circuit having a first switching element connected between an input terminal, where an input voltage is applied, and one terminal of a coil; a second switching element or a first diode connected between a ground potential and the one terminal; a third switching element connected between the ground potential and another terminal of the coil; and a fourth switching element or a second diode connected between an output terminal and the other terminal; a coil current emulation circuit for generating an output voltage similar to a coil current flowing through the coil; and a control circuit which, based on a feedback voltage representing an output voltage being a voltage of the output terminal, and the output voltage of the coil current emulation circuit, performs on-off control of the switching circuit to have the switching circuit carry out a predetermined buck-boost action so that the output voltage generated at the output terminal of the switching circuit becomes a predetermined set voltage, wherein the coil current emulation circuit has a CR integration circuit, and provides an output terminal, between a capacitor and a resistor constituting the CR integration circuit, for outputting the output voltage similar to the coil current, one of three voltages is applied to one terminal of the CR integration circuit by selection associated with an on/off action of switch means, while a voltage proportional to the output voltage is applied to another terminal of the CR integration circuit, and the three voltages are a voltage proportional to the input voltage, a ground voltage, and a voltage proportional to a sum of the input voltage and the output voltage, and on/off control of the switch means is performed by a control signal which is outputted by the control circuit in accordance with a state of the one terminal and the other terminal of the coil, wherein the control circuit comprises: an error amplification circuit for comparing a predetermined reference voltage with the feedback voltage, and amplifying an error representing a difference between the reference voltage and the feedback voltage to generate an error voltage; a peak detection circuit for detecting a peak, where the coil current is maximal, based on the output voltage similar to the coil current, the error voltage, and the reference voltage, to generate a peak detection signal representing the peak; and a switch control unit which generates a switching signal for performing changeover control of the switching element based on the peak detection signal and a predetermined timing representing passage of a preset time, thereby performing the predetermined buck-boost action via the switching circuit; and performs the on/off control of the switch means by the control signal, and wherein the peak detection circuit comprises: a summing circuit for adding the output voltage similar to the coil current to the error voltage to generate an addition output voltage, and a peak detecting comparison circuit for comparing the addition output voltage with the reference voltage to detect the peak.

4. The switching power supply circuit according to claim 3, wherein the predetermined timing is defined based on the output voltage, the input voltage, or the reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram showing a switching power supply circuit according to a first embodiment of the present invention.

(2) FIGS. 2A-2H are explanation drawings showing the timing of a buck action in the switching power supply circuit shown in FIG. 1.

(3) FIGS. 3A-3H are explanation drawings showing the timing of a buck-boost action in the switching power supply circuit shown in FIG. 1.

(4) FIGS. 4A-4H are explanation drawings showing the timing of the buck-boost action in the switching power supply circuit shown in FIG. 1.

(5) FIGS. 5A-5H are explanation drawings showing the timing of the buck-boost action in the switching power supply circuit shown in FIG. 1.

(6) FIGS. 6A-6H are explanation drawings showing the timing of a boost action in the switching power supply circuit shown in FIG. 1.

(7) FIGS. 7A-7C are schematic views showing moves during a full-bridge action in the switching power supply circuit shown in FIG. 1.

(8) FIG. 8 is a circuit diagram showing a coil current emulation circuit which is a concrete example of a coil current detection circuit.

(9) FIG. 9 is a block diagram showing a switching power supply circuit according to a second embodiment of the present invention.

(10) FIGS. 10A-10H are explanation drawings showing the timing of a buck action in the switching power supply circuit shown in FIG. 9.

(11) FIGS. 11A-11H are explanation drawings showing the timing of a buck-boost action in the switching power supply circuit shown in FIG. 9.

(12) FIGS. 12A-12H are explanation drawings showing the timing of the buck-boost action in the switching power supply circuit shown in FIG. 9.

(13) FIGS. 13A-13H are explanation drawings showing the timing of the buck-boost action in the switching power supply circuit shown in FIG. 9.

(14) FIGS. 14A-14H are explanation drawings showing the timing of a boost action in the switching power supply circuit shown in FIG. 9.

(15) FIGS. 15A-15C are schematic views showing moves during a full-bridge action in the switching power supply circuit shown in FIG. 9.

MODE FOR CARRYING OUT THE INVENTION

(16) The switching power supply circuit according to the present invention can be configured in two types, a valley detection system and a peak detection system. The valley detection system is designed to make a changeover from an OFF-period to an ON-period of switching based on detection of a valley in a coil current IL. The peak detection system, on the other hand, is designed to make a changeover from the ON-period to the OFF-period of switching based on detection of a peak in the coil current IL. Embodiments of the switching power supply circuit of the present invention concerned with both systems will now be described in detail with reference to the accompanying drawings.

(17) <First Embodiment>

(18) FIG. 1 is a block diagram showing the switching power supply circuit according to a first embodiment of the present invention. This switching power supply circuit is an example on the valley detection system.

(19) As shown in FIG. 1, the switching power supply circuit according to the present embodiment has a control circuit I, a coil current emulation circuit 4, and a switching circuit 8. The control circuit I performs ON/OFF control of the switching circuit 8, based on a feedback voltage, which represents an output voltage VO being a voltage of an output terminal OUT, and an output voltage VC of the coil current emulation circuit 4, to have the switching circuit 8 carry out a predetermined buck, boost or buck-boost action so that the output voltage VO generated at the output terminal OUT of the switching circuit 8 becomes a predetermined set voltage. For this purpose, the control circuit I according to the present embodiment is equipped with an error amplification circuit 1, a reference voltage generation circuit 2, a valley detection circuit II composed of a summing circuit 3 and a comparison circuit 5, a switch control unit 6, and an oscillation circuit 7.

(20) The output voltage VO is divided by feedback resistors FR1, FR2, and inputted to a non-inverting input terminal of the error amplification circuit 1. On the other hand, an inverting input terminal of the error amplification circuit 1 receives an input of a reference voltage Vref which has been generated by the reference voltage generation circuit 2 and preliminarily set. Thus, the error amplification circuit 1 compares the reference voltage Vref with the output voltage VO divided by the feedback resistors FR1, FR2, amplifies an error which is the difference between Vref and VO, and outputs the amplified value as an error voltage Verr.

(21) The valley detection circuit II is supplied with the output voltage VC of the coil current emulation circuit 4 which is similar to the coil current IL flowing through a coil L; the error voltage Verr, and the reference voltage Vref. Based on these voltages, i.e., output voltage VC, error voltage Verr, and reference voltage Vref, the valley detection circuit II detects a valley where the coil current IL is minimal, to generate a valley detection signal Comp_out.

(22) The valley detection circuit II in the present embodiment is composed of the summing circuit 3 and the comparison circuit 5. In the summing circuit 3, the output voltage VC similar to the coil current IL is added to the error voltage Verr, which is the output of the error amplification circuit 1, to generate an addition output voltage Vadd. The output voltage VC is generated in the coil current emulation circuit 4, as will be described in detail later through a configuration for its generation.

(23) A non-inverting input terminal of the comparison circuit 5 receives an input of the reference voltage Vref which is the output of the reference voltage generation circuit 2, while an inverting input terminal of the comparison circuit 5 receives an input of the addition output voltage Vadd which is the output of the summing circuit 3. As a result, the comparison circuit 5 generates the valley detection signal Comp_out, which represents a time point at which the addition output voltage Vadd of the summing circuit 3 falls short of the reference voltage Vref, namely, a time point at which the coil current IL takes the lowest value, and outputs this valley detection signal Comp_out to the switch control unit 6. The valley detection signal Comp_out is a state signal representing two states, Hi and Lo.

(24) In the present embodiment, the valley detection circuit II is formed from a combination of the summing circuit 3 and the comparison circuit 5, as described above, but this is not limiting. As long as the valley detection circuit II is configured to detect the valley, where the coil current IL is minimal, based on the output voltage VC similar to the coil current IL, the error voltage Verr, and the reference voltage Vref, there is no more special limitation. In the present embodiment, moreover, the summing circuit 3 adds the output voltage VC to the error voltage Verr, and the addition output voltage Vadd from the summing circuit 3 is compared with the reference voltage Vref, but these features are not limiting. It suffices that the valley detection circuit II is configured to generate the addition output voltage Vadd based on the error voltage Verr, the reference voltage Vref, and the output voltage VC.

(25) The switch control unit 6 controls ON/OFF of switching elements SW1, SW2, SW3, SW4 of the switching circuit 8 at a timing, which represents the passage of a preset elapsed time (to be described in detail later), in accordance with a change in the state of the valley detection signal Comp_out, based on a clock signal CLK of a constant frequency generated by the oscillation circuit 7. Consequently, the switch control unit 6 switches among a buck mode, a buck-boost mode, and a boost mode, as appropriate, to keep the output voltage VO constant. Simultaneously, the switch control unit 6 also controls the switching action of switch means S1, S2, S3 (see FIG. 8) of the coil current emulation circuit 4 to be described in detail later. The concrete contents of switching control by the switch control unit 6 will be described in detail later.

(26) The valley detection signal Comp_out, which is the output of the comparison circuit 5, is normally in the Lo state, and enters the Hi state upon detection of a valley point.

(27) The switching circuit 8 is formed by combining the four switching elements SW1 to SW4 with the coil L in the shape of H. In further detail, the switching element SW1 is connected between an input terminal IN, where an input voltage VIN being a power supply voltage, and one terminal LX1 of the coil L; the switching element SW2 is connected between a ground potential and the one terminal LX1; the switching element SW3 is connected between the ground potential and the other terminal LX2 of the coil L; and the switching element SW4 is connected between the output terminal OUT and the other terminal LX2. To the output terminal OUT, a smoothing capacitor C is connected. In the present embodiment, a capacitor with low ESR, such as a ceramic capacitor, can be used as the capacitor C.

(28) The control actions of the switch control unit 6 in respective modes, buck mode, buck-boost mode, and boost mode, will be described based on waveform charts of FIGS. 2 to 6. In FIGS. 2 to 6, (a) shows the waveform of the clock signal, (b) shows the waveform of the valley detection signal Comp_out, (c) shows the waveform of the voltage at the one terminal LX1, (d) shows the waveform of the voltage at the other terminal LX2, and (e) shows the waveform of the coil current IL. In each of the drawings, (f) to (h) show the waveforms in the respective parts of the coil current emulation circuit 4 (see FIG. 8) in the respective modes. More detailedly, in each drawing, (f) shows the waveform of a voltage at one terminal V1 (see FIG. 8), (g) shows the waveform of a voltage at the other terminal V2 (see FIG. 8), and (h) shows the waveform of the output voltage VC (see FIG. 8).

(29) <Buck Mode>

(30) FIG. 2 is the waveform chart in the buck mode. As shown in this drawing, first of all, the valley detection signal Comp_out, which is the output of the valley detecting comparison circuit 5, is reset with the use of the clock signal CLK of the oscillation circuit 7. As a result, the valley detection signal Comp_out enters the Lo state.

(31) Then, the one terminal LX1 of the coil L is switched from the Hi level to the Lo level (the switching element SW1 is turned OFF) at a first timing t1 of two timings preset within the switch control unit 6 in accordance with the input voltage VIN, the output voltage VO, or the reference voltage Vref. At this time, the terminal LX2 remains at the Hi level (the switching element SW4 remains ON). Since the terminal LX1 falls into the Lo level, an OFF-period in which the coil current IL gradually decreases is provided.

(32) At this time, the output voltage of the coil current emulation circuit 4 has been added to the output voltage of the error amplification circuit 1. In the valley detecting comparison circuit 5, therefore, the addition output of the summing circuit 3 based on the coil current IL is compared with the reference voltage Vref. If, as a result, the valley point where the coil current IL is minimal is detected, the output level of the valley detection signal Comp_out is switched to Hi, and latched there, to switch the one terminal LX1 to the Hi level (switch the switching element SW1 to ON). As a result, an ON-period in which the coil current IL gradually increases is provided.

(33) Then, the valley detection signal Comp_out is reset by the clock signal CLK to initiate a new cycle. Here, a second timing t2 comes earlier than the changeover of the valley detection signal Comp_out, and thus becomes ineffective. By repeating such a series of actions and working as a buck converter, the circuit of the present embodiment stabilizes the output voltage VO.

(34) <Buck-Boost Mode>

(35) FIGS. 3 to 5 are the waveform charts in the buck-boost mode. Although these drawings are all in the buck-boost mode, FIG. 3 shows a state where the input voltage VIN is higher than the output voltage VO, FIG. 4 shows a state where the input voltage VIN is equal to the output voltage VO, and FIG. 5 shows a state where the input voltage VIN is lower than the output voltage VO.

(36) In the buck-boost mode, as shown in FIGS. 3 to 5, the valley detection signal Comp_out is reset by the clock signal CLK, as in the buck mode. At the timing t1, the one terminal LX1 is switched from the Hi level to the Lo level, bringing out an OFF-period (turning the switching element SW1 OFF). As a result, the coil current IL is on the decrease. Unlike the buck mode, however, the comparison circuit 5 detects the valley point earlier than the timing t2. Thus, at the same time that the one terminal LX1 is switched to the Hi level (the switching element SW1 is turned ON), the other terminal LX2 is switched to the Lo level (the switching element SW3 is turned ON).

(37) Then, at the timing t2, the action of returning the other terminal LX2 to the Hi level is performed (the switching element SW3 is turned OFF). This action is repeated, whereby the circuit of the present embodiment is made to function as a buck-boost converter to stabilize the output voltage VO.

(38) In the present embodiment, the buck-boost action is realized by combining the buck action of switching the one terminal LX1 and the boost action of switching the other terminal LX2. In the buck-boost action, the period during which both the one terminal LX1 and the other terminal LX2 are at the Hi level is provided, whereby changes in the coil current IL due to the full-bridge action can be kept small. This feature can contribute to an improvement in the conversion efficiency of the switching power supply circuit.

(39) At the boundary between the buck mode and the buck-boost mode, the mode of action shifts owing to the presence or absence of extremely tiny pulses in the other terminal LX2. Thus, great changes in the coil current due to a mode difference do not occur, and continuity can be maintained. This can contribute to a stable action. A detailed explanation in this connection will be offered based on FIGS. 7(a) to 7 (c).

(40) FIG. 7(a) shows the same switching circuit 8 as that in the present embodiment. When the switching circuit 8 is driven with the full-bridge action of alternately repeating the ON-state of the switching elements SW1, SW3 and the ON-state of the switching elements SW2, SW4, the coil current IL increases as shown in FIG. 7(b), and its loss also increases correspondingly. In the present embodiment, therefore, a period during which the switching elements SW1, SW3 are kept in the ON-state is provided from a predetermined timing after the coil current IL exceeds a predetermined output current IO in the ON-state of the switching elements SW1, SW3 until a predetermined timing before the coil current IL falls short of the output current IO in the ON-state of the switching elements SW2, SW4, as shown in FIG. 7(c). By so doing, the coil current IL during the period of the ON-state of the switching elements SW1, SW3 can be kept down to a constant low value. As a result, losses can be decreased markedly.

(41) <Boost Mode>

(42) FIG. 6 is the waveform chart in the boost mode. After resetting of the valley detection signal Comp_out by the clock signal CLK, the valley detection signal Comp_out changes to Hi earlier than the timing t1, so that the other terminal LX2 is switched to Lo (the switching element SW3 is turned ON). This period is an ON-period during which the coil current IL gradually increases. Then, at the timing t2, the other terminal LX2 is switched to the Hi level (the switching element SW3 is switched to OFF), bringing out an OFF-period. Here, the timing t1 comes later than the changeover of the valley detection signal Comp_out, namely, the time point of valley detection in the coil current IL, and thus becomes ineffective. By repeating such actions, the circuit of the present embodiment works as a boost converter to stabilize the output voltage.

(43) Because of the above-described actions, the switching power supply circuit according to the present embodiment works as a buck-boost switching regulator. Particularly when the load abruptly becomes heavy in the boost mode, leading to a fall in the output voltage, detection of the valley detection signal Comp_out occurs at an earlier timing. As a result, the ON-period is prolonged to increase the coil current IL and return the output voltage VO rapidly. When the load suddenly becomes heavy in the buck-boost mode or the buck mode, leading to a fall in the output voltage VO, moreover, detection of the valley detection signal Comp_out similarly occurs at an earlier timing. If this detection occurs earlier than the timing t1, the circuit of the present embodiment works in the boost mode, and thus acts in a direction in which the output is increased more rapidly. This means that the switching power supply circuit according to the present embodiment exhibits a high effect of stabilizing the output in the presence of a sudden change in the load.

(44) Next, detection of the coil current IL will be described. If the coil current IL is detected using a sense resistor, problems as described in the aforementioned paragraph [0009] are posed. In the present embodiment, therefore, the output voltage VC similar to the coil current IL is generated by the coil current emulation circuit 4, and this output voltage VC is utilized to obtain information on the predetermined coil current IL.

(45) It is to be noted here that the switching power supply circuit according to the present embodiment allows the switching circuit 8 constituting the H-shaped bridge to perform the predetermined switching action and work in all of the buck, boost and buck-boost modes. If an integration circuit is merely connected between the one terminal LX1 and the other terminal LX2 of the switching circuit 8, therefore, the terminals LX1, LX2 both have nodes switching. In this situation, the resulting waveform is not similar to that of the coil current IL.

(46) In the present embodiment, it is therefore necessary to fix one end of a CR integration circuit, and apply a voltage in proportional relationship with a potential difference between both ends of the coil L as a potential difference between both ends of the CR integration circuit. In consideration of this necessity, the coil current emulation circuit 4 is configured in the present embodiment. Its concrete configuration will be described below.

(47) As shown in FIG. 8, the coil current emulation circuit 4 in the present embodiment has a CR integration circuit 9 composed of a capacitor C1 and a resistor R1 connected in series, and has a portion between the capacitor C1 and the resistor R1 as an output terminal where the output voltage VC similar to the coil current IL is generated.

(48) One of three voltages is applied to one terminal V1 of the CR integration circuit 9 by the selection of switch means S1, S2, S3, whereas a voltage (AVO) proportional to the output voltage VO (see FIG. 1; the same applies hereinafter) is applied to the other terminal V2 of the CR integration circuit. The three voltages are a voltage (AVIN) proportional to the input voltage VIN (see FIG. 1; the same applies hereinafter), the ground voltage, and a voltage (A(VIN+VO)) proportional to the sum of the input voltage VIN and the output voltage VO.

(49) When, in the coil current emulation circuit 4, the one terminal LX1 (see FIG. 1; the same applies hereinafter) and the other terminal LX2 (see FIG. 1; the same applies hereinafter) of the switching circuit 8 (see FIG. 1; the same applies hereinafter) are both at the Hi level, the switch means S1 is turned ON, whereby the voltage (AVIN) proportional to the input voltage VIN is applied to one end of the integration circuit 9. When the one terminal LX1 is at the Lo level and the other terminal LX2 is at the Hi level, the switch means S2 is turned ON to apply the GND voltage to the one end of the integration circuit 9. Furthermore, when the one terminal LX1 is at the Hi level and the other terminal LX2 is at the Lo level, the switch means S3 is turned ON, whereby the voltage (A(VIN+VO)) proportional to the sum of the input voltage VIN and the output voltage VO is applied to the one end of the integration circuit 9. The proportionality coefficient A is set at the same value.

(50) The respective switch means S1 to S3 of the coil current emulation circuit 4 are subjected to ON/OFF control by the control signal from the switch control unit 6 (see FIG. 1; the same applies hereinafter) in accordance with the states of the one terminal LX1 and the other terminal LX2 of the coil 1.

(51) Assume that the voltage at the one end of the resistor R1 is V1, the voltage at the other end of the capacitor C1 is V2, and the switching cycle is sufficiently shorter than the time constant of the CR integration circuit 9. In this case, the potential difference VC between both ends of the capacitor C1 is represented by Equation (1):

(52) $\begin{array}{cc}\left[\mathrm{Mathematical}1\right]& \\ \mathrm{VC}=\frac{V1-V2}{R1}\frac{1}{C1}t& \left(1\right)\end{array}$

(53) Likewise, the coil current iL is represented by Equation (2):

(54) $\begin{array}{cc}\left[\mathrm{Mathematical}2\right]& \\ \mathrm{iL}=\frac{\mathrm{VLX}1-\mathrm{VLX}2}{L}t& \left(2\right)\end{array}$

(55) Concretely, when the one terminal LX1 and the other terminal LX2 are both at the Hi level, the switch means S1 is turned ON. Thus, the potential difference VC is represented by Equation (3), and the coil current iL is represented by Equation (4).

(56) $\begin{array}{cc}\left[\mathrm{Mathematical}3\right]& \\ \mathrm{VC}=\frac{A\mathrm{VIN}-A\mathrm{VO}}{R1}\frac{1}{C1}t& \left(3\right)\\ \mathrm{iL}=\frac{\mathrm{VLX}1-\mathrm{VLX}2}{L}t& \left(4\right)\end{array}$

(57) When the one terminal LX1 is at the Lo level, and the other terminal LX2 is at the Hi level, the switch means S2 is turned ON. Assuming here that the Lo level is 0V, the potential difference VC is represented by Equation (5) and the coil current iL is represented by Equation (6).

(58) $\begin{array}{cc}\left[\mathrm{Mathematical}4\right]& \\ \mathrm{VC}=\frac{-A\mathrm{VO}}{R1}\frac{1}{C1}t& \left(5\right)\\ \mathrm{iL}=\frac{-\mathrm{VLX}2}{L}t& \left(6\right)\end{array}$

(59) When the one terminal LX1 is at the Hi level, and the other terminal LX2 is at the Lo level, the switch means S3 is turned ON. Assuming here that the Lo level is 0V, the potential difference VC is represented by Equation (7) and the coil current iL is represented by Equation (8).

(60) $\begin{array}{cc}\left[\mathrm{Mathematical}5\right]& \\ \mathrm{VC}=\frac{A\left(\mathrm{VIN}+\mathrm{VO}\right)-A\mathrm{VO}}{R1}\frac{1}{C1}t=\frac{A\mathrm{VIN}}{R1}\frac{1}{C1}t& \left(7\right)\\ \mathrm{iL}=\frac{\mathrm{VLX}1}{L}t& \left(8\right)\end{array}$

(61) In the above-mentioned coil current emulation circuit 4, the Hi level of the one terminal LX1 is nearly equal to the input voltage VIN, while the Hi level of the other terminal LX2 is nearly equal to the output voltage VO. Moreover, the proportionality coefficient A, the resistance value of the resistor R1, the capacity of the capacitor C1, and the inductance of the coil L are constants. Hence, it is seen that the potential difference VC similar to the coil current iL is obtained from the output terminal VC of the coil current emulation circuit 4.

(62) <Second Embodiment>

(63) FIG. 9 is a block diagram showing the switching power supply circuit according to a second embodiment of the present invention. This switching power supply circuit is an example on the peak detection system. In the present embodiment, the same parts as those in the first embodiment are assigned the same numerals or symbols as those in the first embodiment, and duplicate explanations are omitted.

(64) As shown in FIG. 9, the switching power supply circuit according to the present embodiment has a control circuit IA, a coil current emulation circuit 4, and a switching circuit 8, as in the first embodiment. The control circuit IA performs ON/OFF control of the switching circuit 8, based on a feedback voltage, which represents an output voltage VO being a voltage of an output terminal OUT, and an output voltage VC of the coil current emulation circuit 4, to have the switching circuit 8 carry out a predetermined buck, boost or buck-boost action so that the output voltage VO generated in the output terminal OUT of the switching circuit 8 becomes a predetermined set voltage. For this purpose, the control circuit IA according to the present embodiment is equipped with an error amplification circuit 1A, a reference voltage generation circuit 2, a peak detection circuit IIA composed of a summing circuit 3 and a comparison circuit 5A, a switch control unit 6A, and an oscillation circuit 7.

(65) The switching power supply circuit according to the present embodiment is on the peak detection system. Thus, its control circuit IA is somewhat different from the control circuit I of the first embodiment owing to a difference in system between the valley detection system and the peak detection system. That is, signals supplied to a non-inverting input terminal and an inverting input terminal of each of the error amplification circuit 1A and the comparison circuit 5A of the peak detection circuit IIA are opposite to those in the first embodiment.

(66) That is, the output voltage VO given as a feedback is divided by feedback resistors FR1, FR2, and inputted to the inverting input terminal of the error amplification circuit 1A. On the other hand, the non-inverting input terminal of the error amplification circuit 1A receives an input of a reference voltage Vref which has been generated by the reference voltage generation circuit 2 and preliminarily set. Thus, the error amplification circuit 1A compares the reference voltage Vref with the output voltage VO divided by the feedback resistors FR1, FR2, amplifies an error which is the difference between Vref and VO, and outputs the amplified value as an error voltage Verr.

(67) The peak detection circuit IIA is supplied with the output voltage VC of the coil current emulation circuit 4 which is similar to a coil current IL flowing through a coil L; the error voltage Verr, and the reference voltage Vref. Based on the output voltage VC, the error voltage Verr, and the reference voltage Vref, the peak detection circuit IIA detects a peak where the coil current IL is maximal, to generate a peak detection signal Comp_out.

(68) The peak detection circuit IIA in the present embodiment is composed of the summing circuit 3 and the comparison circuit 5A. In the summing circuit 3, the output voltage VC similar to the coil current IL is added to the error voltage Verr, which is the output of the error amplification circuit 1A, to generate an addition output voltage Vadd. The output voltage VC is generated in the same coil current emulation circuit 4 as that in the first embodiment.

(69) In the present embodiment, the reference voltage Vref, which is the output of the reference voltage generation circuit 2, is inputted to the inverting input terminal of the comparison circuit 5A. At the same time, the addition output voltage Vadd, which is the output of the summing circuit 3, inputted to the non-inverting input terminal of the comparison circuit 5A. As a result, the comparison circuit 5A generates the peak detection signal Comp_out, which represents a time point at which the addition output voltage Vadd of the summing circuit 3 exceeds the reference voltage Vref, namely, a time point at which the coil current IL takes the highest value; and outputs this peak detection signal Comp_out to the switch control unit 6A. The peak detection signal Comp_out is a state signal representing two states, Hi and Lo.

(70) In the present embodiment, the peak detection circuit IIA is formed from a combination of the summing circuit 3 and the comparison circuit 5A, as described above, but this is not limiting. As long as the peak detection circuit IIA is configured to detect the peak, where the coil current IL is maximal, based on the output voltage VC similar to the coil current IL, the error voltage Verr, and the reference voltage Vref, there is no more special limitation. In the present embodiment, moreover, the summing circuit 3 adds the output voltage VC to the error voltage Verr, and the addition output voltage Vadd from the summing circuit 3 is compared with the reference voltage Vref, but these features are not limiting. It suffices that the peak detection circuit IIA is configured to generate the addition output voltage Vadd based on the error voltage Verr, the reference voltage Vref, and the output voltage VC.

(71) The switch control unit 6A controls ON/OFF of switching elements SW1, SW2, SW3, SW4 of the switching circuit 8 in accordance with a timing, which represents the passage of a preset elapsed time (to be described in detail later), and a change in the state of the peak detection signal Comp_out, based on a clock signal CLK of a constant frequency generated by the oscillation circuit 7. By so doing, the switch control unit 6A exercises control to switch among a buck mode, a buck-boost mode, and a boost mode, as appropriate, thereby keeping the output voltage VO constant. Simultaneously, the switch control unit 6A also controls the switching action of switch means S1, S2, S3 (see FIG. 8) of the coil current emulation circuit 4 to be described in detail later. The concrete contents of switching control by the switch control unit 6A will be described in detail later.

(72) The peak detection signal Comp_out, which is the output of the comparison circuit 5A, is normally in the Lo state, and enters the Hi state upon detection of the peak point.

(73) The switching circuit 8 is formed by combining the four switching elements SW1 to SW4 with the coil L in the shape of H as in the first embodiment. In further detail, the switching element SW1 is connected between an input terminal IN, where an input voltage VIN being a power supply voltage is applied, and one terminal LX1 of the coil L; the switching element SW2 is connected between a ground potential and the one terminal LX1; the switching element SW3 is connected between the ground potential and the other terminal LX2 of the coil L; and the switching element SW4 is connected between the output terminal OUT and the other terminal LX2. To the output terminal OUT, a smoothing capacitor C is connected. In the present embodiment, a capacitor with low ESR, such as a ceramic capacitor, can be used as the capacitor C.

(74) The control actions of the switch control unit 6A in the respective modes, buck mode, buck-boost mode, and boost mode, will be described based on waveform charts of FIGS. 10 to 14. In FIGS. 10 to 14, (a) shows the waveform of the clock signal, (b) shows the waveform of the peak detection signal Comp_out, (c) shows the waveform of the one terminal LX1, (d) shows the waveform of the other terminal LX2, and (e) shows the waveform of the coil current IL. In each of the drawings, (f) to (h) show the waveforms in the respective parts of the coil current emulation circuit 4 (see FIG. 8) in the respective modes. More detailedly, in each drawing, (f) shows the waveform of the voltage at one terminal V1 (see FIG. 8), (g) shows the waveform of the voltage at the other terminal V2 (see FIG. 8), and (h) shows the waveform of the output voltage VC (see FIG. 8).

(75) <Buck Mode>

(76) FIG. 10 shows the waveform chart in the buck mode. As shown in this drawing, the peak detection signal Comp_out, which is the output of the peak detecting comparison circuit 5A, is reset by the clock signal CLK of the oscillation circuit 7. As a result, the peak detection signal Comp_out enters the Lo state.

(77) Then, when the peak detection signal Comp_out changes to Hi earlier than a first timing t1 of two timings preset within the switch control unit 6A in accordance with the input voltage VIN, the output voltage VO, or the reference voltage Vref, the one terminal LX1 of the coil L is switched from the Hi level to the Lo level (the switching element SW1 is turned OFF). Since, during this period, the terminal LX1 falls into the Lo level, an OFF-period in which the coil current IL gradually decreases is provided.

(78) Then, at a second timing t2, the terminal LX1 is switched to the Hi level to establish an ON-period. Here, the first timing t1 is later than the switching of the peak detection signal Comp_out, and thus becomes ineffective. During such a series of actions, the terminal LX2 is fixed at Hi. By repeating these actions, the circuit of the present embodiment works as a buck converter, stabilizing the output voltage VO.

(79) FIGS. 11 to 13 are timing charts in the buck-boost mode. Although all these drawings show the buck-boost mode, FIG. 11 shows a state where the input voltage VIN is higher than the output voltage VO, FIG. 12 shows a state where the input voltage VIN is equal to the output voltage VO, and FIG. 13 shows a state where the input voltage VIN is lower than the output voltage VO.

(80) <Buck-Boost Mode>

(81) In the buck-boost mode, as shown in FIGS. 11 to 13, the peak detection signal Comp_out is reset by the clock signal CLK, as in the buck mode. At the first timing t1, the terminal LX2 is switched from the Hi level to the Lo level, bringing out an ON-period. As a result, the coil current IL is on the increase.

(82) In this buck-boost mode, unlike the buck mode, the peak detection circuit IIA detects the peak point earlier than the second timing t2 to switch the terminal LX1 to the Lo level and the terminal LX2 to the Hi level.

(83) Then, at the second timing t2, the action of returning the terminal LX1 to the Hi level is performed. Such actions are repeated, whereby the circuit of the present embodiment is made to work as a buck-boost converter to stabilize the output voltage VO.

(84) In the present embodiment, the buck-boost action is realized by combining the buck action of switching the one terminal LX1 and the boost action of switching the other terminal LX2. In the buck-boost action, the period during which both the one terminal LX1 and the other terminal LX2 are at the Hi level is provided, whereby changes in the coil current IL due to the full-bridge action can be kept smaller, as in the first embodiment. This feature can contribute to an improvement in the conversion efficiency of the switching power supply circuit. At the boundary between the buck mode and the buck-boost mode, moreover, the mode of action shifts owing to the presence or absence of extremely tiny pulses in the other terminal LX2. Thus, great changes in the coil current due to a mode difference do not occur, and continuity can be maintained. This can contribute to a stable action. A detailed explanation in this connection will be offered based on FIGS. 15(a) to 15(c).

(85) FIG. 15(a) shows the same switching circuit 8 (see FIG. 9; the same applies hereinafter) as that in the present embodiment. When the switching circuit 8 is driven with the full-bridge action of alternately repeating the ON-state of the switching elements SW1, SW3 and the ON-state of the switching elements SW2, SW4, the coil current IL increases as shown in FIG. 15(b), and its loss also increases correspondingly. In the present embodiment, therefore, a period during which the switching elements SW1, SW4 are kept in the ON-state is provided from a predetermined timing after the coil current IL falls short of a predetermined output current IO in the ON-state of the switching elements SW2, SW4 until a predetermined timing before the coil current IL exceeds the output current IO in the ON-state of the switching elements SW1, SW3, as shown in FIG. 15(c). That is, the period during which the switching elements SW1, SW4 are in the ON-state is provided between the period during which the switching elements SW2, SW4 are in the ON-state and the period during which the switching elements SW1, SW3 are in the ON-state. By so doing, the coil current IL during the full-bridge period can be kept down to a constant low value. As a result, losses can be decreased markedly.

(86) <Boost Mode>

(87) FIG. 14 is the waveform chart in the boost mode. In this mode, as shown in the drawing, the peak detection signal Comp_out of the peak detection circuit IIA is reset by the clock signal CLK which is the output of the oscillation circuit 7. After resetting by the clock signal CLK, the terminal LX2 is switched from the Hi level to the Lo level at the first timing t1. At this time, the LX1 remains at the Hi level. Since the terminal LX2 comes to the Lo level, an ON-period during which the coil current IL gradually increases is provided.

(88) The peak detection circuit IIA detects the peak point, whereupon the output level of the peak detection signal Comp_out is switched to Hi and latched there, while the terminal LX2 is switched to the Hi level. As a result, an OFF-period in which the coil current IL gradually decreases is provided.

(89) Then, the peak detection signal Comp_out is reset by the clock signal CLK to bring about a new cycle. Here, the second timing t2 is earlier than the switching of the peak detection signal Comp_out, and thus becomes ineffective. By repeating such actions, the circuit of the present embodiment works as a buck converter to stabilize the output voltage VO.

(90) Because of the above-described actions, the switching power supply circuit according to the present embodiment works as a buck-boost switching regulator.

(91) Next, detection of the coil current IL will be described. If the coil current IL is detected using a sense resistor, problems as described in the aforementioned paragraph [0009] are posed. In the present embodiment, therefore, the output voltage VC similar to the coil current IL is generated by the coil current emulation circuit 4, and this output voltage VC is utilized to obtain information on the predetermined coil current IL. The coil current emulation circuit 4 as described here has exactly the same configuration as that in the first embodiment. Hence, explanations for it in the present embodiment are omitted.

(92) The switching power supply circuits according to the first and second embodiments described as above are on the so-called current mode control system under which the switching operation of the switching elements SW1 to SW4 is controlled based on the coil current IL. However, this is not limiting. As long as the switching circuit 8 and the coil current emulation circuit 4 are combined with the control unit performing the ON/OFF control of the switching circuit 8, there is no more special limitation. Thus, the present invention is applicable to a switching power supply circuit on a so-called voltage mode control system, or to a switching power supply circuit on a hysteresis control system. Under the voltage mode control system, basically, a feedback voltage and a reference voltage are compared and, in accordance with an error between these voltages, a PWM signal for performing switching is generated. In this case, it suffices to construct a control circuit appropriate to such tasks. Under the hysteresis control system, basically, output ripples are detected, and a control signal for performing switching is generated. Construction of a control circuit suitable for such tasks is sufficient.

EXPLANATIONS OF LETTERS OR NUMERALS

(93) I, IA Control circuit II Valley detection circuit IIA Peak detection circuit 1, 1A Error amplification circuit 2 Reference voltage generation circuit 3 Summing circuit 4 Coil current emulation circuit 5, 5A Comparison circuit 6, 6A Switch control unit 7 Oscillation circuit 8 Switching circuit 9 Integration circuit