Semiconductor layer structure

Abstract

There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising Al.sub.xGa.sub.1-xN, wherein 0≤x≤0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising Al.sub.yGa.sub.1-yN, wherein 0≤y≤0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.

Claims

1. A semiconductor layer structure comprising: a Si substrate having a top surface; a first semiconductor layer arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising AlxGa1-xN, wherein 0≤x≤0.95, the second semiconductor layer comprising at least two dislocations, each of the two dislocations propagating laterally from separate nanowire structures in an M-direction of a wurtzite crystal structure, the two dislocations being coalesced with each other; a third semiconductor layer arranged on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0≤y≤0.95; and a fourth semiconductor layer arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN.

2. The semiconductor layer structure according to claim 1, further comprising a bottom semiconductor layer, arranged intermediate to the top surface of the substrate and the first semiconductor layer, the bottom semiconductor layer comprising AlN.

3. The semiconductor layer structure according to claim 2, further comprising an intermediate semiconductor layer, arranged intermediate to the bottom semiconductor layer and the first semiconductor layer, the intermediate semiconductor layer comprising AlN.

4. The semiconductor layer structure according to claim 1, wherein the top surface of the Si substrate has a Miller index of {111}.

5. The semiconductor layer structure according to claim 1, wherein said fourth semiconductor layer has a vertical thickness in the range 1-5 nm.

6. The semiconductor layer structure according to claim 1, wherein the second semiconductor layer comprises at least two vertically arranged sublayers, wherein x for a first sublayer is greater than x for a second sublayer, wherein the second sublayer is located further from the substrate than the first sublayer.

7. A high-electron-mobility transistor device comprising: the semiconductor layer structure according to claim 1; a metallic source contact arranged directly adjacent to the second semiconductor layer; a metallic drain contact arranged directly adjacent to the second semiconductor layer, wherein the drain contact is separate from the source contact; and a metallic gate contact arranged on the fourth semiconductor layer, wherein the gate contact is arranged laterally between the source and drain contacts, and wherein the gate contact is separate from the source and drain contacts.

8. The high-electron-mobility transistor device according to claim 7, wherein the fourth semiconductor layer is arranged as a vertical fin, wherein the vertical fin is arranged directly adjacent to the third semiconductor layer, wherein the gate contact is arranged to laterally and vertically enclose the vertical fin, and wherein the vertical fin comprises p-doped GaN.

9. A method for producing a semiconductor layer structure, the method comprising: providing a Si substrate comprising a top surface; forming a first semiconductor layer on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures, arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; depositing a second semiconductor layer on the first semiconductor layer, laterally and vertically enclosing said nanowire structures, wherein the second semiconductor layer comprises AlxGa1-xN, wherein 0≤x≤0.95, the second semiconductor layer comprising at least two dislocations, each of the two dislocations propagating laterally from separate nanowire structures in an M-direction of a wurtzite crystal structure, the two dislocations being coalesced with each other; depositing a third semiconductor layer on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0≤y≤0.95; and depositing a fourth semiconductor layer on said third semiconductor layer, the fourth semiconductor layer comprising GaN.

10. The method according to claim 9, wherein forming said first semiconductor layer comprises: depositing the first semiconductor layer on the substrate; and etching the plurality of vertical nanowire structures from the first semiconductor layer.

11. The method according to claim 9, wherein forming said first semiconductor layer comprises epitaxially forming the plurality of vertical nanowire structures on the substrate.

12. The method according to claim 9, further comprising depositing a bottom semiconductor layer intermediate to providing the substrate and forming the first semiconductor layer, the bottom semiconductor layer comprising AlN.

13. The method according to claim 12, further comprising depositing an intermediate semiconductor layer intermediate to depositing the bottom semiconductor layer and forming the first semiconductor layer, the intermediate semiconductor layer comprising AlN.

14. The method according to claim 9, wherein forming said second semiconductor layer comprises: forming a first sublayer on the first semiconductor layer; and forming a second sublayer on the first sublayer, wherein x for the first sublayer is greater than x for the second sublayer.

15. A method for producing a high-electron-mobility transistor device, the method comprising: the steps of the method for producing a semiconductor layer structure according to claim 9; forming at least two trenches through the third and fourth semiconductor layers by etching away portions of said third and fourth semiconductor layers; depositing a first metallic layer into the trenches and on the second semiconductor layer; forming a metallic source contact and a metallic drain contact, in the trenches, by etching away portions of the first metallic layer; forming an oxide layer on the source and drain contacts; forming a gate trench through the oxide layer, between and separate from the at least two trenches through the third and fourth semiconductor layers, by etching away a portion of the oxide layer; depositing a second metallic layer into the gate trench; and forming a metallic gate contact, in the gate trench, by etching away portions of the second metallic layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other aspects of the present invention will, in the following, be described in more detail with reference to appended figures. The figures should not be considered limiting; instead they should be considered for explaining and understanding purposes.

(2) As illustrated in the figures, the sizes of layers and regions may be exaggerated for illustrative purposes and, thus, are provided to illustrate the general structures. Like reference numerals refer to like elements throughout.

(3) Cross section figures may primarily be considered as schematic illustrations. Devices, layers, and/or structures therein should not be considered to scale relative to each other. Furthermore, the cross sections may be considered as viewing the devices, layers, and/or structures from a lateral point of view.

(4) Flowchart boxes with dashed borders may be considered as optional and/or additional steps featured for some variations of the methods.

(5) FIG. 1 illustrates a cross section of a semiconductor layer structure according to the present invention.

(6) FIG. 2 illustrates a cross section of a semiconductor layer structure variation.

(7) FIG. 3 illustrates a cross section of a semiconductor layer structure variation.

(8) FIG. 4 illustrates a cross section of a semiconductor layer structure variation.

(9) FIG. 5 illustrates a cross section of a HEMT according to the present invention.

(10) FIG. 6 illustrates a cross section of a HEMT variation.

(11) FIG. 7 shows a flowchart of a method for producing a semiconductor layer structure.

(12) FIG. 8 shows a flowchart containing further details about steps for producing a semiconductor layer structure.

(13) FIG. 9 shows a flowchart containing further details about steps for producing a semiconductor layer structure.

(14) FIGS. 10a-g illustrates cross sections of a semiconductor layer structure during different chronological states of its production.

(15) FIG. 11 shows a flowchart of a method for producing a HEMT.

(16) FIGS. 12a-i illustrates cross sections of a HEMT during different chronological states of its production.

(17) FIG. 13 shows a top view of HEMT contacts.

DETAILED DESCRIPTION

(18) The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which currently preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided for thoroughness and completeness, and to fully convey the scope of the invention to the skilled person.

(19) In FIG. 1 there is provided a cross sectional schematic for a semiconductor layer structure 100 comprising:

(20) a Si substrate 102 having a top surface 104;

(21) a first semiconductor layer 110 arranged on said substrate 102, the first semiconductor layer 110 comprising a plurality of vertical nanowire structures 112 arranged perpendicularly to said top surface 104 of said substrate 102, the first semiconductor layer 110 comprising AlN;

(22) a second semiconductor layer 120 arranged on said first semiconductor layer 110 laterally and vertically enclosing said nanowire structures 112, the second semiconductor layer 120 comprising Al.sub.xGa.sub.1-xN, wherein 0≤x≤0.95;

(23) a third semiconductor layer 130 arranged on said second semiconductor layer 120, the third semiconductor layer 130 comprising Al.sub.yGa.sub.1-yN, wherein 0≤y≤0.95; and

(24) a fourth semiconductor layer 140 arranged on said third semiconductor layer 130, the fourth semiconductor layer 140 comprising GaN.

(25) The top surface 104 of the Si substrate 102 may have a Miller index of {111}. The Si substrate may be considered to have the face-centered diamond-cubic crystal structure.

(26) The Si substrate 102 and its top surface 104 may be substantially planar. The Si substrate 102 may have a vertical thickness in the range 100-1000 μm. The Si substrate 102 may more preferably have a vertical thickness in the range 275-525 μm. In general, and if not explicitly stated otherwise, thickness will herein refer to vertical thickness.

(27) The Si substrate 102 may be in the form of a substantially circular wafer preferably with a diameter larger than or equal to 1″. The wafer may more preferably have a diameter in the range 2-12″ and most preferably a diameter in the range 2-4″.

(28) The first semiconductor layer 110 may preferably have a thickness in the range 100-500 nm and more preferably a thickness in the range 200-300 nm.

(29) The vertical nanowire structures 112 of the first semiconductor layer 110 may preferably have a vertical length in the range 50-500 nm and more preferably a vertical length in the range 150-250 nm.

(30) The vertical nanowire structures 112 may preferably have a substantially circular or hexagonal lateral cross section. The vertical nanowire structures 112 may preferably have a lateral diameter in the range 5-50 nm and more preferably a lateral diameter in the range 10-30 nm.

(31) The plurality of vertical nanowires 112 may be arranged in a repeating array pattern, as seen from the vertical direction. The repeating array pattern may be a hexagonal pattern, wherein each vertical nanowire structure 112 has six equidistant closest other vertical nanowire structures 112. The repeating array pattern may alternatively be a square pattern, wherein each vertical nanowire structure 112 has four equidistant closest other vertical nanowire structures 112. The distance to a closest other vertical nanowire structure 112 may preferably be in the range 10-500 nm. The closest distance may more preferably be in the range 50-200 nm. This closest distance may alternatively be understood as the spacing between vertical nanowire structures 112.

(32) The second semiconductor layer 120 may preferably have a thickness in the range 100-500 nm and more preferably a thickness in the range 200-300 nm. The second semiconductor layer 120 may be considered to laterally enclose, encapsulate, or encompass the vertical nanowire structures 112, i.e. filling in the space between the vertical nanowire structures 112. The second semiconductor layer 120 may further be considered to vertically enclose or encapsulate the vertical nanowire structures 112, i.e. extending vertically above and covering top portions of the vertical nanowire structures.

(33) The third and fourth semiconductor layers 130, 140 may be considered as relatively thin epilayers, i.e. epitaxially formed thin-film layers. The third semiconductor layer 130 may preferably have a thickness in the range 1-100 nm. The fourth semiconductor layer 140 may have a vertical thickness in the range 1-5 nm.

(34) Generally, for all nitride-based layers and structures, e.g. the first to the fourth semiconductor layers 110, 120, 130, 140 as well as the vertical nanowire structures 112, the material may be considered to have the crystal structure wurtzite. The crystal structure may be aligned so that the C-plane, i.e. a plane with the Miller index {0001}, aligns with or is parallel with the top surface 104 of the Si substrate 102. The wurtzite crystal structure may additionally be considered for all further nitride-based layers and structures disclosed herein. A preferred crystal orientation for GaN thin-films, e.g. the fourth semiconductor layer 140, may correspond to the wurtzite C-direction in such a way that a perpendicular C-plane may be obtained at an external surface of the thin-film. Such a C-plane surface may be considered an advantageous base for processing or fabricating many types of devices such as e.g. HEMTs and light-emitting diodes, LEDs,

(35) FIG. 2 shows the semiconductor layer structure 100 further comprising a bottom semiconductor layer 210, arranged intermediate to the top surface 104 of the substrate 102 and the first semiconductor layer 110, the bottom semiconductor 210 layer comprising AlN.

(36) The bottom semiconductor layer 210 may preferably have a thickness in the range 10-100 nm.

(37) FIG. 3 shows the semiconductor layer structure 100 further comprising an intermediate semiconductor layer 220, arranged intermediately to the bottom semiconductor layer 210 and the first semiconductor layer 110, the intermediate semiconductor layer 220 comprising AlN.

(38) The intermediate semiconductor layer 220 may preferably have a thickness in the range 10-100 nm.

(39) FIG. 4 shows the second semiconductor 120 layer comprising at least two vertically arranged sublayers 121, 122, wherein x for a first sublayer 121 is greater than x for a second sublayer 122, wherein the second sublayer 122 is located further from the substrate than the first sublayer 121.

(40) One exemplary second semiconductor layer 120 may comprise three vertically arranged sublayers. A bottommost sublayer, i.e. the sublayer closest to the substrate 102, may feature x=0.9. A topmost sublayer, i.e. the sublayer furthest from the substrate 102, may feature x=0.2. An intermediate sublayer, i.e. the sublayer between the topmost and bottommost sublayers, may feature x=0.5.

(41) The sublayers 121, 122 may each have a thickness in the range 20-250 nm.

(42) In FIG. 5 there is provided a cross sectional schematic for a high-electron-mobility transistor device, 300 comprising:

(43) the semiconductor layer structure 100;

(44) a metallic source contact 301 arranged directly adjacent on the second semiconductor layer 120;

(45) a metallic drain contact 303 arranged directly adjacent on the second semiconductor layer 120, wherein the drain contact 303 is separate from the source contact 301; and

(46) a metallic gate contact 305 arranged on the fourth semiconductor layer 140, wherein the gate contact 305 is arranged laterally between the source and drain contacts 301, 303, and wherein the gate contact 305 is separate from the source and drain contacts 301, 303.

(47) The source and drain contacts 301, 303 may comprise metal materials such as Ti, Al, Cu, Ni, and/or Au. The source and drain contacts 301, 303 may comprise compounds or alloys such as e.g. AlCu.

(48) The gate contact 305 may, in addition to the materials mentioned for the source and drain contacts 301, 303, comprise Pd and/or Au. As for the source and drain contacts 301, 303, compounds and alloys are also options for the gate contact 305.

(49) The HEMT 300 may further comprise an oxide layer 310 arranged on the semiconductor layers 130, 140. The oxide layer 310 may be configured to feature a low relative permittivity material to reduce parasitic capacitances between the source, drain, and gate contacts 301, 303, 305. The oxide layer may comprise SiO.sub.2, or other types of Si-based oxides.

(50) The third semiconductor layer, comprising Al.sub.yGa.sub.1-yN, may be considered a barrier layer of the HEMT 300.

(51) FIG. 6 shows the fourth semiconductor layer 140 being arranged as a vertical fin 307, wherein the vertical fin 307 is arranged directly adjacent on the third semiconductor layer 130, wherein the gate contact 305 is arranged to laterally and vertically enclose the vertical fin 307, and wherein the vertical fin 307 comprises p-doped GaN. The vertical fin 307 may be etched out of the fourth semiconductor layer 140. The vertical fin 307 may be understood as a laterally elongated fin or alternatively as a laterally shorter mesa structure.

(52) Impurity atoms, for p-doping of GaN, may comprise elements from the second group of the periodic table of elements e.g. Mg. Impurities may be activated through e.g. thermal processing/annealing or electron bombardment/irradiation. The fourth semiconductor layer 140 may further not form a continuous layer between the source, drain and gate contacts 301, 303, 305, as in the case of FIG. 5.

(53) In FIG. 7 there is provided a flowchart for a method for producing a semiconductor layer structure 100, the method comprising:

(54) providing S4001 a Si substrate 102 comprising a top surface 104;

(55) forming S4003 a first semiconductor layer 110 on said substrate 102, the first semiconductor layer 110 comprising a plurality of vertical nanowire structures 112, arranged perpendicularly to said top surface 104 of said substrate 102, the first semiconductor layer 110 comprising AlN;

(56) depositing S4005 a second semiconductor layer 120 on the substrate structure 102, laterally and vertically enclosing said nanowire structures 112, wherein the second semiconductor layer 120 comprises Al.sub.xGa.sub.1-xN, wherein 0≤x≤0.95;

(57) depositing S4007 a third semiconductor layer 130 on said second semiconductor layer 120, the third semiconductor layer 130 comprising Al.sub.yGa.sub.1-yN, wherein 0≤y≤0.95; and

(58) depositing S4009 a fourth semiconductor layer 140 on said third semiconductor layer 130, the fourth semiconductor layer 140 comprising GaN.

(59) The Si substrate 102 may be formed using conventional Si wafer production methods including e.g. the aforementioned Czochralski process.

(60) The first semiconductor layer 110 may be formed S4003 using physical vapor deposition, PVD, chemical vapor deposition, CVD, plasma-enhanced chemical vapor deposition, PECVD, metalorganic chemical vapor deposition, MOCVD, metalorganic vapor-phase epitaxy, MOVPE, sputtering, or similar methods.

(61) The vertical nanowire structures 112 of the first semiconductor layer 110 may be formed using etching methods such as dry etching, wet etching, chemical etching, plasma etching, reactive ion etching, etc. The etching may be performed subsequent to a patterning step aiming to define the nanowire structures 112. The vertical nanowire structures 112 may additionally be formed using epitaxy methods such as MOCVD or MOVPE, both essentially referring to the same technique. Selective area growth, based on the preceding patterning, may be employed for the nanowire structures 112.

(62) Patterning, pattern transferring, or defining of the nanowire structures 112 may be lithography based. Optical lithography, such as ultraviolet, UV, lithography may be employed. Electron beam lithography, EBL, or nanoimprint lithography, NIL, as well as various other similar lithography methods may be employed. As an alternative, patterning may comprise just etching, or depositing, through a solid mask aligned onto, or close to, the surface of the layer or structure to be etched or deposited onto.

(63) FIG. 7 also shows how the method may further comprise depositing S5007 a bottom semiconductor layer 210 intermediate to providing S4001 the substrate 102 and forming S4003 the first semiconductor layer 110, the bottom semiconductor layer 210 comprising AlN.

(64) The bottom layer 210 may be deposited S5007 using similar methods as the first semiconductor layer 110. The bottom layer 120 may preferably be deposited using PVD.

(65) FIG. 7 also shows how the method may further comprise depositing S5009 an intermediate semiconductor layer 220 intermediate to depositing S5007 the bottom semiconductor layer 210 and forming S4003 the first semiconductor layer 110, the intermediate semiconductor layer 220 comprising AlN.

(66) The intermediate layer 220 may be deposited S5009 using similar methods as the first semiconductor layer 110. The intermediate layer 220 may preferably be deposited using high temperature MOCVD/MOVPE.

(67) The second, third, and fourth semiconductor layers 120, 130, 140 may be deposited S4005, S4007, S4009 using MOCVD/MOVPE. Different precursor gas pressure and temperatures may be used to create solid crystal material of different compositions ranging from AlN, through various compositions of AlGaN, to GaN. It is preferred to use a temperature equal or higher than 1000° C. for the GaN MOCVD/MOVPE.

(68) Precursor gases may comprise trimethylaluminium, TMAI, triethylaluminium, TEAI, trimethylgallium, TMGa, triethylgallium, TEGa, phenyl hydrazine, dimethylhydrazine, DMHy, tertiarybutylamine, TBAm, ammonia, NH.sub.3.

(69) The step of depositing S4005 a second semiconductor layer 120 may be understood as epitaxially growing a shell, or shells, laterally or radially out, from the vertical nanowire structures 112, in the M-direction of the wurtzite crystal of the vertical nanowire structures 112. The shell, or shells, from different vertical nanowire structures 112 may coalesce to form a common thin-film being the second semiconductor layer 120.

(70) FIG. 8 shows how forming said plurality of vertical nanowire structures 112 of said first semiconductor layer 110 may comprise:

(71) depositing S5001 the first semiconductor layer 110 on the substrate 102; and

(72) etching S5003 the plurality of vertical nanowire structures 112 from the first semiconductor layer 110.

(73) The etching S5003 may be a selective etching procedure, e.g. based on a preceding patterning step. The etching S5003 may produce the vertical nanowire structures 112. The etching S5003 may be e.g. a chlorine-based plasma etching procedure.

(74) FIG. 8 further shows how forming said plurality of vertical nanowire structures 112 may comprise epitaxially, e.g. through selective area growth MOCVD/MOVPE, forming S5005 the plurality of vertical nanowire structures 112 on the substrate 102.

(75) FIG. 9 shows how forming said second semiconductor layer 120 may comprise:

(76) forming S5011 a first sublayer 121 on the first semiconductor layer 110; and

(77) forming S5013 a second sublayer 122 on the first sublayer 121, wherein x for the first sublayer 121 is greater than x for the second sublayer 122.

(78) Differences in composition of the sublayers 121, 122 may be achieved by gradually changing parameters such as temperature and precursor gas pressure.

(79) FIGS. 10a-g show cross sectional views at different chronological stages of the method for producing the semiconductor layer structure.

(80) FIG. 10a shows just the provided S4001 substrate 102, with its top surface 104.

(81) FIG. 10b shows a bottom semiconductor layer 210 deposited S5007 onto the top surface 104 of the substrate 102.

(82) FIG. 10c shows an intermediate semiconductor layer 220 deposited S5009 onto the bottom semiconductor layer 210.

(83) FIG. 10d shows the first semiconductor layer 110, including the vertical nanowires structures 112, formed S4003 onto the intermediate semiconductor layer 220. Note that the first semiconductor layer 110 may be formed S4003 directly onto the top surface 104 of the substrate 102.

(84) FIG. 10e shows the second semiconductor layer 120 deposited S4005 onto the first semiconductor layer 110, laterally and vertically enclosing the nanowire structures 112.

(85) FIG. 10f shows the third semiconductor layer 130 deposited S4007 onto the second semiconductor layer 120.

(86) FIG. 10g shows a completed semiconductor layer structure 100 with the fourth semiconductor layer 140 deposited S4009 onto the third semiconductor layer 130.

(87) In FIG. 11 there is provided a flowchart for a method for producing a high-electron-mobility transistor device 300, the method comprising:

(88) the steps S4001-S4009, and optionally also steps S5001-S5013, of the method for producing a semiconductor layer structure 100;

(89) forming S6001 at least two trenches 702 through the third and fourth semiconductor layers 130, 140 by etching away portions of said third and fourth semiconductor layers 130, 140;

(90) depositing S6003 a first metallic layer 704 into the trenches 702 and on the second semiconductor layer 120;

(91) forming S6005 a metallic source contact 301 and a metallic drain contact 303, in the trenches 702, by etching away portions of the first metallic layer 704;

(92) forming S6007 an oxide layer 310 on the source and drain contacts 301, 303;

(93) forming S6009 a gate trench 708 through the oxide layer 310, between and separate from the at least two trenches 702 through the third and fourth semiconductor layers 130, 140, by etching away a portion of the oxide layer 310;

(94) depositing S6011 a second metallic layer 710 into the gate trench 708; and

(95) forming S6013 a metallic gate contact 305, in the gate trench 708, by etching away portions of the second metallic layer 710.

(96) The forming S6001 of the at least two trenches 702, as well as the forming S6009 of the gate trench 708 may comprise selective etching based on patterning, as described in the above. Patterning may be performed similar for all trenches 702, 708 but etching may need to be customized according to the material to be etched. E.g. a plasma-based etching may be used for forming S6001 the at least two trenches 702 through the third and fourth semiconductor layers 130, 140. An oxide etch method, e.g. hydrofluoric acid, HF, wet etch, may be used for forming S6009 the gate trench 708 through the oxide layer 310. The trenches 702, 708 may be understood as laterally elongated trenches or alternatively as laterally shorter pits.

(97) The depositing S6003, S6011 of first and second metallic layers 704, 708 may be performed by e.g. sputtering or metal evaporation. When deposited, the first metallic layer 704 may comprise the same materials as described in the above in relation to the metallic source and drain contacts 301, 303. When deposited, the second metallic layer 708 may comprise the same materials as described in the above in relation to the metallic gate contact 305.

(98) The forming S6005, S6013 of the source, drain, and gate contacts 301, 303, 305 may be performed by etching the first and second metallic layers 704, 708 using a metal etch method suitable for the metallic material to be etched. Once again, etching may be mediated through a patterning step to define areas of the layer to remove. Such a patterning step may be performed in accordance with above mentioned methods of patterning.

(99) The forming S6007 of the oxide layer 310 may comprise deposition such an oxide layer 310 through deposition methods described in the above. E.g. CVD, PECVD and sputtering may be utilized for forming the oxide layer 310.

(100) FIGS. 12a-g show cross sectional views at different chronological stages of the method for producing the HEMT 300.

(101) FIG. 12a shows a semiconductor layer structure 100, being the base for a following steps of producing the HEMT 300.

(102) FIG. 12b shows the at least two trenches 702 formed S6001 through the third and fourth semiconductor layers 130, 140.

(103) FIG. 12c shows the first metallic layer 704 deposited S6003 into the trenches 702, onto the second semiconductor layer 120.

(104) FIG. 12d shows the metallic source and drain contacts 301, 303 formed S6005 in the trenches 702 by selective removal of portions of the first metallic layer 704 that initially physically connected the source and drain contacts 301, 303.

(105) FIG. 12e shows the oxide layer 301 formed S6007 onto source and drain contacts 301, 303 and the semiconductor layers.

(106) FIG. 12f shows the gate trench 708 formed S6009 through the oxide layer 310, laterally between the source and drain contacts 301, 303.

(107) FIG. 12g shows the second metallic layer 710 deposited S6011 into the gate trench 708, onto the fourth semiconductor layer 140.

(108) FIG. 12h the metallic gate contacts 305 formed S60013 in the gate trench 708 by selective removal of portions of the second metallic layer 710. The HEMT 300 may now be considered complete.

(109) FIG. 12i shows an additional step of planarizing the top portions of the HEMT 300. This may be done in order to simplify access to the source and drain contacts 301, 303 and reduce interconnect complexity. Chemical mechanical polishing, CMP, may be utilized for such a planarizing step.

(110) Additionally, variations to the disclosed embodiments can be understood and effected by the skilled person in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

(111) FIG. 13 shows a top view of a HEMT 300 contact layout. The source contact 301, the drain contact 303, and the gate contact 305, are herein arranged in a multi-finger layout. The source contact 301 has three fingers and the drain contact has two fingers. The gate contact 305 is shown to meander between the source and drain contacts 301, 303. A HEMT device cross section, as e.g. the one shown in FIG. 5, may be understood to correspond with the cross section 802 indicated in FIG. 13.

(112) The layout furthers efficient area spacing of devices and evenly distributed electric currents. The layout allows for higher currents due to a longer effective channel width. The effective channel width may be understood as the total number of fingers (both source and drain) minus one, all multiplied with the length of one finger. The layout may also reduce the gate resistance and prevent a low-pass filter to form with the gate channel capacitance. Hence HEMT switching speed is improved by such a layout.