SIGNAL PROCESSING UNIT FOR INDUCTIVE POSITION SENSOR

Abstract

A signal processing unit for an inductive position sensor is provided. The inductive position sensor provides a first position signal and a second phase-shifted position signal, such as, a sine position signal and a cosine position signal. The signal processing unit has an integrator for integrating an integer number of periods of the first position signal respectively an integer number of periods of the second phase-shifted position signal. The position of the moving target of the position sensor is calculated from the integrated first position signal and the integrated second phase-shifted position signal.

Claims

1. A signal processing unit for an inductive position sensor, wherein the inductive position sensor provides a first position signal and a second phase-shifted position signal, the signal processing unit comprising: a first input for the first position signal and a second input for the second position signal; an output for providing an AC excitation signal to the inductive position sensor; an oscillator connected to the output for generating the AC excitation signal; and a signal processor for calculating the position of a moving target of the position sensor from the first position signal and the second position signal; wherein: the signal processing unit comprises at least one integrator for integrating an integer number of periods of the first position signal respectively an integer number of periods of the second position signal; and wherein the signal processor calculates the position of the moving target of the position sensor from the integrated first position signal and the integrated second position signal.

2. The signal processing unit according to claim 1, wherein: the first position signal and the second phase-shifted position signal are analog signals; and the signal processing unit comprises an analog-to-digital converter for converting the first position signal and the second position signal to a corresponding first digital position signal and to a corresponding second phase-shifted digital position signal.

3. The signal processing unit according to claim 1, further comprising an oscillator controller for keeping the amplitude of the AC excitation signal in a predefined range.

4. The signal processing unit according to claim 1, wherein the inductive position sensor comprises at least one transmitter coil receiving the AC excitation signal, a first receiver coil providing the first position signal and a second receiver coil providing the second position signal.

5. The signal processing unit according to claim 1, wherein the oscillator comprises an LC-oscillator.

6. The signal processing unit according to claim 1, wherein: the signal processor detects an offset in the integrated first position signal and/or an offset in the integrated second phase-shifted position signal and/or a gain mismatch between the integrated first position signal and the integrated second phase-shifted position signal; and the signal processor provides a corresponding negative compensation signal to the integrator for compensating the detected offset and/or a gain calibration signal for compensating the gain mismatch.

7. The signal processing unit according to claim 6, wherein the negative compensation signal or gain calibration signal is converted from a digital signal to an analog signal by a digital-to-analog converter, particularly to a negative analog signal.

8. The signal processing unit according to claim 1, wherein the signal processing unit provides low-pass filtering and calibration.

9. The signal processing unit according to claim 1, wherein the first input and the second input are connected to a first multiplexer.

10. The signal processing unit according to claim 9, wherein the first input and the second input are connected to an amplifier and/or rectifier.

11. The signal processing unit according to claim 9, wherein an output of the first multiplexer is connected to an amplifier and/or rectifier.

12. The signal processing unit according to claim 9, wherein the signal processing unit comprises a test signal generation unit for providing a test signal to the first multiplexer, wherein the test signal can have a variety of scaling factors.

13. The signal processing unit according to claim 9, wherein the first multiplexer provides a non-inverted signal and an inverted signal for each input.

14. The signal processing unit according to claim 9, wherein the signal processor applies a pseudo-synchronized interleafed sampling method to the multiplexed and integrated first position signal and second phase-shifted position signal.

15. The signal processing unit according to claim 9, further comprising a peak detector for detecting the amplitude of the AC excitation signal provided to the output and a second multiplexer prior to the signal processor, wherein the AC excitation signal provided to the output is additionally provided to the first multiplexer and the signal processor compares the amplitude of the processed AC excitation signal provided to the first multiplexer with the detected amplitude of the peak detector provided to the second multiplexer.

16. The signal processing unit according to claim 15, wherein the peak detector comprises an operational amplifier, a diode and an RC low-pass filter.

17. The signal processing unit according to claim 1, wherein the first position signal comprises a sine position signal and the second phase-shifted position signal comprises a cosine position signal.

18. The signal processing unit according to claim 5, wherein the oscillator comprises a current-driven or current-limited cross-coupled inverter circuitry.

Description

BRIEF DESCRIPTIONS OF THE DRAWINGS

[0065] In the following, the disclosure will be further explained with respect to the embodiments shown in the figures. It shows:

[0066] FIG. 1 a simplified circuit diagram of an inductive position sensor (a) and a layout of a linear inductive position sensor (b),

[0067] FIG. 2 a general signal processing block diagram for an inductive position sensor,

[0068] FIG. 3 a block diagram of an inductive position sensor,

[0069] FIG. 4 a detailed block diagram of a first embodiment of an inductive position sensor comprising a signal processing unit according to the present disclosure,

[0070] FIG. 5 a circuit diagram of an RC-integrator,

[0071] FIG. 6 a detailed block diagram of a second embodiment of an inductive position sensor comprising a signal processing unit according to the present disclosure,

[0072] FIG. 7 a circuit diagram of a peak detector,

[0073] FIG. 8 a detailed architecture of a complete inductive position sensor interface circuitry according to the present disclosure,

[0074] FIG. 9 a detailed view of the analog front-end circuitry of the detailed architecture of FIG. 8,

[0075] FIG. 10 a pseudo-synchronized interleafed sampling method implemented by a signal processing unit according to the present disclosure,

[0076] FIG. 11 a diagram showing a detailed integration and conversion process,

[0077] FIG. 12 a simplified signal flow for ADC scheduling,

[0078] FIG. 13 an architecture of the digital post-processing method for the sine and cosine channel, and

[0079] FIG. 14 the basic analog signal integration flow for this kind of amplitude measurement within this disclosure.

DETAILED DESCRIPTION

[0080] FIG. 1 shows a simplified circuit diagram of an inductive position sensor 2, referring to section (a) of the figure. The inductive position sensor 2 is an apparatus based on the principle of magnetic induction for detecting a moving target 11 like a metallic target. By using this principle of mechanically interacting with an electromagnetic field, a huge variety of sensors for several application in e.g., mechatronics, e-motors and object detections can be created. The essential advantage of this high reliable inductive sensing technique is the contact-free position detection of the moving target 11.

[0081] Principally this type of inductive position sensor 2 can be understood as a transformer with two output coils, namely a first receiver coil 15 and a second receiver coil 16. A simplified circuit diagram is given in section (a) of FIG. 1. The transmitter or excitation coil 14 is interconnected with a capacitor 33 to perform an oscillator 9 (LC-oscillator) in resonance. The alternating magnetic field induces a current (voltage) in the receiver coils 15, 16. This induction method can be influenced by introducing a conductive target (moving target) 11 over the transformer. The conductive target 11 is affecting like a shortcut for the magnetic field and is manipulating the induced currents. This kind of amplitude modulation depends on the mechanical position of the conductive target 11.

[0082] FIG. 1 also shows a layout of a linear inductive position sensor 2, referring to section (b) of the figure. For this type of inductive sensor coils, the implementation of the receiver coils 15, 16 as sine and cosine shaped layout is characteristically. This sophisticated coil layout together with the conductive target 11 yields a position depending on sine and cosine amplitude modulated signal at the receiver coils 15, 16.

[0083] The layout of the transmitter coil 14 and the receiver coils 15, 16 can be easily adapted to the geometrically dimensions and shape of a mechatronic sub-system. This results a high flexibility and versatility of this position sensing method. The coils 14, 15, 16 can be cost-efficient produced by using standardize multi-layer printed circuit boards (PCBs). The challenge of this position sensing approach is a robust and accurate sensor-signal evaluation technique. The proposed signal processing unit 1 of this disclosure provides an efficient and precise electronically accomplishment of inductive position sensor systems.

[0084] FIG. 2 shows a general signal processing block diagram for an inductive position sensor 2. The inductive sensor elements can be understood as a transformer with an excitation coil 14 like primary windings and two receiver coils 15, 16 as secondary windings. The conductive target 11 is influencing the AC-signal coupling to the receiver coils 15, 16 and yields a position depending on amplitude modulation in the receiver coils 15, 16. The AC excitation signal 8 within the primary windings of the transmitter coil 14 is generated with a resonant oscillator (LCO) 9 consisting of the coil inductivity of the transmitter coil 14 and a capacitor 33 in parallel. A resistor 34 in parallel is representing the electrical losses of several parasitic elements. The oscillation is controlled by an oscillator controller 17 mainly to keep the amplitude constant in a predefined range. The receiver coils 15, 16 are connected to a so-called analog front-end circuitry (AFE) 35 with main functionality of measuring their amplitude levels. The AFE can comprise an input multiplexer 19, an amplifier 21 and a rectifier 22. Afterwards the amplitude value is preferably converted to a digital number by an analog-to-digital converter (ADC) 13. Finally, a signal processor 10, particularly a digital signal processor (DSP), is following for calculating the position with digital low-pass filtering and calibration.

[0085] FIG. 3 shows a block diagram of an inductive position sensor 2. Essential for an inductive position sensor 2 is the resonant LCO 9 for sensor signal excitation. The LCO 9 comprises the excitation coil 14 and the capacitor 33. The LC-oscillator frequency is not stable and can vary over temperature and other electrical or mechanical impacts. An oscillator controller 17 is necessary to drive the LC-oscillation in a certain range to avoid distortions in case of too high or too low amplitude levels. The oscillator controller 17 can be integrated (FIG. 2) in the LCO 9 or connected thereto (FIG. 3).

[0086] The coupling factor (induction of the planar receiver coils) between the excitation coil 14 and the receiver coils 15, 16 can also vary in a wide range. This amplitude reduction effect is compensated by a gain & offset controller 37, to keep the received amplitude signals of the first position signal 3 and the second position signal 4 appropriately for the input range of the ADC 13. An iterative algorithm works like an automatic gain and range control. The digital part is running with a stable high frequency oscillator (HFO) 38 and performs three complex processes in parallel. At first, a signal processor 10 performs a signal-processing algorithm for low-pass filtering (noise reduction) and position calculation. Second, a finite-state machine is controlling the important process and sensor parameters. Finally, the measured and processed sensor data are provided to a communication interface 39.

[0087] The coil-sensor is characterized by the resonant frequency F.sub.LCO and quality Q.sub.LCO:

[00002]$F_{\mathrm{LCO}}=\frac{1}{2?\sqrt{L_O{C}_O}}$$Q_{\mathrm{LCO}}=R_O\sqrt{\frac{C_O}{L_O}}$

[0088] FIG. 4 shows a detailed block diagram of a first embodiment of an inductive position sensor 2 comprising a signal processing unit 1 according to the present disclosure.

[0089] The signal processing unit 1 according to the present disclosure is for an inductive position sensor 2, wherein the inductive position sensor 2 provides a first position signal 3 and a second position signal 4, particularly a sine position signal and a cosine position signal. The signal processing unit 1 of the disclosure comprises: [0090] a first input 5 for the first position signal 3 and a second input 6 for the second position signal 4; [0091] an output 7 for providing an AC excitation signal 8 to the inductive position sensor 2; [0092] an oscillator 9 connected to the output 7 for generating the AC excitation signal 8; and [0093] a signal processor 10 for calculating the position of a moving target 11 of the inductive position sensor 2 from the first position signal 3 and the second position signal 4; and [0094] at least one integrator 12 for integrating an integer number of periods of the first position signal 3 respectively an integer number of periods of the second position signal 4.

[0095] The signal processor 10 calculates the position of the moving target 11 of the inductive position sensor 2 from the integrated first position signal 3 and the integrated second position signal 4.

[0096] The first input 5 and the second input 6 can be protected by an ESD-protection and EMC filter 39.

[0097] The first position signal 3 and the second position signal 4 are analog signals. The signal processing unit 1 comprises an analog-to-digital converter (ADC) 13 for converting the first position signal 3 and the second position signal 4 to a corresponding first digital position signal and to a corresponding second digital position signal. The ADC 13 is located after the integrator 12 and before the signal processor 10. Thus, the analog-to-digital converter converts the integrated first position signal 3 and the integrated second position signal 4 and the signal processor 10 is a digital signal processor (DSP). The signal processor 10 implements a CORDIC/arctan algorithm for calculating the position of the moving target 11 of the inductive position sensor 2.

[0098] The inductive position sensor 2 comprises at least one transmitter coil 14 receiving the AC excitation signal 8, a first receiver coil 15 providing the first position signal 3 and a second receiver coil 16 providing the second position signal 4, as for example shown in detail on the left-hand side of FIG. 3. In FIG. 4, these details have been replaced by boxes, but generally could be implemented as shown in FIG. 3.

[0099] The LCO 9 is an LC-oscillator, preferably a current-driven or current-limited cross-coupled inverter circuitry. The LCO 9 comprises the transmitter coil 14, a capacitor 33 and a resistor 34 representing the electrical losses of several parasitic elements.

[0100] This disclosure is based on a new approach using a frequency-synchronized integration scheme for evaluating the effective amplitude value of a first position signal 3 and a second position signal 4. Frequency-synchronized means that an integer number N.sub.INT of periods are integrated continuously. The integrator 12 behaves like an analogue 1.sup.st order low-pass filter if the integration time is comparable short. By integrating exactly N.sub.INT periods, the analog integrator 12 becomes an analog FIR filter with zeros at the fundamental and multiples of LC-oscillation frequency. In that sense, the number of integration periods defines the number of zeros for this quasi-analog low-pass FIR filter. A comparable 1.sup.st order RC low-pass filter is generating an attenuation and the remaining sine-ripple is limiting the signal-to-noise ratio. The integrator 12 approach can also be understood as a precise integrated mean-value evaluation of N.sub.INT rectified periods without any ripples or other frequency related effects.

[0101] The circuit implementation effort and size of the integrator 12 approach according to the present disclosure is comparable to the RC-low-pass filter approach known from the prior art. A disadvantage, in sense of circuit size, for the RC low-pass filter is the functionality of an anti-aliasing filter in front of the ADC 13. Depending on the sampling frequency of the ADC 13, a high order low-pass filtering may become necessary. That would require several low-pass filter stages in series. While the RC time constant R.sub.b*C.sub.b of a low-pass filter defines the attenuation (?3 dB corner frequency) the time constant 1/R.sub.int*C.sub.int of the integrator 12 is behaving like a gain factor. High gain values can simply be reached with small R.sub.int and C.sub.int values. Further, the entire analogue integration process works like an amplification over time and the number of integration periods N.sub.INT acts like an additional gain factor.

[0102] According to the embodiment of FIG. 4, the first input 5 and the second input 6 are connected to a first multiplexer 19. The signal processor 10 applies a pseudo-synchronized interleafed sampling method to the multiplexed and integrated first position signal 5 and second phase-shifted position signal 6.

[0103] FIG. 5 shows a detailed circuit diagram of an RC-integrator 12. An input 44 of the RC-integrator 12 is connected to a first terminal of a resistor 41. A second terminal of the resistor 41 is connected to an inverting input of an operational amplifier 40 of the RC-integrator 12. A non-inverting input of the operational amplifier 40 is connected to electrical ground.

[0104] A capacitor 42 is arranged between the inverting input of the operational amplifier 40 and an output of the operational amplifier 40. A switch 43 is arranged parallel to the capacitor 42. The switch 43 becomes necessary to set the initial integrator condition to zero volt, i.e., by discharging the capacitor 42.

[0105] FIG. 6 shows a detailed block diagram of a second embodiment of an inductive position sensor comprising a signal processing unit according to the present disclosure. The second embodiment of FIG. 6 differs from the first embodiment of FIG. 4 by additionally comprising a peak detector 27 for detecting the amplitude of the AC excitation signal 8 provided to the output 7 and a second multiplexer 28 prior to the signal processor 10. The AC excitation signal 8 provided to the output 7 is additionally provided to the first multiplexer 19 and the signal processor 10 compares the amplitude of the processed AC excitation signal 8 provided to the first multiplexer 19 with the detected amplitude of the peak detector 27 provided to the second multiplexer 28.

[0106] FIG. 7 shows a circuit diagram of the peak detector 27 of the second embodiment shown in FIG. 6. The input of the peak detector 27 is connected to an inverting input of an operational amplifier 29, while a non-inverting input of the operational amplifier is connected to electrical ground. An output of the operational amplifier is connected to the anode of a diode 30. The cathode of the diode 30 is connected to an output 47 of the peak detector. Furthermore, the cathode of the diode is connected to the inverting input of the operational amplifier 29 as a feedback loop. An RC low-pass filter 31 is connected between the output 47 of the peak detector 27 and electrical ground.

[0107] An important aspect for automotive sensor applications is the diagnostic capability, mainly for supporting functional safety requirements. An analogue signal path with enhanced diagnostic features is shown in FIG. 5. The basic approach is to feed the LC-oscillator signal directly into the AFE 35 for measuring the amplitude. In parallel, the peak detector 27 is implemented to provide continuously the amplitude signal for comparison and integrity. The peak detector 27 is shown in detail in FIG. 6 and represents a redundant hardware implementation and consists of the operational amplifier 29, the diode 30 and the RC low-pass filter 31. With these enhancements, two hardware-different amplitude measurement approaches for an AC excitation signal 8 are available. While the AFE 35 is determining an integrated (similar to effective) amplitude value, the peak detector 27 is providing the amplitude peak value of the positive and the negative phase directly. The comparison for equality of these measurement values is done in the signal processor 10.

[0108] FIG. 8 shows a detailed architecture of an inductive position sensor 2 interface circuitry according to the present disclosure. FIG. 9 shows a detailed view of the AFE 35 of the detailed architecture of FIG. 8.

[0109] The AFE 35 is implemented with differential circuitry. This improves mainly the immunity regarding distortions and power supply noise. A low-noise instrumentation amplifier 21 with a programmable gain resistor network is via the EMC filter 39 directly connected with the sensor coils 15, 16. The rectifier 22 is implemented using a mixer that is basically a CMOS transmission-gate switch. It realizes the multiplication of the phase-delayed LCO-clock signal with the output of the amplifier 21. The final stage of the analogue signal-processing path is the integrator 12. It is composed of a programmable resistor R.sub.INT and capacitor C.sub.INT array to reach a wide range of integration time constants. Further, a switching network is implemented to realize the reset function of the integrator 12 that forces the differential output value to zero. The AFE 35 contains an analogue offset compensation at the integrator stage.

[0110] The sensor coils 15, 16 are suffering from a crossfeed or crosstalk directly from the excitation coil 14 to the lead wires or other non-linearity of the coil layout. This is considered by assuming a LC-oscillator layout-depending amplitude V.sub.OFFS.sup.sin and V.sub.OFFS.sup.cos respectively. Additionally, a gain mismatch with different coil coupling (attenuation) factors C.sub.ATT.sup.sin and C.sub.ATT.sup.cos is considered. After rectification of the receiver coil signals S.sub.sin(t) and S.sub.cos(t) this coupling effect appears like a static offset voltage .Math..sub.sin and .Math..sub.cos and will be integrated in addition to the raw sensor signals 3, 4.

[0111] Especially for small coil layouts, these offset amplitudes can reach the size of the raw sensor signals 3, 4. The compensation of these offsets is done by adding a complementary negative voltage as an additional input path to the integrator 12. A digital-to-analogue converter (DAC) 18 controlled by the digital part (calibration values) generates these voltages V.sub.DAC.sup.sin and V.sub.DAC.sup.cos. This ensures that the offset voltage does not degrade the output range of the integrator 12 and the input range of the ADC 13 respectively.

S.sub.sin(t)=A.sub.LCO*C.sub.ATT.sup.sin*sin(?.sub.PS*t)*sin(?.sub.LCO*t)+V.sub.OFFS.sup.sin*sin(?.sub.LCO*t)

S.sub.cos(t)=A.sub.LCO*C.sub.ATT.sup.cos*cos(?.sub.PS*t)*sin(?.sub.LCO*t)+V.sub.OFFS.sup.cos*sin(?.sub.LCO*t)

{circumflex over (U)}.sub.sin=?V.sub.OFFS.sup.sin*sin(?.sub.LCO*t)?V.sub.DAC.sup.sin

{circumflex over (U)}.sub.cos=?V.sub.OFFS.sup.scos*sin(?.sub.LCO*t)?V.sub.DAC.sup.cos

[0112] The multiplexer 19 defines the differential input channel for the AFE 35 and is controlled by the finite-state-machine (FSM) Sequencer module. It is composed of low-resistive CMOS transmission-gate switches. The input of the multiplexer 19 is connected directly to the first receiver coil 15 (sine coil) and the second receiver coil 16 (cosine coil) of the inductive position sensor 2. The Test-In channel connected to a test signal generation unit 23 has been implemented for diagnostic purposes. A scaled voltage of the LCO 9 is generated here for a self-test of the complete AFE 35 and ADC 13 path. A certain variety of scaling factors is necessary to validate the settings of the amplifier 21 and time constants of the integrator 12. Further, this multiplexer 19 is providing inverted and non-inverted signals for each input.

[0113] The LC-oscillator 9 is principally a current-driven or current-limited cross-coupled inverter circuitry. The LC tank is storing the oscillation energy that is proportional to the oscillation current I.sub.LCO. The characteristic impedance Z.sub.LCO is defining the voltage amplitude V.sub.LCO of this resonant circuit in ideal case based on the current I.sub.LCO:

[00003]$Z_{\mathrm{LCO}}=\sqrt{\frac{C_X}{L_X}}$$V_{\mathrm{LCO}}=I_{\mathrm{LCO}}\sqrt{\frac{L_X}{C_X}}$

[0114] In real applications, the resonant circuit is damped by parasitic resistive elements. The active oscillation circuit of cross-coupled current-controlled inverters becomes necessary to compensate these losses and for keeping the amplitude constant. The peak detector 27 is continuously monitoring the oscillation amplitude V.sub.LCO and is evaluated by the oscillator controller 17, also referred to as Amplitude & Frequency Monitor. The oscillator controller 17 computes the control values for the programmable CMOS current sources I.sub.LCOp and I.sub.LCOn to reach a predefined amplitude and to keep the amplitude at a constant level.

[0115] The LC-oscillation sine wave signal is phase-delayed because of several parasitic effects in the sensor coils 15, 16, the EMC filter 39 and the input multiplexer 19. Mainly to avoid distortions during rectification a phase-delay module 48 provides a phase-synchronous clock signal for the rectifier 22.

[0116] At first, the frequency monitor 17 is evaluating the frequency proportion between the LC-oscillator 9 and the digital oscillator 38 (frequency counter principle). The resonant frequency is predefined by external components and is assumed to be in range from 2 to 6 MHz. If the resonant frequency is outside of this range the sensor interface operation will be stopped. Beside the frequency, the LC-oscillator amplitude is monitored. If the amplitude becomes too high, distortion effects can degrade the sensor performance. If the amplitude is too low, the signal quality for sensor position detection is affected by increased noise and reduced resolution. Further, this module includes a level control processor (PID control) keeping the amplitude in a predefined range.

[0117] The digital oscillator 38 is an on-chip relaxation oscillator and is temperature compensated and calibrated during ATE test. The generated clock signal can be handled as a 3% accurate time base.

[0118] The FSM sequencer 49 is a measurement control subsystem and works synchronously with the LC-oscillator 9. The basic operation is to manage the sequence of integration cycles, reset phase, settings of the multiplexer channels and sample conversion scheme.

[0119] The signal processor 10 and signal processing unit controller 36 are shown in FIG. 8 as a single module. This module comprises a digital signal processor for filtering the ADC sample values, the CORDIC algorithm for position or angle calculation, a set of parameters for controlling the measurement cycles and some functions for analysis and diagnostic of several measurement values.

[0120] FIG. 10 shows a pseudo-synchronized interleafed sampling method implemented by a signal processing unit according to the present disclosure. The important part of this disclosure is the time succession of measurements and the calculation of mean values. This measurement approach utilizes values from a single multiplexed analog path. Further, it compensates the sampling delay caused by channel multiplexing. The sine channel (first position signal 3) and cosine channel (second position signal 4) are measured in an alternating way using multiplexer 19 and in between, the polarity is swapped. This swapping or chopping technique for the input channels (sensor coils 15, 16) is necessary to remove any circuit offset and reduces the noise, mainly the low frequency and 1/f noise.

[0121] FIG. 10 illustrates the interleaved sampling scheme. The circles are defining the time points t.sub.m of the new calculated mean values. This treatment generates a measurement value delay of 2.5 ADC conversion steps that is equal for sine and cosine channel.

[0122] The interleaved sampling scheme can be processed with four consecutive conversion steps: [0123] 1. sine channel with positive polarity at time step tn?3:

A.sup.+.sub.SIN[tn?3] [0124] 2. cosine channel with positive polarity at time step tn?2:

A.sup.+.sub.COS[tn?2] [0125] 3. cosine channel with negative polarity at time step tn?1:

A.sup.?.sub.COS[tn?1] [0126] 4. sine channel with negative polarity at time step tn:

A.sup.?.sub.SIN[tn] [0127] 5. sine channel with positive polarity at time step tn+1:

A.sup.+.sub.SIN[tn+1] [0128] 6. cosine channel with positive polarity at time step tn+2:

A.sup.+.sub.COS[tn+2] [0129] 7. . . .

[0130] After capturing these four values A.sup.+.sub.SIN, A.sup.+.sub.COS, A.sup.?.sub.COS, A.sup.?.sub.SIN, the calculation of the mean value is performed with the equations hereafter. For following mean value calculations two new samples (e.g., steps 5. and 6. above) are sufficient:

?.sub.SIN[tm]=A.sup.+.sub.SIN[tn?3]?A.sup.?.sub.SIN[tn]

?.sub.COS[tm]=A.sup.+.sub.COS[tn?2]?A.sup.?.sub.COS[tn?1]

?.sub.SIN[tm+1]=A.sup.+.sub.SIN[tn+1]?A.sup.?.sub.SIN[tn]

?.sub.COS[tm+1]=A.sup.+.sub.COS[tn+2]?A.sup.?.sub.COS[tn?1]

[0131] With this method, the channel throughput rate is cut in half, compared with the ADC sampling rate. Pseudo-synchronized means that even though the channels and polarities are sampled after each other. The sampling time point for the sine ?.sub.SIN and the cosine ?.sub.COS values is (approximately) the same, if the sampling frequency is about 32 times (or more) higher than the signal frequency of the position sensor themselves.

[0132] The analogue integration phase has to run synchronously with the resonant LC-oscillator 9 to ensure exactly the integration of N.sub.INT (integer) phases. After this integration phase, a reset of the analogue integrator circuitry 12 is invoked for an entire oscillation phase. Further, this reset phase is used for an inherent offset cancellation of the operational amplifiers. The detailed integration and conversion process is depicted in FIG. 11. An important outcome of this disclosure is the implementation of a sophisticated synchronization procedure between the LC-oscillation based integration and the analogue-to-digital conversion process that is running with the digital clock. To reach this kind of synchronization a SAR-ADC is realized with an asynchronously working sample-and-hold stage for capturing the input voltage. It is presumed that the digital clock frequency is minimum factor 10 higher than the LCO frequency.

[0133] Detailed description based on the signal flow of FIG. 12: The ADC-sampling phase is activated in the next-to-last LCO period (M.1) of the integration phase. This ensures that the sampling duration is slightly larger than the last integration cycle (M.2). The ADC sampling phase is closed precisely with the positive edge of the LCO-clock (M.3) that is disposed as the integrator reset phase. After the ADC-sampling phase is closed, the analog captured value is stored for a short time synchronization window (M.6). The following analog-to-digital conversion phase (SAR principle) is then started synchronously with the digital clock (M.7).

[0134] An important enhancement of the proposed signal processing architecture is the possibility to sample multiple analog channels for diagnostic purposes. SAR-ADCs realized in modern mixed-signal technologies offer a conversion rate of a few MS/s at 14-bit accuracy and they fit into the requirements of this disclosure optimally. FIG. 12 shows the simplified signal flow for this ADC scheduling. Based on a programmable number N.sub.INT (K.2) of LC-oscillator periods the integration process duration is given by (K.1). The programmable integrator reset phase (K.3) is exactly one LCO period in this example. This result in a measurement repetition time T.sub.INTP (E.15). If the ADC conversion time T.sub.ADC is significant shorter than the integration process duration T.sub.INTP intermediate conversions can be applied. If the condition of ?.sub.COS[tm]=A.sup.+.sub.COS[tn?2]?A.sup.?.sub.COS[tn?1] is valid, two ADC conversions can be performed during the integration process. The shaded areas are highlighting the sample phase for the SAR-ADC. The coil channel conversion starts synchronously with the integrator reset phase. Thereafter the diagnostic conversion is executed.

T.sub.INTP=(N.sub.INT+1)/F.sub.LCO

T.sub.INTP>2.5*T.sub.ADC

[0135] This disclosure comprises a sophisticated analogue and digital signal processing path for an inductive sensor interface circuitry. The architecture of the digital post-processing method for the sine and cosine channel is depicted in FIG. 13. The block Control & DSP & Diagnostic of FIG. 8 includes this digital processing implantation.

[0136] The first processing stage executes the combined channel de-multiplexing and pseudo-synchronization as given in FIG. 10 and provides the raw sample values S.sub.SIN[tm], S.sub.COS[tm]. A programmable 1.sup.st order IIR low-pass filter is available for further noise reduction that improve the position calculation precision. The 1.sup.st order IIR low-pass filter is defined by:

R.sub.SIN[tm]=C.sub.a*S.sub.SIN[tm]+C.sub.b*R.sub.SIN[tm?1], 0<C.sub.a<1, C.sub.b=1?C.sub.a

R.sub.COS[tm]=C.sub.a*S.sub.COS[tm]+C.sub.b*R.sub.COS[tm?1], 0<C.sub.a<1, C.sub.b=1?C.sub.a

[0137] The most significant sensor accuracy reduction is caused by offsets and amplitude mismatch. The Offset & Gain Error Detection block is monitoring the minimum and maximum values of each sine and cosine channel during operation. Based on these peak values the sensor offsets O.sub.SIN, O.sub.COS and the gain mismatch G.sub.ERR can be calculated. Further, the offset and gain correction values can be determined in an external calibration run and stored in dedicated calibration registers. In the following processing stage, the sensor values are corrected by:

P.sub.SIN[tm]=R.sub.SIN[tm]+O.sub.SIN

P.sub.COS[tm]=G.sub.ERR*(R.sub.COS[tm]+O.sub.COS)

[0138] Finally, the position or angle is computed with a classical CORDIC algorithm:

Position @t.sub.m=CORDIC{P.sub.SIN[tm], P.sub.COS[tm]}

[0139] Following the method for gain and offset correction of this disclosure is described in detail and can be done automatically for rotary sensors. The calculated sensor offsets O.sub.SIN and O.sub.COS values are divided in an analogue compensation value, DAC voltage equivalents C.sub.OFFS.sup.sin (V.sub.DAC.sup.sin) and C.sub.OFFS.sup.cos (V.sub.DAC.sup.cos) as given in FIGS. 8 and 9, and a digital value as described above to be applied for highly precise position calculations. Because of the limited resolution of V.sub.DAC, the offset cannot be removed completely. If the analogue offset compensation is provided by these values, the new measured and calculated sensor offsets O.sub.SIN and O.sub.COS values are already reduced by this amount. The overall offset and gain compensation procedure is subdivided in three successive steps: [0140] 1.sup.st iteration: analogue offset compensation by using the DAC; [0141] 2.sup.nd iteration: analogue gain adaptation by using the PGA and integrator time-constant; [0142] 3rd iteration: digital calculation of remaining offset O.sub.SIN, O.sub.COS and gain mismatch G.sub.ERR.

[0143] If the digital offset or digital peak-amplitude values are deviating from pre-defined limits the above defined 3-step iteration process needs to be invoked again.

[0144] FIG. 14 illustrates the basic analog signal integration flow for an amplitude measurement within this disclosure. Principally the measurement procedure is a sequence of N.sub.INT cycle integration periods and a following integrator-reset phase. This sequence is running synchronously with the LC-oscillator frequency and phase. Diagram (2) depicts the coil signal after the input multiplexer 19. In this example, the inverted and non-inverted coil signals are drawn. The integrator reset phase is utilized for switching the input multiplexer 19 and coil signal settling. The rectified coil signal is shown in diagram (3). The coil signal integration process is given in diagram (4). After the reset phase, the signal integration starts and is finally captured in the sample-&-hold stage (diagram 4) for conversion. Signal integration and analogue-to-digital conversion within an SAR-ADC are parallel running processes.

List of Reference Numerals

[0145] 1 signal processing unit

[0146] 2 inductive position sensor

[0147] 3 first position signal

[0148] 4 second position signal

[0149] 5 first input (signal processing unit)

[0150] 6 second input (signal processing unit)

[0151] 7 output (signal processing unit)

[0152] 8 excitation signal

[0153] 9 oscillator (LCO)

[0154] 10 signal processor

[0155] 11 conductive target (moving target)

[0156] 12 integrator (RC-integrator)

[0157] 13 analog-to-digital converter (ADC)

[0158] 14 transmitter coil (excitation coil)

[0159] 15 first receiver coil (sensor coil)

[0160] 16 second receiver coil (sensor coil)

[0161] 17 oscillator controller (Amplitude & Frequency Monitor)

[0162] 18 digital-to-analog converter (DAC)

[0163] 19 first multiplexer (input multiplexer)

[0164] 20 output (first multiplexer)

[0165] 21 amplifier

[0166] 22 rectifier

[0167] 23 test signal generation unit

[0168] 24 test signal

[0169] 25 non-inverted signal (first multiplexer)

[0170] 26 inverted signal (multiplexer)

[0171] 27 peak detector

[0172] 28 second multiplexer

[0173] 29 operational amplifier (peak detector)

[0174] 30 diode (peak detector)

[0175] 31 RC low-pass filter (peak detector)

[0176] 33 capacitor (excitation coil)

[0177] 34 resistor (excitation coil)

[0178] 35 analog front-end circuitry (AFE)

[0179] 36 controller (signal processing unit)

[0180] 37 gain & offset controller

[0181] 38 high frequency oscillator (HFO) (digital oscillator)

[0182] 39 ESD-protection, EMC filter

[0183] 40 operational amplifier (RC-integrator)

[0184] 41 resistor (RC-integrator)

[0185] 42 capacitor (RC-integrator)

[0186] 43 switch (RC-integrator)

[0187] 44 input (RC-integrator)

[0188] 45 output

[0189] 46 input (peak detector)

[0190] 47 output (peak detector)

[0191] 48 phase-delay module

[0192] 49 FSM sequencer