TEST SYSTEMS AND METHODS FOR CHIPS IN WAFER SCALE PHOTONIC SYSTEMS

Abstract

A qualification apparatus for a photonic chip on a wafer that leaves undisturbed an edge coupler that provides an operating port for the photonic devices or circuits on the chip during normal operation in order to not introduce extra loss in the optical path of the final circuit. The qualification apparatus provides an optical path that is angled with regard to the surface of the chip, for example by using a grating coupler. The qualification apparatus can be removed after the chip is qualified. Optionally, the qualification apparatus can be left in communication with the chip and optionally employed as an input port for the chip after the chip has been separated from other chips on a common substrate.

Claims

1-16. (canceled)

17. A wafer comprising: a plurality of photonic chips defined in or upon the wafer, the plurality of photonic chips including at least one photonic chip comprising: a photonic integrated circuit (PIC); an operating port configured to be used during normal operation of the at least one photonic chip after a separation thereof from the wafer; a test port configured for testing the PIC prior to the separation from the wafer; a first optical waveguide connecting the operating port to the PIC; and, a device disposed to couple test light from the test port into the first optical waveguide to be guided into the PIC.

18. The wafer of claim 17 comprising wherein the at least one photonic chip is separated from another photonic chip defined in or upon the wafer by a dicing line, and wherein the operating port comprises an edge port disposed at the dicing line.

19. The wafer of claim 17 wherein the test port comprises a grating coupler configured to receive the test light that propagates at an angle to a free surface of the wafer.

20. The wafer of claim 17 further comprising a second optical waveguide connecting the test port to the directional coupler.

21. The wafer of claim 20 wherein the test port is configured to couple the test light that propagates at an angle to a free surface of the wafer into the second optical waveguide.

22. The wafer of claim 17 comprising a semiconductor material.

23. The wafer of claim 17 comprising silicon on insulator.

24. The wafer of claim 17 wherein the device comprises a directional coupler.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The objects and features of the invention can be better understood with reference to the drawings described below, and the claims. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the drawings, like numerals are used to indicate like parts throughout the various views.

[0022] FIG. 1 is a drawing that illustrates one embodiment in which a chip having a circuit or a photonic device to be tested is present on a wafer.

[0023] FIG. 2 is a drawing that illustrates another embodiment in which a chip having a circuit or a photonic device to be tested is present on a wafer.

[0024] FIG. 3 is a diagram in plan view of a plurality of chips fabricated on a wafer.

[0025] FIG. 4 is a first cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon.

[0026] FIG. 5 is a second cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon.

[0027] FIG. 6 is a cross sectional view through a second embodiment of a wafer having a plurality of chips fabricated thereon.

[0028] FIG. 7 is a cross sectional view through a third embodiment of a wafer having a plurality of chips fabricated thereon.

[0029] FIG. 8 is a cross sectional view through a fourth embodiment of a wafer having a plurality of chips fabricated thereon.

[0030] FIG. 9 is a cross sectional view through a fourth embodiment of a wafer having a plurality of chips fabricated thereon.

DETAILED DESCRIPTION

Acronyms

[0031] A list of acronyms and their usual meanings in the present document (unless otherwise explicitly stated to denote a different thing) are presented below. [0032] AMR Adabatic Micro-Ring [0033] APD Avalanche Photodetector [0034] ARM Anti-Reflection Microstructure [0035] ASE Amplified Spontaneous Emission [0036] BER Bit Error Rate [0037] BOX Buried Oxide [0038] CMOS Complementary Metal-Oxide-Semiconductor [0039] CMP Chemical-Mechanical Planarization [0040] DBR Distributed Bragg Reflector [0041] DC (optics) Directional Coupler [0042] DC (electronics) Direct Current [0043] DCA Digital Communication Analyzer [0044] DRC Design Rule Checking [0045] DUT Device Under Test [0046] ECL External Cavity Laser [0047] FDTD Finite Difference Time Domain [0048] FOM Figure of Merit [0049] FSR Free Spectral Range [0050] FWHM Full Width at Half Maximum [0051] GaAs Gallium Arsenide [0052] InP Indium Phosphide [0053] LiNO.sub.3 Lithium Niobate [0054] LIV Light intensity(L)-Current(I)-Voltage(V) [0055] MFD Mode Field Diameter [0056] MPW Multi Project Wafer [0057] NRZ Non-Return to Zero [0058] PIC Photonic Integrated Circuits [0059] PRBS Pseudo Random Bit Sequence [0060] PDFA Praseodymium-Doped-Fiber-Amplifier [0061] PSO Particle Swarm Optimization [0062] Q Quality factor

[00001]$Q=2.Math.\frac{\mathrm{Energy}.Math..Math.\mathrm{Stored}}{\mathrm{Energy}.Math..Math.\mathrm{dissipated}.Math..Math.\mathrm{per}.Math..Math.\mathrm{cycle}}=2.Math..Math..Math.f_r\frac{\mathrm{Energy}.Math..Math.\mathrm{Stored}}{\mathrm{Power}.Math..Math.\mathrm{Loss}}.$ [0063] QD Quantum Dot [0064] RSOA Reflective Semiconductor Optical Amplifier [0065] SOI Silicon on Insulator [0066] SEM Scanning Electron Microscope [0067] SMSR Single-Mode Suppression Ratio [0068] TEC Thermal Electric Cooler [0069] WDM Wavelength Division Multiplexing

[0070] As used herein the term substrate is meant to include a silicon wafer, a silicon on insulator (SOI) wafer, a semiconductor wafer comprising material such as III-V compounds such as GaAs, InP and alloys of such III-V compounds, and wafers made of materials that are not semiconducting such as quartz and alumina.

[0071] We describe systems and methods for wafer scale qualification of photonic systems that would otherwise need to be diced and processed before component qualification can occur. In brief, the systems and methods of the invention allow one to measure every chip fabricated on the substrate, decide which chips are good (e.g., pass a qualification test) and which are bad (e.g., fail at least one element of a qualification test), mark the ones that are bad, separate the individual chips (for example by dicing), readily identify the bad chips after the chips are separated, and optionally throw the bad chips away or destroy them, while keeping the good chips. In some embodiments, an edge coupler is used to provide optical input and/or to receive optical output from photonic devices (or circuits) on a chip (e.g., to behave as an operating port for the photonic devices or circuits on the chip during normal operation). In order to not introduce extra loss, it is desirable to keep the optical path of the final circuit unchanged as compared to the optical path of a test circuit. In some embodiments, the optical test circuit remains on the completed chip and may optionally be used as an input port after the chip is fabricated and separated from the other chips on the substrate.

[0072] As illustrated in the embodiment shown in FIG. 1, a chip 110 having a circuit 120 or a photonic device 120 to be tested is present on a wafer 100. The chip 110 includes an edge coupler 130 that communicates with the circuit 120 by way of a waveguide 125.

[0073] As illustrated in the embodiment shown in FIG. 1, a second optical coupler can be used to provide an optical connection for testing the device (e.g., to provide a temporary optical port that allows the device to be tested, and which can subsequently be removed, masked off, or put into an unused state). As shown in the embodiment of FIG. 1, a sacrificial region 115 on the wafer 100 adjacent the chip 110 can be provided. In the sacrificial region 115 a second edge coupler 140 can be used to couple to the edge coupler 130 of the circuit 120 of interest. This second edge coupler 140 can then be connected to a grating coupler 150 by way of an optical waveguide 180 in order to provide an interface for light that couples out of the plane of the chip. Dicing lanes 160 are provided so that the chip 110 and the sacrificial region 115 can be cut out of the wafer 100 if the chip 110 is found to be acceptable after the test. The sacrificial region 115 may be separated from the chip 110 and discarded.

[0074] One advantage of using a grating coupler is that the test signal can be applied from a source that does not have to have its optical propagation direction in the plane of the chip. In addition, a resulting optical signal that may be generated by the circuit can be observed without having to place an optical sensor or receiver in the plane of the chip. For example, an optical test source (and/or an optical sensor or receiver) can be used that is oriented at an angle to a surface of the chip, and that can be rastered over the surface of the chip, so that individual grating couplers 150 present on the chip (for example, one grating couple per circuit fabricated on the chip) can each be accessed in a convenient manner, quickly, and at reduced expense. In this manner, a plurality of circuits on the chip can be tested without having to dice or saw the chip, and the location of each circuit and whether it passed or failed a given test can be logged.

[0075] In some embodiments, the sacrificial grating coupler chip includes an optical circuit useful in testing, such as a phase modulator to test a coherent mixer or a photodetector for alignment.

[0076] As illustrated in another embodiment shown in FIG. 2, a wafer 200 has a chip 210 fabricated thereon. The chip 210 has not been cleaved or sawed from the wafer 200. The chip 210 is in optical communication with an edge coupler 230 by way of waveguide 225, which is the optical interface that is to be used with the chip 210 if the chip 210 passes the required tests and inspections, and is then cleaved or sawed out of the wafer 200.

[0077] As illustrated in the embodiment shown in FIG. 2, a test interface comprising a grating coupler 250 in optical communication with a directional coupler 270 by way of a waveguide 280 can be provided as a convenient optical connection to allow the circuit 210 to be tested. Once again, the grating coupler 250 provides the same advantages as are provided by the grating coupler 150 shown in FIG. 1.

[0078] In the embodiment of FIG. 2, wafer-scale test of edge coupled systems can be enabled by using a grating coupler 250 that is fed into the main optical path 225 using a directional coupler 270. As directional couplers are optically symmetric, a small tap is used so that little power is lost from the main optical circuit. A second tap can be used to measure an optical output of the circuit. Electrical outputs can be probed such that the electrical systems in the circuit can be tested in some way before dicing. After dicing and facet preparation, the testing structures are still present in the circuit, but provide minimal loss for the circuit operation.

[0079] After testing is completed, and depending on the method of facet fabrication, the testing interface (e.g., a grating coupler and/or a second edge coupler) can be removed in a variety of ways. If polishing is the approach used for facet preparation, the extra area or the test grating coupler 150, 250 can simply be polished away. If the facet is etched, the second set of edge couplers could exist on the other side of the etch trench, or the etch could proceed after circuit test. If the wafer is cleaved or sawed, the couplers could sit on opposite sides of the cleave (or saw) line. In some embodiments, such as illustrated in FIG. 2, the optical connection provided by the grating coupler 250 can simply be ignored if the chip on which the circuit 210 is fabricated is housed or used in such a way that the grating coupler 250 is masked off or otherwise is rendered optically inaccessible. In some alternative embodiments, the grating coupler 250 may be left in place without being masked off, but the waveguide 280 is cut or removed, so that the grating coupler 250 is no longer in optical communication with the directional coupler 270.

[0080] In the embodiment of FIG. 2, wafer-scale test of edge coupled systems can be enabled by using a grating coupler that is fed into the main optical path using a directional coupler. As directional couplers are optically symmetric, a small tap is used so that little power is lost from the main optical circuit. A second tap can be used to measure an optical output of the circuit. Electrical outputs can be probed such that most systems can be tested in some way before dicing. After dicing and facet preparation, the testing structures are still present in the circuit, but provide minimal loss for the circuit operation.

[0081] In some embodiments, the gap between the edge couplers can be in the range of 50 to 100 m. Due to the significant distance, the edge couplers can be designed to have large mode fields to minimize the optical divergence to just a few degrees.

[0082] In a further embodiment, the etched facets are angled, so that one can deflect the optical beam of the edge coupler of the optical circuit in one direction or another. The second edge coupler can be designed to be higher or lower in the back end to match the location where the optical beam will hit. Further, the second edge couple may be configured such that the optical output propagates at an angle opposite the first edge coupler so that the two modes will overlap for minimal optical loss.

[0083] FIG. 3 is a diagram in plan view of a plurality of chips 310, 310, 310, 310 fabricated on a wafer 300. In FIG. 3, each chip includes an edge coupler 320 connected by an optical waveguide to a circuit 320, and a grating coupler 340 connected to a second edge coupler 350. As should be apparent from the forgoing discussion, chip 310 can be tested using the grating coupler and the second edge coupler present on adjacent chip 310. For chips at the periphery of the wafer, additional grating couplers and second edge couplers (not shown) can be provided in areas that do not carry circuits, such as in area 305 to allow testing of the circuits present on chips that are at the periphery of the wafer 300. Dicing lanes 360 are illustrated to indicate how the chips may be separated from each other, with the test structures (the grating coupler and the second edge coupler) for the adjacent chip remaining after dicing. In another embodiment, a dicing lane 370 (shown in a dotted line) may be used to remove the test structures so that the diced chip includes only the first edge coupler and the circuit, but not the test structures for a chip that is no long present after dicing. During testing, the chips that pass the qualification test and the chips that fail the qualification test are differentiated, for example by marking the chips that have failed at least one element of the qualification test, so that they can be separated from the good chips after the dicing operation.

[0084] FIG. 4 is a first cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon. As shown in FIG. 4 an edge coupler 400 that is part of the test structure and an edge coupler 420 that is connected to a circuit are present. A region 410 that can be used to etch to separate chips on a wafer, or that can be a dicing lane, is illustrated. The test edge coupler 400 is constructed so that it is quite close to the edge coupler 420 during testing so that optical communication between edge coupler 400 and edge coupler 420 will be good. However, during etching or dicing for separating chips, some of edge coupler 400 will be lost, while none of edge couple 420 will be removed or damaged.

[0085] FIG. 5 is a second cross sectional view through a first embodiment of a wafer having a plurality of chips fabricated thereon. In FIG. 5, which is a diagram similar to FIG. 4 but after etching has occurred, one sees that part of edge coupler 400 is gone, but the edge coupler 420 is intact.

[0086] FIG. 6 is a cross sectional view through a second embodiment of a wafer having a plurality of chips fabricated thereon. In the embodiment of FIG. 6, an edge coupler 620 connected to a circuit on a chip (not shown) communicates with another edge coupler 600 as illustrated by the propagating light 610 that propagates across an etch trench.

[0087] FIG. 7 is a cross sectional view through a third embodiment 700 of a wafer having a plurality of chips fabricated thereon. In the embodiment of FIG. 7, an edge coupler 730 connected to a circuit on a chip (not shown) communicates with another edge coupler 700 as illustrated by the propagating light 720 that propagates across an etch trench at an angle. Propagating light 720 is situated at an angle to a direction of propagation in edge coupler 730 in order to accommodate edge coupler 710, which is shown at a different height than edge coupler 730.

[0088] FIG. 8 is a cross sectional view through a fourth embodiment 800 of a wafer having a plurality of chips fabricated thereon. In the embodiment of FIG. 8, an edge coupler 840 connected to a circuit on a chip (not shown) communicates with a grating coupler 810 as illustrated by the propagating light 830 that propagates across an etch trench at an angle. Propagating light 830 is situated at an angle to a direction of propagation in edge coupler 840 in order to accommodate grating coupler 810, which is shown at a different height than edge coupler 840. Also shown is propagating light 820 from the grating coupler 810 to the edge coupler 840.

[0089] FIG. 9 is a cross sectional view through a fourth embodiment 900 of a wafer having a plurality of chips fabricated thereon. In the embodiment of FIG. 9, a first grating coupler 940 connected to a circuit on a chip (not shown) communicates with a second grating coupler 910 as illustrated by the propagating light 930 that propagates across an etch trench at an angle. Propagating light 930 is situated at an angle to a direction of propagation in grating coupler 940 in order to accommodate grating coupler 910, which is shown at a different height than grating coupler 940. Also shown is propagating light 920 from the grating coupler 910 to the grating coupler 940.

[0090] Various additional embodiments and features can be used with the systems and methods of the invention.

[0091] One can use on-chip photodiodes as monitors for edge couplers, using either taps or the structure shown in FIG. 1 and FIG. 2.

[0092] In some embodiments, one can use a plurality of coupler structures in sequence in order to characterize system losses.

[0093] In some embodiments, one can use couplers facing one another across a wafer-scale etched trench, in order to directly characterize coupling losses.

[0094] In some embodiments, grating coupled taps can be used to observe signals from an actual system such as a coherent transceiver, so as to allow testing of the actual edge facet that will be used and will be coupled to an optical fiber.

[0095] In some embodiments, one can provide lithographically designed in-plane lenses on one or two axes in combination with the chip.

[0096] In some embodiments, one may integrate polarization controllers and rotators with these structures.

[0097] In some embodiments, one may integrate additional electro-optical circuitry in the test structure to aid in the qualification of the chips, such as an on-chip phase modulator.

[0098] In some embodiments, one may integrate large photodiodes across the trench from the optical circuit's edge couplers, so as to monitor parameters such as insertion loss.

Design and Fabrication

[0099] Methods of designing and fabricating devices having elements similar to those described herein are described in one or more of U.S. Pat. Nos. 7,200,308, 7,339,724, 7,424,192, 7,480,434, 7,643,714, 7,760,970, 7,894,696, 8,031,985, 8,067,724, 8,098,965, 8,203,115, 8,237,102, 8,258,476, 8,270,778, 8,280,211, 8,311,374, 8,340,486, 8,380,016, 8,390,922, 8,798,406, and 8,818,141, each of which documents is hereby incorporated by reference herein in its entirety.

Test Apparatus and Methods

[0100] Methods of testing photonic devices having elements similar to those described herein, and various kinds of test apparatus, are described in one or more of U.S. Pat. Nos. 7,200,308, 7,339,724, 7,424,192, 7,480,434, 7,643,714, 7,760,970, 7,894,696, 8,031,985, 8,067,724, 8,098,965, 8,203,115, 8,237,102, 8,258,476, 8,270,778, 8,280,211, 8,311,374, 8,340,486, 8,380,016, 8,390,922, 8,798,406, and 8,818,141, each of which documents is hereby incorporated by reference herein in its entirety.

Definitions

[0101] As used herein, the term optical communication channel is intended to denote a single optical channel, such as light that can carry information using a specific carrier wavelength in a wavelength division multiplexed (WDM) system.

[0102] As used herein, the term optical carrier is intended to denote a medium or a structure through which any number of optical signals including WDM signals can propagate, which by way of example can include gases such as air, a void such as a vacuum or extraterrestrial space, and structures such as optical fibers and optical waveguides.

Theoretical Discussion

[0103] Although the theoretical description given herein is thought to be correct, the operation of the devices described and claimed herein does not depend upon the accuracy or validity of the theoretical description. That is, later theoretical developments that may explain the observed results on a basis different from the theory presented herein will not detract from the inventions described herein.

[0104] Any patent, patent application, patent application publication, journal article, book, published paper, or other publicly available material identified in the specification is hereby incorporated by reference herein in its entirety. Any material, or portion thereof, that is said to be incorporated by reference herein, but which conflicts with existing definitions, statements, or other disclosure material explicitly set forth herein is only incorporated to the extent that no conflict arises between that incorporated material and the present disclosure material. In the event of a conflict, the conflict is to be resolved in favor of the present disclosure as the preferred disclosure.

[0105] While the present invention has been particularly shown and described with reference to the preferred mode as illustrated in the drawing, it will be understood by one skilled in the art that various changes in detail may be affected therein without departing from the spirit and scope of the invention as defined by the claims.