METHOD FOR FABRICATION OF A CEM DEVICE

Abstract

Disclosed is a method for the fabrication of a correlated electron material (CEM) device comprising: forming a layer of a conductive substrate on a substrate; forming a layer of a correlated electron material on the layer of conductive substrate; forming a layer of a conductive overlay on the layer of correlated electron material; patterning these layers to form a stack comprising a conductive substrate, a CEM layer and a conductive overlay, on the substrate; forming a cover layer of an insulating material over the stack; and patterning the cover layer wherein: the patterning of the cover layer comprises etching a trench in the cover layer whereby to expose the conductive overlay; and the method further comprises treating the exposed conductive overlay to remove an oxidation layer there from.

Claims

1. A method for the fabrication of a correlated electron material (CEM) device comprising: forming a layer of a conductive substrate on a substrate; forming a layer of a correlated electron material on the layer of conductive substrate; forming a layer of a conductive overlay on the layer of correlated electron material; patterning these layers to form a stack comprising a conductive substrate, a CEM layer and a conductive overlay on the substrate; forming a cover layer of an insulating material over the stack; and patterning the cover layer wherein: the patterning of the cover layer comprises etching a trench in the cover layer whereby to expose the conductive overlay; and the method further comprises treating the exposed conductive overlay to remove an oxidation layer there from.

2. A method according to claim 1, wherein treating the exposed conductive overlay removes an oxidation layer from the upper surface and at least a part of the sidewalls of the exposed conductive overlay.

3. A method according to claim 1, wherein treating the exposed conductive overlay comprises sputtering the conductive overlay within the trench.

4. A method according to claim 1, wherein treating the exposed conductive overlay comprises exposing the conductive overlay to a reducing gas.

5. A method according to claim 4, wherein the reducing gas comprises an inert gas comprising one or more of hydrogen, ammonia or hydrazine.

6. A method according to claim 1, wherein treating the exposed conductive overlay comprises contacting it with a wet etchant which is specific for the oxidation layer.

7. A method according to claim 6, wherein the etchant comprises dilute hydrofluoric acid.

8. A method according to claim 1, further comprising depositing a moisture barrier layer over the stack prior to the forming of the cover layer.

9. A method according to claim 8, wherein the moisture barrier layer comprises one or more of silica, silicon nitride or silicon carbon nitride.

10. A method according to claim 1, further comprising depositing a metal barrier layer over the treated conductive overlay and the interior walls of the trench.

11. A method according to claim 10, wherein the metal barrier layer comprises one or more tantalum nitride, titanium nitride, cobalt, ruthenium and tantalum.

12. A method according to claim 10, further comprising depositing a metal interconnect in the trench and over the metal barrier layer whereby to substantially fill the trench.

13. An integrated circuit having a CEM device comprising a conductive substrate, a CEM layer and a conductive overlay wherein the device is provided between an upper metal interconnect provided in a cover layer and a lower metal interconnect provided in a substrate, the upper metal interconnect and the conductive overlay having a trench contact, wherein the contacting surface of the conductive overlay is substantially free from an oxidation layer.

14. An integrated circuit having a CEM device comprising a conductive substrate, a CEM layer and a conductive overlay wherein the device is provided between an upper metal interconnect provided in a cover layer and a lower metal interconnect provided in a substrate, the upper metal interconnect and the conductive overlay having a trench contact and the lower metal interconnect and the conductive substrate having a via contact, wherein the device has a moisture barrier layer on substantially the whole of the sidewalls of the conductive substrate and the CEM layer and on the sidewalls of the conductive overlay below and up to the trench contact.

15. An integrated circuit according to claim 13, wherein the lower metal interconnect and the conductive substrate have a via contact.

16. An integrated circuit according to claim 13, wherein a metal barrier layer is present between the conductive overlay and the upper metal interconnect.

17. An electronic device comprising an integrated circuit having a CEM device comprising a conductive substrate, a CEM layer and a conductive overlay wherein the device is provided between an upper metal interconnect provided in a cover layer and a lower metal interconnect provided in a substrate, the upper metal interconnect and the conductive overlay having a trench contact, wherein the contacting surface of the conductive overlay is substantially free from an oxidation layer.

18. An electronic device comprising an integrated circuit having a CEM device comprising a conductive substrate, a CEM layer and a conductive overlay wherein the device is provided between an upper metal interconnect provided in a cover layer and a lower metal interconnect provided in a substrate, the upper metal interconnect and the conductive overlay having a trench contact and the lower metal interconnect and the conductive substrate having a via contact, wherein the device has a moisture barrier layer on substantially the whole of the sidewalls of the conductive substrate and the CEM layer and on the sidewalls of the conductive overlay below and up to the trench contact.

19. An electronic device according to claim 17, wherein the lower metal interconnect and the conductive substrate have a via contact.

20. An electronic device according to claim 17, wherein a metal barrier layer is present between the conductive overlay and the upper metal interconnect.

Description

[0099] The method, fabricated CEM device and integrated circuit according to the present disclosure will now be described in more detail having regard to the following non-limiting embodiments and the accompanying drawings in which:

[0100] FIG. 1A shows a schematic illustration of a current density versus voltage profile of a CEM switching device;

[0101] FIG. 1B shows a schematic illustration of the CEM switching device of FIG. 1A;

[0102] FIG. 1C shows a schematic diagram of an equivalent circuit for the switching device;

[0103] FIGS. 2A and 2B are schematic illustrations showing the dry etching of a layer of conductive substrate, a layer of correlated electron material and a layer of conductive overlay to form a stack for a CEM switching device;

[0104] FIGS. 3A and 3B are schematic illustrations showing the forming of a trench in a cover layer of insulating material which has been provided over the stack whereby to expose the conductive overlay;

[0105] FIGS. 4A and 4B are schematic illustrations showing the removal of an oxidation layer formed on the upper surface and part of the sidewalls of a conductive overlay;

[0106] FIGS. 5A and 5B are schematic illustrations showing the formation of a metal barrier layer over the treated conductive overlay and at least the interior walls of the trench;

[0107] FIGS. 6A and 6B are schematic illustrations showing the deposition of a metal interconnect over the metal barrier layer whereby to substantially fill the trench; and

[0108] FIG. 7 is a flow diagram highlighting the steps for the removal of an oxidation layer which has formed on the upper surface and part of the sidewalls of a conductive overlay during the fabrication of a device.

[0109] Referring now to FIGS. 2A and 2B, there is shown a scheme generally illustrating the dry etching of a layer of a conductive substrate 202, a layer of a correlated electron material 204 and a layer of a conductive overlay 206 to from a stack, generally designated 250, comprising a conductive overlay 280, a CEM layer 270 and a conductive substrate 260 for a CEM switching device.

[0110] The CEM layer 270 may, in particular, comprise a doped nickel oxide NiO:C as described above. The conductive substrate 260 and the conductive layer 280 may each comprise a first (bulk) layer comprising tantalum nitride (TaN) and a second layer (liner) comprising iridium (not shown). The iridium layer in both the conductive overlay 280 and the conductive substrate 260 contacts the CEM layer 270.

[0111] Referring now to FIG. 2A, these layers are provided on a (FSG) glass (SiO.sub.2) plate 208 which is in turn disposed on a lower substrate 210 (comprising a low k) dielectric material) in which a lower copper interconnect 212 is provided. The dielectric material may comprise (FSG) silica (SiO.sub.2).

[0112] A silicon nitride (Si.sub.3N.sub.4) barrier layer 214 is provided between the substrate 210 and the glass plate 208. The glass plate 208 and the barrier layer 214 include a via 216 providing contact between the conductive substrate 202 and the copper interconnect 212.

[0113] A hard mask 218 comprising a layer of a silica (SiO.sub.2) is provided on the conductive overlay 206. The hard mask 218, which may be formed by a standard photolithographic process using a photoresist and reactive ion etching, defines the lateral dimensions of the (trapezoidal) CEM switching device.

[0114] Referring now to FIG. 2B, the dry etching (for example, reactive ion etching or deep reactive ion etching) results in a stack 250 which is ready for integration with a (FSG) glass (SiO.sub.2) cover layer.

[0115] Referring now to FIGS. 3A and 3B, there is shown the etching of a (FSG) glass cover layer 220 which has been deposited over the stack 250.

[0116] Referring to FIG. 3A, note that the deposition of the glass cover layer 220 is preceded by a deposition of a silicon nitride (Si.sub.3N.sub.4) moisture barrier layer 222 over the hard mask 218.

[0117] Referring now to FIG. 3B, the etching of the glass cover layer 220 results in a trench 226 having interior sidewalls 228 within which the conductive overlay 206 (in part) protrudes.

[0118] Note that the moisture barrier layer 222, is etched away at and around the upper surface of the conductive overlay during the etching of the cover layer 220.

[0119] Note also that the hard mask is removed during the etching of the cover layer 220 and that the conductive overlay 206 has an oxidation layer 224 on and around its upper surface which is formed during the etching of the cover layer 220.

[0120] Referring now to FIGS. 4A and 4B, there is shown the removal of the oxidation layer 224 by treatment of the exposed conductive overlay 206.

[0121] As mentioned above, the oxidation layer 224 of the conductive overlay 206 may be removed by re-sputtering the conductive overlay 206 within the trench 226 or by exposure of the conductive overlay 206 to a reducing gas, such as hydrogen (H.sub.2), nitrogen (N.sub.2) or ammonia (NH.sub.3), or by a wet cleaning chemical, such as dilute hydrofluoric acid (DHF).

[0122] The re-sputtering may be carried out in a chamber provided for the (subsequent step) deposition of the metal barrier layer.

[0123] Referring now to FIGS. 5A and 5B, there is shown the deposition of a metal barrier layer 230 over the conductive overlay 206, the bottom and at least the interior walls 228 of the trench 226.

[0124] Referring now to FIGS. 6A and 6B, there is shown the deposition of a copper interconnect 232 to fill the trench 226 and contact the conductive overlay 206 and the barrier layer 230.

[0125] Referring now to FIG. 7, there is shown a flow diagram illustrating a method for the fabrication of a device with removal of an oxidation layer on the conductive overlay which has formed during the processing.

[0126] As may be seen, the method provides that a trench is etched in an insulating cover layer for the device so as to expose the conductive overlay within the trench.

[0127] The exposed conductive overlay is subsequently treated to remove the oxidation layer that has formed on the conductive overlay because of the processing of the device (for example, from the etching of the trench in the cover layer).

[0128] The method includes the deposition of a metal barrier layer comprising, for example, titanium nitride or tantalum nitride, after the treatment to remove the oxidation layer of the conductive overlay.

[0129] The metal barrier layer, which coats the treated conductive overlay, the bottom of the trench and, at least, the interior side walls of the trench, prevents the ingress of moisture into the fabricated device.

[0130] The method further includes the deposition of a metal interconnect in the trench whereby to cover the coated conductive overlay and to fill the trench.