Multi-level signal transmitter and method thereof

Abstract

A multi-level signal transmitter includes an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.

Claims

1. A multi-level signal transmitter comprising: an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.

2. The multi-level signal transmitter of claim 1, wherein the input data is a serial bit stream comprising a plurality of bits that arrive sequentially, and at a present moment there is a present bit that has just arrived, a previous bit that precedes the present bit, an alternate previous bit that precedes the previous bit, and a next bit that succeeds the present bit.

3. The multi-level signal transmitter of claim 2, wherein the serial bit stream is encoded by the encoder to embody a FIR (finite impulse response) filter function.

4. The multi-level signal transmitter of claim 3, wherein the serial bit stream is encoded by the encoder to embody a 3-tap FIR filter function.

5. The multi-level signal transmitter of claim 4, wherein each of said plurality of logical signals of each of said plurality of logical signal sets is independently set to one of the following: the present bit, the previous bit, the next bit, a logical inversion of the present bit, a logical inversion of the previous bit, and a logical inversion of the next bit.

6. The multi-level signal transmitter of claim 3, wherein the serial bit stream is encoded by the encoder to embody a 4-tap FIR filter function.

7. The multi-level signal transmitter of claim 6, wherein each of said plurality of logical signals of each of said plurality of logical signal sets is independently set to one of the following: the present bit, the previous bit, the alternate previous bit, the next bit, a logical inversion of the present bit, a logical inversion of the previous bit, a logical inversion of the alternate previous bit, and a logical inversion of the next bit.

8. A method of multi-level signal transmission comprising: receiving input data; encoding the input data into a plurality of logical signal sets using an encoder, each of said plurality of logical signal sets comprising a plurality of logical signals; and using a plurality of tree-structured drivers to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structured drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.

9. The method of multi-level transmission of claim 8, wherein the input data is a serial bit stream comprising a plurality of bits that arrive sequentially, and at a present moment there is a present bit that has just arrived, a previous bit that precedes the present bit, an alternate previous bit that precedes the previous bit, and a next bit that succeeds the present bit.

10. The method of multi-level transmission of claim 9, wherein the serial bit stream is encoded by the encoder to embody a FIR (finite impulse response) filter function.

11. The method of multi-level transmission of claim 10, wherein the serial bit stream is encoded by the encoder to embody a 3-tap FIR filter function.

12. The method of multi-level transmission of claim 11, wherein each of said plurality of logical signals of each of said plurality of logical signal sets is independently set to one of the following: the present bit, the previous bit, the next bit, a logical inversion of the present bit, a logical inversion of the previous bit, and a logical inversion of the next bit.

13. The method of multi-level transmission of claim 10, wherein the serial bit stream is encoded by the encoder to embody a 4-tap FIR filter function.

14. The method of multi-level transmission of claim 13, wherein each of said plurality of logical signals of each of said plurality of logical signal sets is independently set to one of the following: the present bit, the previous bit, the alternate previous bit, the next bit, a logical inversion of the present bit, a logical inversion of the previous bit, a logical inversion of the alternate previous bit, and a logical inversion of the next bit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic diagram of a prior art multi-level signal transmitter.

(2) FIG. 2 shows a schematic diagram of a multi-level signal transmitter in accordance with an embodiment of the present disclosure.

(3) FIG. 3 shows a timing diagram of an input data to the multi-level signal transmitter of FIG. 2.

(4) FIG. 4 shows a flow diagram of a method of multi-level signal transmission in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THIS DISCLOSURE

(5) The present disclosure is directed to multi-level signal transmitter. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

(6) Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “circuit node,” “ground,” “inverter,” “voltage,” “load,” “logical signal,” “resistor,” “resistance,” and “impedance.” Terms and basic concepts like these, when used in a context of microelectronics, are apparent to those of ordinary skill in the art and thus will not be explained in detail here.

(7) Those of ordinary skills in the art can read schematics of a circuit comprising components such as inverters, resistors, and so on, and do not need a verbose description about how one component connects with another in the schematics. Those of ordinary skill in the art can recognize circuit symbols of inverter, resistor, and ground, and understand units such as Ohm and thus no explanations are needed of these.

(8) This disclosure is presented in an engineering sense, instead of a rigorous mathematical sense. For instance, “A is equal to B” means “a difference between A and B is smaller than an engineering tolerance. “X is zero” means “an absolute value of X is smaller than an engineering tolerance.” “A is substantially smaller than B” means a ratio between A and B is smaller than an engineering tolerance. In an embodiment, “A” is said to be substantially smaller than “B” when a ratio between “A” and “B” is less than 1/10.

(9) In this disclosure, a “circuit node” is frequently simply stated as a “node” for short, when what it means is clear from a context.

(10) A signal is a voltage of a variable level that carries a certain information and can vary with time. A level of the signal at a moment represents a state of the signal at that moment.

(11) A logical signal is a voltage signal of two states: a low state and a high state. The low state is also known as a “0” state, while the high stage is also known as a “1” state. Regarding a logical signal Q, “Q is high” or “Q is low” means that “Q is in the high state” or “Q is in the low state.” Likewise, “Q is 1” or “Q is 0” means that “Q is in the 1 state” or “Q is in the 0 state.”

(12) A first logical signal is said to be a logical inversion of a second logical signal if the first logical signal and the second logical signal always have opposite states. That is, when the first logical signal is 1, the second logical signal will be 0; when the first logical signal is 0, the second logical signal will be 1.

(13) A logical inversion of a logical signal Q can be mathematically expressed as “1−Q,” since when Q is 1, the logical inversion is 0, and when Q is 0, the logical inversion is 1.

(14) Throughout this disclosure, a ground node is a node of substantially zero voltage (0 V). A power supply node is a node of a substantially fixed voltage and is denoted by “V.sub.DD,” which is a convention widely used in the literature. In this disclosure, depending on a context that is apparent to those of ordinary skill in the art, sometimes “V.sub.DD” refers to the voltage level at the power supply node “V.sub.DD.” For instance, it is apparent that “V.sub.DD is 0.9V” means that the voltage level at the power supply node V.sub.DD is 0.9V.

(15) Throughout this disclosure, a label of a resistor may also be used to refer to a resistance of the resistor, depending on a context. For instance, “R.sub.0” is a label of a resistor, but it is clear from the context that in the mathematical expression “1/R.sub.0,” the “R.sub.0” term refers to a resistance of the resistor “R.sub.0.”

(16) A schematic diagram of a multi-level signal transmitter 200 in accordance with an embodiment of the present disclosure is shown in FIG. 2. Multi-level signal transmitter 200 comprises: an encoder ENC configured to receive an input data and output a plurality of logical signal sets D.sub.0, D.sub.1, D.sub.2, and so on; and a plurality of tree-structured drivers DR0, DR1, DR2, and so on, configured to receive said plurality of logical signal sets D.sub.0, D.sub.1, D.sub.2, and so on, respectively, and jointly establish an output voltage V.sub.out at an output node NOUT. The output node NOUT is terminated with a load R.sub.L that shunts the output node NOUT to ground. Each of said plurality of logical signal sets D.sub.0, D.sub.1, D.sub.2, and so on, comprises a plurality of logical signals. To be specific, D.sub.0 (D.sub.1, D.sub.2, . . . ) comprises logical signals D.sub.00 (D.sub.10, D.sub.20, . . . ), D.sub.01 (D.sub.11, D.sub.21, . . . ), D.sub.02 (D.sub.12, D.sub.22, . . . ), and so on. Each tree-structured driver comprises: a plurality of inverters configured to receive the logical signals of a respective logical signal set and establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of branch resistors, respectively; and a trunk resistor configured to couple the bifurcation node to the output node NOUT. To be more specific, tree-structured driver DR0 (DR1, DR2) comprises inverters I00 (I10, I20), I01 (I11, I21), I02 (I12, I22), and so on configured to receive logical signals D.sub.00 (D.sub.10, D.sub.20), D.sub.01 (D.sub.11, D.sub.21), D.sub.02 (D.sub.12, D.sub.22), and so on, respectively, and establish a joint voltage V.sub.0 (V.sub.1, V.sub.2) at a bifurcation node N0 (N1, N2) via coupling to the bifurcation node N0 (N1, N2) through branch resistors R.sub.00 (R.sub.10, R.sub.20), R.sub.01 (R.sub.11, R.sub.21), R.sub.02 (R.sub.12, R.sub.22), and so on, respectively, and a trunk resistor R.sub.0 (R.sub.1, R.sub.2) configured to couple the bifurcation node N0 (N1, N2) to the output node NOUT. Tree-structured driver DR0 (DR1, DR2) is said to have a tree structure, because when looking back from the output node NOUT it comprises the trunk resistor R.sub.0 (R.sub.1, R.sub.2) that branches into a plurality of branch resistors R.sub.00 (R.sub.10, R.sub.20), R.sub.01 (R.sub.11, R.sub.21), R.sub.02 (R.sub.12, R.sub.22), and so on at the bifurcation node N0 (N1, N2). Here, the terms “trunk” and “branch” pertain to description of topology, wherein a “trunk” branches into a plurality of “branches” that resembles a tree.

(17) In an embodiment, in tree-structured driver DR0, inverters I00, I01, I02, and so on, have output impedances that are substantially smaller than resistances of branch resistors R.sub.00, R.sub.01, R.sub.02, and so on, respectively, and the same condition also applies to tree-structured drivers DR1, DR2, and so on. Consequently, an impedance Z.sub.0 (Z.sub.1, Z.sub.2, . . . ) looking back into tree-structured driver DR0 (DR1, DR2, . . . ) from the output node NOUT can be written as:

(18) $\begin{array}{cc}{Z}_0\cong R_0+\frac{1}{\frac{1}{R_{00}}+\frac{1}{R_{01}}+\frac{1}{R_{02}}+.Math.}& \left(4\right)\end{array}$$\begin{array}{cc}{Z}_1\cong R_1+\frac{1}{\frac{1}{R_{10}}+\frac{1}{R_{11}}+\frac{1}{R_{12}}+.Math.}& \left(5\right)\end{array}$$\begin{array}{cc}{Z}_2\cong R_2+\frac{1}{\frac{1}{R_{20}}+\frac{1}{R_{21}}+\frac{1}{R_{22}}+.Math.}& \left(6\right)\end{array}$

(19) An output impedance Z.sub.s looking back into the multi-level signal transmitter 200 from the output node NOUT is:

(20) $\begin{array}{cc}{Z}_S=\frac{1}{\frac{1}{Z_0}+\frac{1}{Z_1}+\frac{1}{Z_2}+.Math.}& \left(7\right)\end{array}$

(21) Combining equations (4), (5), (6), and (7) we obtain

(22) $\begin{array}{cc}{Z}_S\cong \frac{1}{\begin{array}{c}\frac{1}{R_0+\frac{1}{\frac{1}{R_{00}}+\frac{1}{R_{01}}+\frac{1}{R_{02}}+.Math.}}+\\ \frac{1}{R_1+\frac{1}{\frac{1}{R_{10}}+\frac{1}{R_{11}}+\frac{1}{R_{12}}+.Math.}}+\frac{1}{R_2+\frac{1}{\frac{1}{R_{20}}+\frac{1}{R_{21}}+\frac{1}{R_{22}}+.Math.}}+.Math.\end{array}}& \left(8\right)\end{array}$

(23) In an embodiment, all trunk resistors and branch resistors are chosen such that Z.sub.S is approximately equal to R.sub.L, so that an impedance matching condition is met.

(24) Tree-structure driver DR0 performs a weighted sum of logical inversions of D.sub.00, D.sub.01, D.sub.02, and so on, wherein weights of logical inversions of D.sub.00, D.sub.01, D.sub.02, and so on are inversely proportional to resistances of branch resistors R.sub.00, R.sub.01, R.sub.02, and so on, respectively, and the weighted sum is represented by the joint voltage V.sub.0. The same thing can be said about tree-structured drivers DR1 and DR2 and thus is not explicitly described herein. This is a first level weighted sum, and all the branch resistors are said to be first-level weighting resistors.

(25) The joint voltages V.sub.0, V.sub.1, V.sub.2, and so on are summed in a weighted manner via trunk resistors R.sub.0, R.sub.1, R.sub.2, and so on, resulting in the output voltage V.sub.out, wherein the weights of the joint voltages V.sub.0, V.sub.1, V.sub.2, and so on are inversely proportional to the resistances of trunk resistors R.sub.0, R.sub.1, R.sub.2, and so on, respectively. This is a second level weighted sum, and all the trunk resistors are said to be second-level weighting resistors.

(26) All logical signals from all logical signal sets D.sub.0, D.sub.1, D.sub.2, and so on are thus summed in a two-level weighted sum manner: in the first level the weights are determined by the branch resistors, and then in the second level the weighs are determined by the trunk resistors. This way, all logical signals in all logical signal sets contribute to the output voltage V.sub.out, and each of them contributes with a weight that is determined in a two-level manner.

(27) Mathematically, we have:

(28) $\begin{array}{cc}{V}_{\mathrm{out}}=\frac{V_0{R}_t}{R_0}+\frac{V_1{R}_t}{R_1}+\frac{V_2{R}_t}{R_2}+.Math.\mathrm{where}& \left(9\right)\end{array}$$\begin{array}{cc}{R}_t=\frac{1}{\frac{1}{R_L}+\frac{1}{R_0}+\frac{1}{R_1}+\frac{1}{R_2}+.Math.}& \left(10\right)\end{array}$

(29) This is an equation for the second-level weighted sum. Also, we have:

(30) $\begin{array}{cc}{V}_0\cong V_{\mathrm{DD}}{R}_{t0}.Math.\left(\frac{1-D_{00}}{R_{00}}+\frac{1-D_{01}}{R_{01}}+\frac{1-D_{02}}{R_{02}}+.Math.\right)& \left(11\right)\end{array}$$\begin{array}{cc}{V}_1\cong V_{\mathrm{DD}}{R}_{t1}.Math.\left(\frac{1-D_{10}}{R_{10}}+\frac{1-D_{11}}{R_{11}}+\frac{1-D_{12}}{R_{12}}+.Math.\right)& \left(12\right)\end{array}$$\begin{array}{cc}{V}_2\cong V_{\mathrm{DD}}{R}_{t2}.Math.\left(\frac{1-D_{20}}{R_{20}}+\frac{1-D_{21}}{R_{21}}+\frac{1-D_{22}}{R_{22}}+.Math.\right)\mathrm{where}& \left(13\right)\end{array}$$\begin{array}{cc}{R}_{t0}=\frac{1}{\frac{1}{\frac{1}{\frac{1}{R_L}+\frac{1}{Z_S}-\frac{1}{Z_0}}+R_0}+\frac{1}{R_{00}}+\frac{1}{R_{01}}+\frac{1}{R_{02}}+.Math.}& \left(14\right)\end{array}$$\begin{array}{cc}{R}_{t1}=\frac{1}{\frac{1}{\frac{1}{\frac{1}{R_L}+\frac{1}{Z_S}-\frac{1}{Z_1}}+R_1}+\frac{1}{R_{10}}+\frac{1}{R_{11}}+\frac{1}{R_{12}}+.Math.}& \left(15\right)\end{array}$$\begin{array}{cc}{R}_{t2}=\frac{1}{\frac{1}{\frac{1}{\frac{1}{R_L}+\frac{1}{Z_S}-\frac{1}{Z_2}}+R_2}+\frac{1}{R_{20}}+\frac{1}{R_{21}}+\frac{1}{R_{22}}+.Math.}& \left(16\right)\end{array}$

(31) Here, “V.sub.DD” is a power supply voltage for all inverters in the multi-level signal transmitter 200.

(32) An advantage of using a tree-structure driver is that an accuracy of a level of the output voltage V.sub.out is improved due to using the two-level weighted sum. Since the trunk resistor R.sub.0 is common to all logical signals in the logical signal set D.sub.0, there is no mismatch among all logical signals in the logical signal set D.sub.0 in the second level weighted sum. The same thing can be said about logical signal sets D.sub.1 and D.sub.2. The inaccuracy is thus limited to mismatches among branch resistors R.sub.00, R.sub.01, R.sub.02, and so on. The same thing can be said about logical signal sets D.sub.1, D.sub.2, and so on.

(33) Another advantage is that a total sum of all resistance values from all resistors is reduced, compared to the case in the prior art that has no trunk resistor, thanks to re-using the trunk resistor that is common to all branches.

(34) In an embodiment, the input data is a serial bit stream X.sub.0, X.sub.1, X.sub.2, X.sub.3, and so on that arrives sequentially, as illustrated by a timing diagram shown in FIG. 3. At a present moment, there is a present bit X.sub.i that has just arrived, wherein i is a time index corresponding to the present moment, a previous bit X.sub.i−1 that precedes the present bit X.sub.i, an alternate previous bit X.sub.i−2 that precedes the previous bit X.sub.i−1, and a next bit X.sub.i+1 that succeeds the present bit X.sub.i. In an embodiment, the serial bit stream X.sub.0, X.sub.i, X.sub.2, X.sub.3, and so on, is encoded by the encoder ENC into the logical signal sets D.sub.0, D.sub.1, D.sub.2, and so on, to embody a FIR (finite impulse response) filter. In an embodiment, a 3-tap FIR filter is embodied, wherein the 3-tap FIR filter comprises a precursor tap, a main tap, and a post-cursor tap, and each logical signal in any one of logical signal sets D.sub.0, D.sub.1, D.sub.2, and so on, can be independently set to one of X.sub.i−1, 1−X.sub.i−1, X.sub.i, 1−X.sub.i, X.sub.i+1, and 1−X.sub.i+1, to embody a post-cursor tap, a negative post-cursor tap, a main tap, a negative main tap, a precursor tap, and a negative precursor tap, respectively. In many applications, the main tap is always positive, while the precursor tap and the post-cursor tap are always negative; in this case, each logical signal in any one of logical signal sets D.sub.0, D.sub.1, D.sub.2, and so on, can be independently set to one of 1−X.sub.i−1, X.sub.i, and 1−X.sub.i+1. Concepts of “FIR filter,” “precursor tap,” “main tap,” and “post-cursor tap,” are well understood by those of ordinary skill in the art and thus not explained in detail herein.

(35) In another embodiment, a 4-tap FIR filter is embodied, wherein the 4-tap FIR filter comprises a precursor tap, a main tap, a first post-cursor tap, and a second post-cursor tap, and each logical signal in any one of logical signal sets D.sub.0, D.sub.1, D.sub.2, and so on, can be independently set to one of X.sub.i−2, 1−X.sub.i−2, X.sub.i−1, 1−X.sub.i−1, X.sub.i, 1−X.sub.i, X.sub.i+1, and 1−X.sub.i+1, to embody a second post-cursor tap, a negative second post-cursor tap, a first post-cursor tap, a negative first post-cursor tap, a main tap, a negative main tap, a precursor tap, and a negative precursor tap, respectively.

(36) By way of example but not limitation: R.sub.L is 50 Ohm; V.sub.DD is 0.9V; there are four tree-structured drivers DR0, DR1, DR2, and DR3 that comprise four chunk resistors R.sub.0, R.sub.1, R.sub.2, and R.sub.3, respectively; all the four chunk resistors are 100 Ohm; each of the four tree-structured drivers has four branch resistors and thus there are totally sixteen branch resistors R.sub.00, R.sub.01, R.sub.02, R.sub.03, R.sub.10, R.sub.11, R.sub.12, R.sub.13, R.sub.20, R.sub.21, R.sub.22, R.sub.23, R.sub.30, R.sub.31, R.sub.32, and R.sub.33, and all the sixteen branch resistors are 400 Ohm; DR0, DR1, DR2, and DR3 receive logical signal sets D.sub.0, D.sub.1, D.sub.2, and D.sub.3, respectively; D.sub.0 comprises four logical signals D.sub.00, D.sub.01, D.sub.02, and D.sub.03; D.sub.1 comprises four logical signals D.sub.10, D.sub.11, D.sub.12, and D.sub.13; D.sub.2 comprises four logical signals D.sub.20, D.sub.21, D.sub.22, and D.sub.23; D.sub.3 comprises four logical signals D.sub.30, D.sub.31, D.sub.32, and D.sub.33; there are totally sixteen logical signals and they are encoded from the serial bit stream X.sub.0, X.sub.1, X.sub.2, X.sub.3, . . . , in accordance with the following equations:
D.sub.00=D.sub.10=D.sub.20=D.sub.30=1−X.sub.i−1  (17)
D.sub.01=D.sub.11=D.sub.21=D.sub.31=X.sub.i  (18)
D.sub.02=D.sub.12=D.sub.22=D.sub.32=X.sub.i  (19)
D.sub.03=D.sub.13=D.sub.23=D.sub.33=1−X.sub.i+1  (20)

(37) For i=1, 2, 3, 4, . . . , and so on. This embodies a 3-tap FIR comprising a precursor tap, a main tap, and a post-cursor tap that can be mathematically modeled by a z-transform transfer function:
H(z)=[−1/4.Math.z+1/2−1/4.Math.z.sup.−1].Math.z.sup.−1  (21)

(38) Inside the bracket on the right-hand side of equation (21): the first term “−1/4.Math.z” is a negative precursor tap pertaining to the next bit X.sub.i+1 and embodied by D.sub.03, D.sub.13, D.sub.23, and D.sub.33; the second term “1/2” is a main tap pertaining to the present bit X.sub.i and embodied by D.sub.01, D.sub.11, D.sub.21, D.sub.31, D.sub.02, D.sub.12, D.sub.22, and D.sub.32; and the third term “−1/4.Math.z.sup.−1” is a negative post-cursor tap pertaining to the previous bit X.sub.i−1 and embodied by D.sub.00, D.sub.10, D.sub.20, and D.sub.30. Out of the totally sixteen logical signals, four of them are set to 1−X.sub.i−1, so the post-cursor tap coefficient is − 4/16 (i.e. −¼); eight of them are set to X.sub.i, so the main tap coefficient is 8/16 (i.e. ½); and four of them are set to 1−X.sub.i+1, so the precursor tap coefficient is − 4/16 (i.e. −¼). A larger post-cursor tap is realized by assigning the previous bit X.sub.i−1 (or its logical inversion 1−X.sub.i−1 if the post-cursor tap is negative) to more logical signals, while a larger precursor tap is realized by assigning the next bit X.sub.i+1 (or its logical inversion 1−X.sub.i+1 if the precursor tap is negative) to more logical signals. Those skilled in the art can extend the same concept to embody FIR filter of four or more taps.

(39) Inverters are well known in the prior art and thus not described in detail.

(40) As shown in a flow diagram 300 depicted in FIG. 4, a method of multi-level signal transmission in accordance with an embodiment of the present disclosure comprises: (step 410) receiving an input data; (step 420) encoding the input data into a plurality of logical signal sets using an encoder, each of said plurality of logical signal sets comprising a plurality of logical signals; and (step 430) using a plurality of tree-structured drivers to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.

(41) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.