Polyphase filter and filter circuit

Abstract

Provided is a polyphase filter, which is capable of achieving amplitude matching and phase matching while achieving a low insertion loss with a single-stage configuration. A first variable resistor and a second variable resistor have resistance values that are equal to each other, and the resistance values are set so as to correct an amplitude error between orthogonal signals of outputs of a first output terminal to a fourth output terminal. A first variable capacitor, a second variable capacitor, a third variable capacitor, and a fourth variable capacitor have capacitance values that are equal to one another, and the capacitance values are set so as to correct a phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal.

Claims

1. A polyphase filter, comprising: a first fixed resistor, which has one end connected to a first input terminal, and another end connected to a first output terminal; a first variable resistor, which has one end connected to the first input terminal, and another end connected to a second output terminal; a second fixed resistor, which has one end connected to a second input terminal, and another end connected to a third output terminal; a second variable resistor, which has one end connected to the second input terminal, and another end connected to a fourth output terminal; a first variable capacitor, which has one end connected to the second input terminal, and another end connected to the first output terminal; a second variable capacitor, which has one end connected to the first input terminal, and another end connected to the second output terminal; a third variable capacitor, which has one end connected to the first input terminal, and another end connected to the third output terminal; and a fourth variable capacitor, which has one end connected to the second input terminal, and another end connected to the fourth output terminal, the first variable resistor and the second variable resistor having resistance values that are equal to each other, the resistance values being set so as to correct an amplitude error between orthogonal signals of outputs of the first output terminal to the fourth output terminal, the first variable capacitor, the second variable capacitor, the third variable capacitor, and the fourth variable capacitor having capacitance values that are equal to one another, the capacitance values being set so as to correct a phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal.

2. A filter circuit, which uses the polyphase filter of claim 1, the filter circuit comprising: an amplitude comparison circuit, which is configured to compare amplitudes between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal to detect an amplitude error; a first arithmetic circuit, which is configured to calculate the resistance values of the first variable resistor and the second variable resistor so as to correct the amplitude error; an phase comparison circuit, which is configured to compare phases between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal to detect a phase error; and a second arithmetic circuit, which is configured to calculate, after the resistance values of the first variable resistor and the second variable resistor are set, the capacitance values of the first variable capacitor, the second variable capacitor, the third variable capacitor, and the fourth variable capacitor so as to correct the phase error.

3. A filter circuit, which uses the polyphase filter of claim 1, the filter circuit comprising: a vector sum phase shifter, to which the outputs of the first output terminal to the fourth output terminal are to be input, and which is configured to synthesize orthogonal signals to output the synthesized signals; a phase detection circuit, which is configured to detect phases of the synthesized signals from the vector sum phase shifter; a phase control circuit, which is configured to output a control signal to the vector sum phase shifter based on an input phase set value; a phase comparison circuit, which is configured to compare an output value from the phase detection circuit to the phase set value, which is set in the vector sum phase shifter; and an arithmetic circuit, which is configured to calculate an amplitude error and a phase error of the polyphase filter based on a comparison result of the phase comparison circuit, and to calculate the resistance values of the first variable resistor and the second variable resistor, and the capacitance values of the first variable capacitor, the second variable capacitor, the third variable capacitor, and the fourth variable capacitor using the calculated amplitude error and the calculated phase error.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a circuit diagram for illustrating a problem of a related-art polyphase filter.

(2) FIG. 2 is a partial circuit diagram for illustrating the problem of the related-art polyphase filter.

(3) FIG. 3 is a graph for showing the problem of the related-art polyphase filter.

(4) FIG. 4 is a circuit diagram for illustrating a problem of another related-art polyphase filter.

(5) FIG. 5 is a circuit diagram for illustrating a filter circuit using a polyphase filter according to Embodiment 1 of the present invention.

(6) FIG. 6 is a graph for showing an effect of the filter circuit using the polyphase filter according to Embodiment 1 of the present invention.

(7) FIG. 7 is a graph for showing another effect of the filter circuit using the polyphase filter according to Embodiment 1 of the present invention.

(8) FIG. 8 is a circuit diagram for illustrating a filter circuit using a polyphase filter according to Embodiment 2 of the present invention.

DESCRIPTION OF EMBODIMENTS

(9) A description is now given of a polyphase filter and a filter circuit according to preferred embodiments of the present invention with reference to the drawings, and throughout the drawings, like or corresponding components are denoted by like reference symbols to describe those components.

(10) Before the embodiments of the present invention are described, problems inherent in the above-mentioned related-art polyphase filters are described first in detail with reference to FIG. 1 to FIG. 4. FIG. 1 to FIG. 3 relate to the polyphase filter of Non Patent Literature 1, and FIG. 4 relates to the polyphase filter of Patent Literature 1.

(11) FIG. 1 is a circuit diagram for illustrating a problem of a related-art polyphase filter. In FIG. 1, the polyphase filter includes four fixed resistors R.sub.0 and four varactors C.sub.0.

(12) Moreover, differential signals are input to a first input terminal and a second input terminal. Of orthogonal signals to be output, I differential signals are output from a first output terminal and a third output terminal, and Q differential signals are output from a second output terminal and a fourth output terminal. Depending on variations in process, temperature, and the like, a phase error may be generated between the orthogonal signals to be output.

(13) The phase error may be corrected by adjusting capacitance values of the varactors C.sub.0. However, the varactors C.sub.0 have a characteristic of a reduced Q value especially in a high-frequency range. Therefore, in the high-frequency range, there apparently occurs a condition equivalent to a configuration in which a series resistor r is connected to the varactor C.sub.0 as illustrated in FIG. 2. Therefore, there is a problem in that an amplitude error may be generated between the orthogonal signals to be output.

(14) For example, when a Q value of the varactor C.sub.0 is as low as 10 at 10 GHz, it is considered to be equivalent to a configuration in which the resistor r=5 is connected in series to the varactor C.sub.0. Here, as shown in FIG. 3, when the phase error is set to 0 deg at 10 GHz, the I/Q orthogonal signals have an amplitude error of 0 dB when r=0, but the I/Q orthogonal signals have an amplitude error of 0.9 dB when r=5.

(15) As described above, with the related-art polyphase filter having the single-stage configuration illustrated in FIG. 1, although the phase error is corrected by adjusting the capacitance values of the varactors C.sub.0 while fixing resistance values, there is a problem in that the amplitude error cannot be corrected.

(16) FIG. 4 is a circuit diagram for illustrating a problem of a related-art polyphase filter. In FIG. 4, the polyphase filter includes two variable resistors R.sub.0, two variable resistors R.sub.0, and four fixed capacitors C.sub.0.

(17) Here, a case is assumed in which differential input signals to a second input terminal and a fourth input terminal have amplitudes that are (1+) times larger than amplitudes of differential input signals to a first input terminal and a third input terminal, where represents an amplitude error, and in which a phase error therebetween is 90 degrees.

(18) The amplitude error can be corrected by setting resistance values of the variable resistors R.sub.0 to one over (1+) times the resistance values in a case where there is no amplitude error, and setting resistance values of the variable resistors R.sub.0 to (1+) times the resistance values in the case where there is no amplitude error without changing the fixed capacitors C.sub.0.

(19) The above-mentioned control can be performed when the following expressions are satisfied: .sub.0C.sub.0R.sub.0=1/(1+) and .sub.0C.sub.0R.sub.0=1+, where .sub.0 represents an angular frequency of an IF signal, and hence the control cannot be performed unless the capacitors C.sub.0 or the resistors R.sub.0 are fixed.

(20) As described above, with the related-art polyphase filter having the single-stage configuration illustrated in FIG. 4, only the amplitude error is corrected by adjusting the resistance values of the variable resistors while fixing the capacitance values, and there is a problem in that the phase error cannot be corrected.

(21) Moreover, it can be considered to combine the related-art polyphase filter illustrated in FIG. 1 and the related-art polyphase filter illustrated in FIG. 4 to reduce the amplitude error and the phase error to 0, to thereby achieve amplitude matching and phase matching. However, the polyphase filter has a two-stage configuration, and there is a problem in that a low insertion loss cannot be achieved.

(22) In view of the above-mentioned problems, in the following embodiments, a description is given of a polyphase filter capable of achieving amplitude matching and phase matching while achieving the low insertion loss with a single-stage configuration, and a filter circuit using the polyphase filter.

Embodiment 1

(23) FIG. 5 is a circuit diagram for illustrating a filter circuit using a polyphase filter according to Embodiment 1 of the present invention. In FIG. 5, a filter circuit 100 includes a polyphase filter 11, an amplitude comparison circuit 12, a first arithmetic circuit 13, a phase comparison circuit 14, and a second arithmetic circuit 15.

(24) The polyphase filter 11 includes two fixed resistors R.sub.1: a first fixed resistor and a second fixed resistor, two variable resistors R.sub.2: a first variable resistor and a second variable resistor, and four variable capacitors C.sub.1: a first variable capacitor, a second variable capacitor, a third variable capacitor, and a fourth variable capacitor.

(25) Moreover, the first fixed resistor R.sub.1 has one end connected to a first input terminal, and another end connected to a first output terminal. The first variable resistor R.sub.2 has one end connected to the first input terminal, and another end connected to a second output terminal. The second fixed resistor R.sub.1 has one end connected to a second input terminal, and another end connected to a third output terminal. The second variable resistor R.sub.2 has one end connected to the second input terminal, and another end connected to a fourth output terminal.

(26) Moreover, the first variable capacitor C.sub.1 has one end connected to the second input terminal, and another end connected to the first output terminal. The second variable capacitor C.sub.1 has one end connected to the first input terminal, and another end connected to the second output terminal. The third variable capacitor C.sub.1 has one end connected to the first input terminal, and another end connected to the third output terminal. The fourth variable capacitor C.sub.1 has one end connected to the second input terminal, and another end connected to the fourth output terminal.

(27) Here, the first variable resistor R.sub.2 and the second variable resistor R.sub.2 have resistance values that are equal to each other, and the resistance values are set so as to correct the amplitude error between orthogonal signals of outputs of the first output terminal to the fourth output terminal. Moreover, the first variable capacitor C.sub.1, the second variable capacitor C.sub.1, the third variable capacitor C.sub.1, and the fourth variable capacitor C.sub.1 have capacitance values that are equal to one another, and the capacitance values are set so as to correct the phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal. As a result, the polyphase filter 11 forms an amplitude phase matching type polyphase filter.

(28) The amplitude comparison circuit 12 receives, as inputs, orthogonal signals output from the third output terminal and the fourth output terminal, and outputs a signal indicating a comparison result to the first arithmetic circuit 13. The first arithmetic circuit 13 receives, as an input, the signal from the amplitude comparison circuit 12, and outputs control signals to the first variable resistor R.sub.2 and the second variable resistor R.sub.2.

(29) The phase comparison circuit 14 receives, as inputs, orthogonal signals output from the first output terminal and the second output terminal, and outputs a signal indicating a comparison result to the second arithmetic circuit 15. The second arithmetic circuit 15 receives, as an input, the signal from the phase comparison circuit 14, and outputs control signals to the first variable capacitor C.sub.1, the second variable capacitor C.sub.1, the third variable capacitor C.sub.1, and the fourth variable capacitor C.sub.1.

(30) Now, operation of the filter circuit 100 having the above-mentioned configuration is described.

(31) The amplitude comparison circuit 12 detects the amplitude error based on the orthogonal signals output from the third output terminal and the fourth output terminal. Here, the amplitude error is a value that varies dynamically due to a variation in input signal, a variation in temperature, a variation in process, and other factors, and =0 when ideal differential signals are input to the input terminals.

(32) The first arithmetic circuit 13 optimizes the first variable resistor R.sub.2 and the second variable resistor R.sub.2 using the amplitude error detected by the amplitude comparison circuit 12. At this time, when it is assumed that the variable capacitors C.sub.1 have a low Q value, and that there occurs a condition equivalent to a condition in which the series resistor r is connected, a relationship of the following expression (1) is established between the amplitude error and the variable resistors R.sub.2.
=/[{(r/R.sub.1).sup.2+(R.sub.2/r).sup.2}/2]1(1)

(33) In the expression (1), in a range in which the amplitude error is close to 0, the amplitude error exhibits a monotonously increasing characteristic with respect to the variable resistors R.sub.2. In other words, the first arithmetic circuit 13 can cause values of the variable resistors R.sub.2 to converge by repeatedly controlling the values such that the amplitude error becomes 0.

(34) The phase comparison circuit 14 detects a phase error based on the orthogonal signals output from the first output terminal and the second output terminal. Here, the phase error is a value that varies dynamically due to a variation in input signal, a variation in temperature, a variation in process, and other factors, and =0 when ideal differential signals are input to the input terminals.

(35) The second arithmetic circuit 15 optimizes the first variable capacitor C.sub.1, the second variable capacitor C.sub.1, the third variable capacitor C.sub.1, and the fourth variable capacitor C.sub.1 using the phase error detected by the phase comparison circuit 14. At this time, a relationship of the following expression (2) is established between the phase error and the variable capacitors C.sub.1.
tan ={(C.sub.1).sup.2R.sub.1R.sub.2+1}/{(C.sub.1).sup.2R.sub.1R.sub.21}(2)

(36) In other words, the second arithmetic circuit 15 can cause values of the variable capacitors C.sub.1 to converge by repeatedly controlling the values such that the phase error becomes 0. Here, as shown in the expression (1), the amplitude error does not depend on the variable capacitors C.sub.1, and hence controlling the variable capacitors C.sub.1 such that =0 does not affect the amplitude error .

(37) Those procedures of optimizing the variable resistors R.sub.2 and the variable capacitors C.sub.1 are performed depending on the amplitude error that varies dynamically, and hence the variable resistors R.sub.2 and the variable capacitors C.sub.1 also vary dynamically.

(38) FIG. 6 and FIG. 7 are graphs for showing effects of the filter circuit using the polyphase filter according to Embodiment 1 of the present invention. An amplitude error characteristic is shown in FIG. 6, and a phase error characteristic is shown in FIG. 7.

(39) In FIG. 6 and FIG. 7, it is assumed, for example, that the following characteristics: an amplitude error of 1.9 dB and a phase error of 5.6 deg are obtained at 10 GHz for an element constant (before adjustment). Here, when the variable resistors R.sub.2 and the variable capacitors C.sub.1 are controlled by the above-mentioned method, as shown in FIG. 6 and FIG. 7, the following correction results was able to be obtained: the amplitude error of 0 dB, and the phase error of 0 deg (phase error of 90 deg).

(40) As described above, the polyphase filter 11 achieves amplitude matching of I/Q orthogonal signals by comparing the amplitude error between the orthogonal signals at the output terminals in the amplitude comparison circuit 12, and adjusting the variable resistors R.sub.2 so as to correct the amplitude error, and achieves phase matching of the I/Q orthogonal signals by comparing the phase error between the orthogonal signals at the output terminals in the phase comparison circuit 14, and adjusting the variable capacitors C.sub.1 so as to correct the phase error. Moreover, amplitude matching and phase matching can be achieved at the same time by performing the control through the above-mentioned procedure.

(41) As described above, according to Embodiment 1, in the polyphase filter, the first variable resistor and the second variable resistor have the resistance values that are equal to each other, and the resistance values are set so as to correct the amplitude error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal. Moreover, the first variable capacitor, the second variable capacitor, the third variable capacitor, and the fourth variable capacitor have the capacitance values that are equal to one another, and the capacitance values are set so as to correct the phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal.

(42) Therefore, amplitude matching and phase matching can be achieved while achieving the low insertion loss with the single-stage configuration.

Embodiment 2

(43) FIG. 8 is a circuit diagram for illustrating a filter circuit using a polyphase filter according to Embodiment 2 of the present invention. In FIG. 8, a filter circuit 100A includes a polyphase filter 11, a vector sum phase shifter 21, a phase detection circuit 22, a phase comparison circuit 23, an arithmetic circuit 24, and a phase control circuit 25.

(44) The polyphase filter 11 is an amplitude phase matching type polyphase filter having the same configuration as that described above in Embodiment 1, and has an input side connected to input terminals 111 and 112, and an output side connected to output terminals 113 to 116. Four orthogonal differential signals are output from the output terminals 113 to 116, and are branched to be input to the vector sum phase shifter 21.

(45) The vector sum phase shifter 21 includes a VGA_I 211 and a VGA_Q 212. The term VGA stands for variable gain amplifier. The VGA_211 and the VGA_Q 212 receive, as inputs, I/Q orthogonal differential signals from the polyphase filter 11 and control signals from the phase control circuit 25, synthesize the orthogonal signals, and output the synthesized signals to the phase detection circuit 22.

(46) The phase detection circuit 22 has an input side connected to an output side of the vector sum phase shifter 21, and the phase detection circuit 22 has an output side connected to an input side of the phase comparison circuit 23. Moreover, the phase comparison circuit 23 has the input side connected to the output side of the phase detection circuit 22, and the phase comparison circuit 23 has an output side connected to an input side of the arithmetic circuit 24.

(47) The arithmetic circuit 24 has the input side connected to the output side of the phase comparison circuit 23, and the arithmetic circuit 24 has an output side connected to the polyphase filter 11. Moreover, the phase control circuit 25 has an input side connected to the output side of the arithmetic circuit 24, and the phase control circuit 25 has an output side connected to the phase comparison circuit 23, the VGA_I 211, and the VGA_Q 212.

(48) Here, the arithmetic circuit 24 receives, as inputs, signals from the phase comparison circuit 23, outputs control signals to the polyphase filter 11, and also outputs a control signal to the phase control circuit 25. Moreover, the phase control circuit 25 outputs control signals not only to the VGA_I 211 and the VGA_Q 212, but also to the phase comparison circuit 23.

(49) Now, operation of the filter circuit 100A having the above-mentioned configuration is described.

(50) The polyphase filter 11 converts differential signals, which are input from the input terminals 111 and 112, into the I/Q orthogonal differential signals. Here, it is assumed that an amplitude error and a phase error are generated due to an element variation of the polyphase filter 11.

(51) The amplitude error and the phase error are values that vary dynamically due to a variation in input signal, a variation in temperature, a variation in process, and other factors, and =0 and =0 when ideal differential signals are input to the input terminals. Moreover, the amplitude error and the phase error are corrected by a loop formed of the vector sum phase shifter 21, the arithmetic circuit 24, and other such components, which is to be described later. The specific correction procedure proceeds as follows.

(52) First, the arithmetic circuit 24 sweeps a phase shift amount of the vector sum phase shifter 21 at a plurality of points of from 0 to 360. Moreover, the vector sum phase shifter 21 is operated in accordance with phase set values for the VGAs, which are given through the phase control circuit 25, to thereby determine phases of outputs. However, the amplitude error and the phase error are generated in the polyphase filter 11 as described above, and hence the phases of the output signals include errors from the phase set values.

(53) Subsequently, the amplitude error and the phase error are detected by the phase detection circuit 22 and the phase comparison circuit 23. Here, a comparison result of the phase comparison circuit 23 may be input to the arithmetic circuit 24 to determine error characteristics of the vector sum phase shifter 21, and the amplitude error and the phase error of the polyphase filter 11 can be calculated through inverse operation based on the error characteristics.

(54) Next, using the calculated amplitude error and the calculated phase error , values of the variable resistors R.sub.2 and the variable capacitors C.sub.1 of the polyphase filter 11 are optimized by the method described above in Embodiment 1. As a result, the amplitude error and the phase error of the polyphase filter 11 can be corrected.

(55) Those procedures of optimizing the variable resistors R.sub.2 and the variable capacitors C.sub.1 are performed depending on the amplitude error that varies dynamically, and hence the variable resistors R.sub.2 and the variable capacitors C.sub.1 also vary dynamically.

(56) As described above, according to Embodiment 2, in the polyphase filter, the first variable resistor and the second variable resistor have the resistance values that are equal to each other, and the resistance values are set so as to correct the amplitude error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal. Moreover, the first variable capacitor, the second variable capacitor, the third variable capacitor, and the fourth variable capacitor have the capacitance values that are equal to one another, and the capacitance values are set so as to correct the phase error between the orthogonal signals of the outputs of the first output terminal to the fourth output terminal.

(57) Therefore, amplitude matching and phase matching can be achieved while achieving the low insertion loss with the single-stage configuration.