Manufacturing method of circuit board

Abstract

A manufacturing method of a circuit board and a stamp are provided. The method includes: forming a circuit pattern and a dielectric layer on a dielectric substrate; forming a conductive via in the dielectric layer; forming a thermal-sensitive adhesive layer on the dielectric layer; forming a photoresist material layer on the thermal-sensitive adhesive layer; imprinting the photoresist material layer using a stamp, wherein a first conductive layer is disposed on the surface of the pressing side of the stamp, a second conductive layer is disposed on the surface of the other portions; applying a current to the stamp; removing the stamp and the photoresist material layer and the thermal-sensitive adhesive layer below the pressing side to form a patterned photoresist layer and thermal-sensitive adhesive layer; forming a patterned metal layer on the region exposed by the patterned photoresist layer; removing the patterned photoresist layer and thermal-sensitive adhesive layer.

Claims

1. A manufacturing method of a circuit board, comprising: providing a dielectric substrate, wherein a circuit pattern, a dielectric layer covering the circuit pattern, and a conductive via located in the dielectric layer and connected to the circuit pattern are disposed on the dielectric substrate; forming a thermal-sensitive adhesive layer on the dielectric layer; forming a photoresist material layer on the thermal-sensitive adhesive layer; performing imprinting on the photoresist material layer via a stamp, wherein a first conductive layer is disposed on a surface of a pressing side of the stamp facing the circuit pattern, a second conductive layer is disposed on a surface of other portions of the stamp, and a resistance of the first conductive layer is greater than a resistance of the second conductive layer; applying a current to the stamp; removing the stamp and the photoresist material layer and the thermal-sensitive adhesive layer below the pressing side to form a patterned photoresist layer and a patterned thermal-sensitive adhesive layer; forming a patterned metal layer on a region exposed by the patterned photoresist layer; removing the patterned photoresist layer; heating the patterned thermal-sensitive adhesive layer to reduce the adhesion of the patterned thermal-sensitive adhesive layer; and after heating the patterned thermal-sensitive adhesive layer, removing the patterned thermal-sensitive adhesive layer.

2. The manufacturing method of the circuit board of claim 1, wherein the photoresist material layer is a negative photoresist material layer, and after the current is applied to the stamp and before the photoresist material layer and the thermal-sensitive adhesive layer below the pressing side are removed, the method further comprises performing exposure on the photoresist material layer.

3. The manufacturing method of the circuit board of claim 1, wherein the photoresist material layer is a positive photoresist material layer, and after the current is applied to the stamp, the photoresist material and the thermal-sensitive adhesive layer below the pressing side are directly removed.

4. The manufacturing method of the circuit board of claim 1, wherein after the current is applied to the stamp, a temperature of the first conductive layer is higher than 100 C. to reduce an adhesion of the thermal-sensitive adhesive layer below the pressing side.

5. The manufacturing method of the circuit board of claim 1, further comprising, after the conductive via is formed and before the thermal-sensitive adhesive layer is formed, forming a conductive seed layer on the dielectric layer and the conductive via, and further comprising, after the patterned thermal-sensitive adhesive layer is removed, removing the conductive seed layer below the patterned thermal-sensitive adhesive layer.

6. The manufacturing method of the circuit board of claim 1, further comprising, before the patterned thermal-sensitive adhesive layer is removed, performing UV irradiation, laser irradiation, or infrared heating on the patterned thermal-sensitive adhesive layer.

7. The manufacturing method of the circuit board of claim 1, wherein the patterned thermal-sensitive adhesive layer is removed by applying a mechanical force.

8. A stamp for imprinting a photoresist material layer, the stamp comprising: a body having a pressing side facing the photoresist material layer; a body having a circuit-forming intaglio pattern disposed on a side of the body facing the photoresist material layer, the side with the circuit-forming intaglio pattern of the body being the pressing side for patterning the photoresist material layer; a first conductive layer disposed on a portion of an outmost surface of the body on the pressing side; and a second conductive layer disposed on another portion of the outmost surface of the body on the pressing side, wherein a resistance of the first conductive layer is greater than a resistance of the second conductive layer, and a resistance of the body is greater than a resistance of the first conductive layer.

9. The stamp of claim 8, wherein a material of the body comprises a polymer material.

10. The stamp of claim 8, wherein when a current passes through the first conductive layer and the second conductive layer, a temperature of the first conductive layer is higher than a temperature of the second conductive layer.

11. The stamp of claim 8, wherein the body is an insulating body.

12. The stamp of claim 8, wherein the first conductive layer does not overlap the second conductive layer in a direction parallel to a normal vector of the outmost surface of the body on the pressing side.

13. The stamp of claim 8, wherein the first conductive layer and the second conductive layer form a single layer structure conformally disposed on the pressing side of the body.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

(2) FIG. 1A to FIG. 1I are cross-sectional schematics of the manufacturing process of a circuit board shown according to an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

(3) FIG. 1A to FIG. 1I are cross-sectional schematics of the manufacturing process of a circuit board shown according to an embodiment of the invention. First, referring to FIG. 1A, a circuit pattern 102 is formed on a dielectric substrate 100. The forming method of the circuit pattern 102 includes, for instance, forming a conductive material layer on the dielectric substrate 100 via a lamination method and patterning the conductive material layer. The material of the dielectric substrate 100 is, for instance, epoxy resin, glass fiber cloth, or ceramic. The conductive material layer is, for instance, a copper layer. Next, a dielectric layer 104 is formed on the dielectric substrate 100. The dielectric layer 104 covers the circuit pattern 102 on the dielectric substrate 100. The material of the dielectric layer 104 is, for instance, epoxy resin. The dielectric layer 104 is, for instance, formed on the dielectric substrate 100 via a lamination method. Next, a via exposing a portion of the circuit pattern 102 is formed in the dielectric layer 104. The forming method of the via includes, for instance, performing laser drilling or mechanical drilling. Then, a conductive layer 106 is formed in the via. The material of the conductive layer 106 is, for instance, copper, and the forming method thereof includes, for instance, performing an electroplating process. Alternatively, the material of the conductive layer 106 is, for instance, conductive gel, and the forming method thereof includes, for instance, performing a stuffing process. The conductive layer 106 is used as a conductive via for connecting the circuit pattern 102. Then, a conductive seed layer 108 is formed on the dielectric layer 104 and the conductive layer 106. The material of the conductive seed layer 108 is, for instance, copper.

(4) Then, referring to FIG. 1B, a thermal-sensitive adhesive layer 110 is formed on the conductive seed layer 108. When the thermal-sensitive adhesive layer 110 is heated to high temperature (such as greater than 100 C.) by UV irradiation, laser irradiation, or infrared heating, the adhesion of the thermal-sensitive adhesive layer 110 is significantly reduced (even lost) such that the thermal-sensitive adhesive layer 110 is readily removed. Then, a photoresist material layer 112 is formed on the thermal-sensitive adhesive layer 110. The forming method of the photoresist material layer 112 is, for instance, a spin coating method. Alternatively, the photoresist material layer 112 can be formed on the thermal-sensitive adhesive layer 110 via a lamination method. In the present embodiment, the photoresist material layer 112 is, for instance, a negative photoresist material layer, and a portion thereof irradiated by UV light in a subsequent exposure process is solidified.

(5) Moreover, a stamp 114 is provided to perform imprinting on the photoresist material layer 112. The stamp 114 has a pattern corresponding to the circuit pattern to be formed on the dielectric layer 104. When the stamp 114 is pressed on the photoresist material layer 112, mechanical deformation can occur to the photoresist material layer 112, such that a pattern is precisely transferred to the photoresist material layer 112. Moreover, the stamp 114 includes a body 114a and a conductive layer 114b and a conductive layer 114c disposed on the body 114a. Specifically, the body 114a has a circuit-forming intaglio pattern on a pressing side, the conductive layer 114b is disposed on the surface of the pressing side of the body 114a facing the circuit pattern 102, the conductive layer 114c is disposed on the surface of the other portions of the body 114a, and the resistance of the conductive layer 114b is greater than the resistance of the conductive layer 114c. In the present embodiment, the material of the conductive layers 114b and 114c is not limited as long as the resistance of the conductive layer 114b is greater than the resistance of the conductive layer 114c. Moreover, the conductive layers 114b and 114c are connected to an external power supply 116. When the external power supply 116 is turned on, current can pass through the conductive layers 114b and 114c and heating can be performed on the conductive layers 114b and 114c via the inherent resistance of the conductive layers 114b and 114c.

(6) Next, referring to FIG. 1C, imprinting is performed on the photoresist material layer 112 using the stamp 114. When the stamp 114 is pressed on the photoresist material layer 112, the photoresist material layer 112 is deformed, such that the pattern of the stamp 114 can be precisely transferred to the photoresist material layer 112. When the imprinting is performed, a very thin and unavoidable photoresist residue 112a is generally formed between the stamp 114 and the thermal-sensitive adhesive layer 110. In particular, for the large contact area between the stamp 114 and the thermal-sensitive adhesive layer 110, the very thin and unavoidable photoresist residue 112a is largely concentrated in the center of the contact region, and the thickness distribution thereof shows a roughly Gaussian distribution from the periphery to the center. Since the stamp 114 is largely formed by a polymer material, as shown in FIG. 1C, the region of the stamp 114 in contact with the photoresist residue 112a is slightly deformed with the photoresist residue 112a.

(7) Next, as shown in FIG. 1D, the external power supply 116 is turned on to apply current to the stamp 114. After the external power supply 116 is turned on, current passes through the conductive layers 114b and 114c. At this point, current thermal effect is induced by the inherent resistance characteristics of the conductive layers 114b and 114c, such that the temperature of the conductive layers 114b and 114c is increased. Since the resistance of the conductive layer 114b is greater than the resistance of the conductive layer 114c, the temperature of the conductive layer 114b is higher than the temperature of the conductive layer 114c. As a result, heating can be indirectly performed on the thermal-sensitive adhesive layer 110 below the conductive layer 114b via the conductive layer 114b to reduce the adhesion of the thermal-sensitive adhesive layer 110 below the conductive layer 114b. In the present embodiment, the temperature of the conductive layer 114b is increased to greater than 100 C. via the regulation of current, so as to significantly reduce the adhesion of the thermal-sensitive adhesive layer 110 below the conductive layer 114b, and the adhesion of the thermal-sensitive adhesive layer 110 below the conductive layer 114b may even be lost, such that adhesion of the thermal-sensitive adhesive layer 110 below the conductive layer 114b to the conductive seed layer 108 is lost. Regarding the thermal-sensitive adhesive layer 110 not below the conductive layer 114b, since the temperature is not increased to the point at which significant adhesion is lost, adhesion to the conductive seed layer 108 is retained. At this point, the thermal-sensitive adhesive layer 110 on the conductive seed layer 108 is divided into a first portion heated by the conductive layer 114b and for which the adhesion is significantly reduced or lost and a second portion not heated by the conductive layer 114b and retaining the original adhesion.

(8) Next, referring to FIG. 1E, the external power supply 116 is turned off. Next, an exposure process is performed on the imprinted photoresist material layer 112 to solidify the photoresist material layer 112. In the present embodiment, comprehensive irradiation is performed on the imprinted photoresist material layer 112 using a UV light 117. When the UV light 117 passes through the body 114a and the conductive layers 114b and 114c and is irradiated on the photoresist material layer 112, a cross-linking reaction can occur in the photoresist material layer 112 such that the photoresist material layer 112 is solidified. Since the UV light 117 needs to pass through the body 114a and the conductive layers 114b and 114c, the materials of the body 114a and the conductive layers 114b and 114c need to be UV penetrable.

(9) Next, referring to FIG. 1F, the stamp 114 is removed. At this point, the first portion for which the adhesion is significantly reduced or lost and the second portion retaining the original adhesion of the thermal-sensitive adhesive layer 110 are retained on the conductive seed layer 108.

(10) Next, referring to FIG. 1G, since the adhesion of the first portion of the thermal-sensitive adhesive layer 110 is significantly reduced or lost, the first portion can be directly removed, and the photoresist residue 112a located on the first portion when the first portion is removed is also removed. At this point, a patterned photoresist layer 112b and the second portion of the thermal-sensitive adhesive layer 110 not removed (i.e., a patterned thermal-sensitive adhesive layer 110a) are formed on the conductive seed layer 110, and the patterned photoresist layer 112b is firmly formed on the conductive seed layer 108 via the patterned thermal-sensitive adhesive layer 110a below the patterned photoresist layer 112b. As a result, even if the patterned photoresist layer 112b has high aspect ratio, the patterned photoresist layer 112b can still be located on the conductive seed layer 108 in a stable manner without falling or collapsing. In other words, in the present embodiment, the patterned photoresist layer 112b can be formed on the conductive seed layer 108 in a stable manner via the patterned thermal-sensitive adhesive layer 110a, and therefore the selection of the photoresist material can be more flexible and the adhesion of the photoresist material is less influential. Moreover, the region exposed by the patterned photoresist layer 112b is the region in which a circuit pattern is to be subsequently formed.

(11) Then, referring to FIG. 1H, a patterned metal layer 118 is formed on the region exposed by the patterned photoresist layer 112b. The material of the patterned metal layer 118 is, for instance, copper. The forming method of the patterned metal layer 118 includes, for instance, performing an electroplating process using the conductive seed layer 108.

(12) Next, referring to FIG. 1I, the patterned photoresist layer 102b is removed. The method of removing the patterned photoresist layer 112b includes, for instance, performing a wet stripping process. Next, the patterned thermal-sensitive adhesive layer 110a below the patterned photoresist layer 112b is removed. The method of removing the patterned thermal-sensitive adhesive layer 110a includes, for instance, performing UV irradiation, laser irradiation, or infrared heating on the patterned thermal-sensitive adhesive layer 110a to heat the patterned thermal-sensitive adhesive layer 110a to high temperature (such as greater than 100 C.) such that the adhesion thereof is significantly reduced or lost, and then the patterned thermal-sensitive adhesive layer 110a is removed. Alternatively, the patterned thermal-sensitive adhesive layer 110a can also be removed by applying a mechanical force (such as artificial stripping). Next, the conductive seed layer 108 below the patterned thermal-sensitive adhesive layer 110a is removed. The method of removing the conductive seed layer 108 includes, for instance, performing a flash etch process. In this way, the manufacture of the circuit board of the present embodiment is complete. In a circuit board of the present embodiment, the patterned metal layer 118 on the dielectric layer 104 and the conductive seed layer 108 below the patterned metal layer 118 form a circuit pattern 120, and the circuit pattern 120 is connected to the circuit pattern 102 via the conductive via 106.

(13) It should be mentioned that, in the present embodiment, the photoresist material layer 112 is a negative photoresist material layer, but the invention is not limited thereto. In another embodiment, the photoresist material layer 112 can also be a positive photoresist material layer. When the photoresist material layer 112 is a positive resist material layer, after the photoresist material layer 112 is imprinted, an exposure process does not need to be performed (i.e., the step of FIG. 1E is omitted), and the stamp 114 can be directly removed (as shown in FIG. 1F).

(14) Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.