Power converter and methods of controlling a power converter

Abstract

The present invention relates to a new method of power converter regulation, in particular regulation of very high frequency (VHF) power converters operating at frequencies in the MHz range, wherein accurate output regulation utilizes inherent delays in the regulation loop, whereby, contrary to hysteresis on/off control, the new method does not require immediate responses to comparisons of a sense voltage to two reference voltages; rather, according to the new method, only one reference voltage is used, and delays in the feedback loop are allowed to cause some variation of an output of the power converter.

Claims

1. A power converter comprising: a control circuit configured to compare a sense voltage with a single reference voltage, and having a control output that is coupled to the power converter to control the power converter to turn-on and turn-off by enabling and disabling energy transfer from an input of the power converter to an output of the power converter in such a way that after each previous turn-off of the power converter, the power converter is turned-on only when an absolute value of the sense voltage is less than or equal to an absolute value of the single reference voltage, and a first time period has elapsed since the previous turn-off of the power converter; and after each previous turn-on of the power converter, the power converter is turned-off only when the absolute value of the sense voltage is larger than or equal to the absolute value of the single reference voltage, and a second time period has elapsed since the previous turn-on of the power converter.

2. The power converter according to claim 1, wherein the control circuit comprises a comparator that is configured to compare the sense voltage with the single reference voltage, and having a comparator output that is the control output.

3. The power converter according to claim 1, wherein the power converter is configured for operation at a frequency above 1 MHz.

4. The power converter according to claim 1, further comprising a delay circuit configured to provide at least part of at least one of the first and second time periods.

5. The power converter according to claim 1, wherein an output voltage of the power converter is coupled to a signal conditioning circuit configured to output the sense voltage.

6. The power converter according to claim 1, further comprising a switch, wherein the control output is configured to control the power converter to turn-on and turn-off by turning on and turning off the switch of the power converter.

7. The power converter according to claim 1, wherein the power converter is a SEPIC converter.

8. The power converter according to claim 7, wherein the SEPIC converter is a self-oscillating SEPIC converter.

9. The power converter according to claim 7, wherein the power converter is an interleaved SEPIC converter.

10. The power converter according to claim 1, wherein the control circuit is configured to compensate a dependence of the sense voltage on an output current.

11. The power converter according to claim 10, wherein the control circuit is configured to vary the single reference voltage in dependence on the output current, whereby the dependence of the sense voltage on the output current is compensated.

12. The power converter according to claim 10, wherein the control circuit is configured to vary at least one of the first and second time periods in dependence of the output current, whereby the dependence of the sense voltage on the output current is compensated.

13. The power converter according to claim 1, wherein the sense voltage is the only sense voltage received by the control circuit.

14. The power converter according to claim 1, wherein the single reference voltage is the only reference voltage received by the control circuit.

15. A method of controlling a power converter, comprising: after each previous turn-off of the power converter, turning the power converter on by enabling energy transfer from an input of the power converter to an output of a power converter only when an absolute value of a sense voltage is less than or equal to an absolute value of a single reference voltage, and a first time period has elapsed since the previous turn-off of the power converter; and after each previous turn-on of the power converter, turning the power converter off by disabling energy transfer from an input of the power converter to an output of the power converter only when the absolute value of the sense voltage is larger than or equal to the absolute value of the single reference voltage, and a second time period has elapsed since the previous turn-on of the power converter.

16. The method according to claim 15, further comprising comparing the sense voltage with the single reference voltage by a control circuit, wherein the sense voltage is the only sense voltage received by the control circuit.

17. The method according to claim 15, further comprising comparing the sense voltage with the single reference voltage by a control circuit, wherein the single reference voltage is the only reference voltage received by the control circuit.

18. The method according to claim 15, wherein the power converter comprises a switch, wherein turning the power converter on comprises turning on the switch of the power converter, and wherein turning the power converter off comprises turning off the switch of the power converter.

19. The method according to claim 15, wherein the power converter comprises a switch, wherein turning the power converter on comprises turning off the switch of the power converter, and wherein turning the power converter off comprises turning on the switch of the power converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Below, the new method and the new power converter are explained in more detail with reference to the drawings in which various resonant examples of the new power converter are shown. In the drawings:

(2) FIG. 1 shows a schematic diagram of a resonant power converter with the new control circuit,

(3) FIG. 2 shows a schematic circuit diagram of an exemplary new resonant power converter,

(4) FIG. 3 shows a schematic circuit diagram of an exemplary new resonant power converter,

(5) FIG. 4 shows a schematic circuit diagram of an exemplary new resonant power converter,

(6) FIG. 5 shows a schematic circuit diagram of an exemplary new resonant power converter,

(7) FIG. 6 shows exemplary signal conditioning circuits,

(8) FIG. 7 shows exemplary switch drivers,

(9) FIG. 8 shows a schematic circuit diagram of an exemplary new resonant power converter with a stop circuit,

(10) FIG. 9 shows a switch driver with oscillator turn-off,

(11) FIG. 10 shows a power circuit diagram of a VHF interleaved self-oscillating resonant SEPIC converter,

(12) FIG. 11 is a plot of simulated waveforms of the power circuit shown in FIG. 10,

(13) FIG. 12 shows a schematic circuit diagram of a model of a new resonant power converter used for calculation of component values,

(14) FIG. 13 shows a circuit diagram of a control circuit used to control the power circuit shown in FIG. 10,

(15) FIG. 14 is a plot of characteristic waveforms of the model shown in FIG. 12,

(16) FIG. 15 is a plot of experimental waveforms of the control circuit shown in FIG. 13,

(17) FIG. 16 is a plot of experimental waveforms of the power circuit shown in FIG. 10,

(18) FIG. 17(a) shows a plot of converter efficiency as a function of output power and (b) shows a plot of output voltage offset as a function of the load,

(19) FIG. 18 is a flowchart of the new method,

(20) FIG. 19 shows (a) a schematic circuit diagram of a model of the new resonant power converter together with (b) a conventional hysteretic control circuit and (c) a phase-shift burst mode control circuit,

(21) FIG. 20 shows a plot of simulated waveforms of the model converter current and voltages controlled by the hysteretic control circuit,

(22) FIG. 21 shows a plot of simulated waveforms of the model converter current and voltages controlled by the phase-shift burst mode control circuit, and

(23) FIG. 22 shows schematic circuit diagrams of control circuits with varying sense voltage.

DETAILED DESCRIPTION OF EMBODIMENTS

(24) The accompanying drawings are schematic and simplified for clarity, and they merely show details which are essential to the understanding of the new resonant power converter, while other details have been left out. The new resonant power converter according to the appended claims may be embodied in different forms not shown in the accompanying drawings and should not be construed as limited to the examples set forth herein.

(25) Like reference numerals refer to like elements throughout. Like elements may, thus, not be described in detail with respect to the description of each figure.

(26) FIG. 1 shows a schematic block diagram of a resonant power converter 10 controlled in accordance with the new method. The illustrated resonant power converter 10 comprises a VHF power circuit 12, a control circuit 14 with a control output 16, and a signal conditioning circuit 18 providing a sense voltage 20 based on and corresponding to the output voltage 22.

(27) The control circuit 14 is coupled to compare the sense voltage 20 with a reference voltage 24.

(28) Alternatively, the sense voltage 20 may be provided by a current sensor, such as a resistor, a hall element, etc., coupled so that the sense voltage corresponds to an output current of the resonant power converter 10.

(29) The control circuit 14 has a control output 16 that is coupled to control turn-on and turn-off of the VHF power circuit 12 of the resonant power converter.

(30) In the illustrated examples, the output voltage and the sense voltage have positive values, so that the absolute value of the sense voltage or the output voltage is equal to the value itself.

(31) The VHF power circuit 12 of the resonant power converter 10 is turned-on when the sense voltage 20 is less than or equal to the reference voltage 24 and a first time period has elapsed since a previous turn-off of the VHF power circuit 12. The VHF power circuit 12 of the resonant power converter 10 is turned-off when the sense voltage 20 is larger than or equal to the reference voltage 24 and a second time period has elapsed since a previous turn-on of the VHF power circuit 12.

(32) The VHF power circuit 12 may be of any known resonant power converter topology with a frequency of operation in the MHz range, such as at or above 20 MHz, such as at or above 30 MHz, such as in the 30 MHz-300 MHz range, such as converters comprising: a class E inverter and a class E rectifier, a class DE inverter and a class DE rectifier, a class DE inverter and a class E rectifier, etc.; or, class EF2 (or class ) converters, resonant SEPIC converters, etc.

(33) The resonant power converter may be driven by an oscillator, or the converter may be self-oscillating. Further, the resonant power converter may be interleaved.

(34) Inherent signal propagation delays of the components of the control circuit 14 forms parts of the first and second time periods, and the inherent signal propagation delays may form the entire first and second time periods. Additionally, one or more delay circuits may provide part of the first time period and/or part of the second time period, namely part of the third time period and/or part of the fourth time period.

(35) The control circuit 14 may comprise a comparator that is coupled to compare the sense voltage 20 with the reference voltage 24, and having a comparator output that is the control output 16.

(36) The delays with which the comparator changes state of its output from high to low and vice versa, in response to changed input(s), constitute part of the respective first and second time periods, namely part of the third time period and/or part of the fourth time period.

(37) The signal conditioning circuit 18 may be a low-pass filter configured to output the sense voltage.

(38) The control output 16 may be coupled to control turn-off of at least one power switch (not shown) of the resonant power converter 10 thereby turning the resonant power converter off.

(39) This is illustrated in the class E inverter based resonant power converters shown in FIGS. 2 and 3. The only difference between the resonant power converter of FIG. 2 and the resonant power converter of FIG. 3 is that inductor L.sub.3 of FIG. 2 has been substituted by rectifier D.sub.1 in FIG. 3.

(40) Alternatively, or additionally, the control output 16 may be coupled to control other parts of the resonant power converter circuit than the power switches, e.g. by enabling and disabling energy transfer from the input to the output of the resonant power converter 10, e.g. by turning the resonant power converter on and off by changing the impedance or the loop-gain of the resonant part of the power circuit, whereby the resonant power converter is turned-off by changing the impedance to a first value at which the power circuit does not oscillate, and whereby the resonant power converter is turned-on by changing the impedance to a second value at which the power circuit oscillates.

(41) This is illustrated in FIGS. 4 and 5 showing a class E inverter based resonant power converter similar to the class E inverter based resonant power converters shown in FIG. 3 except for the fact that the control output 16 turns S.sub.2 on and off.

(42) In FIG. 4, the resonant part of the resonant power converter 10 does not oscillate when switch S.sub.2 is turned-on, and the resonant part of the resonant power converter 10 oscillates and operates like the resonant power converter 10 of FIG. 3 when switch S.sub.2 is turned-off.

(43) In FIG. 5, the functions of rectifier D2 and switch S2 of FIG. 4 are combined in switch S2 functioning as a synchronous rectifier in FIG. 5 when the second self-oscillating gate driver is enabled so that the resonant power converter is turned on.

(44) FIG. 6 shows circuit diagrams of two examples of low-pass filters that may constitute the signal conditioner 18.

(45) The signal conditioners shown in FIGS. 6(a) and (b) may be substituted with any suitable signal conditioner chosen from other signal conditioner designs available to the person skilled in the art.

(46) Examples of self-oscillating gate drivers are shown in FIG. 7.

(47) In FIG. 7(a), a low enable signal keeps the gate of the power switch at zero voltage, whereby oscillation of the power circuit is inhibited, while a high enable signal allows propagation of the VHF oscillator signal driving the gate of the power switch causing the power circuit to oscillate.

(48) In FIG. 7(b), a low enable signal switches switch transistor S.sub.aux off and keeps the gate of the power switch at a constant voltage, whereby oscillation of the power circuit is inhibited, while a high enable signal allows propagation of the VHF oscillator signal driving the switch transistor S.sub.aux on and off thereby driving the power switch on and off causing the power circuit to oscillate.

(49) The gate drivers shown in FIGS. 7(a) and (b) may be substituted with any suitable gate driver chosen from other gate driver designs available to the person skilled in the art.

(50) FIG. 8 shows a schematic circuit diagram of an exemplary new resonant power converter with a stop circuit,

(51) FIG. 9 shows a switch driver with oscillator turn-off,

(52) FIG. 10 is a circuit diagram of a power circuit 12 of an interleaved self-oscillating resonant SEPIC converter, wherein two power circuits 12a, 12b drive each other via capacitive coupling C.sub.X1 and C.sub.X2 between the switches S.sub.1 and S.sub.2 and operate in interleaved mode.

(53) The power circuits are substantially identical, i.e.:
L.sub.I1=L.sub.I2=L.sub.I
C.sub.I1=C.sub.I2=C.sub.I
C.sub.X1=C.sub.X2=C.sub.X
C.sub.S1=C.sub.S2=C.sub.S

(54) The values of the most important parasitic components of the semiconductor devices, namely diode junction capacitors and parasitic capacitors of the semiconductor switches, are included in determination of operating frequency of the resonant power converter. The oscillation frequency f.sub.S is determined mainly by the inductance L.sub.I and the total capacitance seen from the drain when the rectifiers are shorted, C.sub.DS,tot

(55) $f_s=\frac{1}{2\sqrt{L_I{C}_{\mathrm{DS},\mathrm{tot}}}}$$\mathrm{where}$$C_{\mathrm{DS},\mathrm{tot}}=C_I+C_{\mathrm{OSS}}+C_S+C_X.Math..Math.C_{\mathrm{ISS}}$$C_{\mathrm{OSS}}=C_{\mathrm{DS}}+C_{\mathrm{DG}}$$C_{\mathrm{ISS}}=C_{\mathrm{GS}}+C_{\mathrm{DG}}$

(56) Oscillations start once the gate voltages of the MOSFET switches S.sub.1 and S.sub.2 become slightly higher than the MOSFET threshold voltage. Simulated waveforms of the resonant power circuit of FIG. 10 are shown in FIG. 11. Ideally, respective waveforms of the two interleaved power converters are identical and shifted 180 with relation to each other.

(57) If VHF ripple is neglected, the converter output can be modeled as a current source with the current value of I.sub.0. When an on/off modulation is applied on the converter, the current supplied by the converter i.sub.conv to C.sub.out and the load may be approximately modeled as a current square wave:

(58) $i_{\mathrm{conv}}=\{\begin{array}{cc}{I}_0,& \mathrm{when}\mathrm{the}\mathrm{converter}\mathrm{is}\mathrm{ON}\\ 0,& \mathrm{when}\mathrm{the}\mathrm{converter}\mathrm{is}\mathrm{OFF}\end{array}$

(59) Output current I.sub.out is equal to average value of i.sub.conv over one modulation cycle. The resulting current going into C.sub.out is i.sub.convI.sub.out, which has no DC component in steady state. If parasitics of C.sub.out are negligible, the resulting V.sub.out voltage waveform is a triangular wave. Assuming that turn-on and turn-off delays are independent of the output voltage rate of change, the output voltage ripple is

(60) $V_{\mathrm{out}}=\frac{I_{\mathrm{out}}}{C_{\mathrm{out}}}{t}_{D,\mathrm{on}}+\frac{I_0-I_{\mathrm{out}}}{C_{\mathrm{out}}}{t}_{D,\mathrm{off}}$
where t.sub.D,on is the fourth time period and t.sub.D,off is the third time period, i.e. t.sub.D,on and t.sub.D,off are the control loop turn-on and turn-off delays, respectively, from the sense voltage crossing the reference voltage and to turn-on or turn-off, respectively, of the power converter. If the control circuit's delays are constant, the equation shows that V.sub.out is a linear function of I.sub.out, and the longer delay defines V.sub.out,max. In the special case of t.sub.D,on and t.sub.D,off being equal, V.sub.out is independent of I.sub.out. At any given load, the offset of V.sub.out: V.sub.out,off, and f.sub.M are determined from the values of C.sub.out and the delays t.sub.D,on and t.sub.D,off by:

(61) $V_{\mathrm{out},\mathrm{off}}=\frac{V_{\mathrm{out}}}{2}\frac{t_{D,\mathrm{on}}-t_{D,\mathrm{off}}}{t_{D,\mathrm{off}}+t_{D,\mathrm{om}}}\mathrm{and}$$f_M=\frac{I_0}{C_{\mathrm{out}}{V}_{\mathrm{out}}}\frac{I_{\mathrm{out}}}{I_0}\left(1-\frac{I_{\mathrm{out}}}{I_0}\right)$

(62) Modulation frequency is highest at 50% duty cycle, i.e. the power converter is turned on half the time:

(63) $f_{M,\max }=\frac{1}{2\left(t_{D,\mathrm{on}}+t_{D,\mathrm{off}}\right)}$

(64) I.sub.0 is not known from values of circuit components. An approximate value of I.sub.0 can be determined from Spice simulations. Once I.sub.0 is obtained, the output filter and the feedback circuit need to be designed to provide a desired modulation frequency f.sub.M at a specified load.

(65) FIG. 12 shows a block diagram of such a low frequency model of a resonant power. The VHF power circuit 12 is modelled as an on-off controllable DC current source.

(66) The conditioning circuit 18 at the input of the control circuit 14, see FIG. 13, has a simple transfer function:

(67) $H\left(s\right)=\frac{A_{\mathrm{FB}}}{1+s{}_{\mathrm{FB}}}$$\mathrm{Where}$$A_{\mathrm{FB}}=\frac{R_{\mathrm{FB}2}}{R_{\mathrm{FB}1}+R_{\mathrm{FB}2}}$${}_{\mathrm{FB}}=\frac{R_{\mathrm{FB}1}{R}_{\mathrm{FB}2}}{R_{\mathrm{FB}1}+R_{\mathrm{FB}2}}{C}_{\mathrm{FB}}$

(68) The comparator 26 of the control circuit 14 model is ideal; the propagation delay of the real comparator is added into the delay block. The delay block is represented by two different time delays, since the shutdown of the power circuit is significantly faster than the start-up sequence. This is because shutdown is performed by the auxiliary switches S.sub.aux1 and S.sub.aux2, while during start-up C.sub.ISS is passively charged from the bias voltage V.sub.B through the biasing resistors.

(69) FIG. 13 shows the control circuit 14. The sense voltage 20 is low-pass filtered in H(s), a voltage divider/low pass filter 18 formed by R.sub.FB1, R.sub.FB2, and C.sub.FB, and input to the comparator 26. The comparator output 16 turns the switches S.sub.aux1 and S.sub.aux2 on and off in response to the voltage difference at the comparator inputs. When S.sub.aux1 and S.sub.aux2 are on, v.sub.GS1 and v.sub.GS2 are zero and the power circuit oscillations are inhibited. Once S.sub.aux1 and S.sub.aux2 are off, C.sub.ISS1 and C.sub.ISS2 are charged through R.sub.B1 and R.sub.B2, whereby v.sub.GS1 and v.sub.GS2 start to increase from 0 to V.sub.B. After the first time period, when v.sub.GS1 and V.sub.GS2 exceed the power MOSFET threshold voltage V.sub.th, switches S.sub.1 and S.sub.2 enter saturation and initiate oscillations in the power circuit. H(s) has two primary purposes: to filter high frequency noise and adjust the feedback voltage level. It also contributes to propagation delay in the feedback loop.

(70) In FIG. 14, characteristic voltage and current levels from a numerical example of the model are shown, where C.sub.out=3.3 F I.sub.0=1.04 A, I.sub.out=0.52 A R.sub.FB2=2 k, R.sub.FB1=8.2 k C.sub.FB=22 pF t.sub.d,on=700 ns+170 ns=870 ns t.sub.d,off=170 ns

(71) The parameters are chosen to approximate the experimental setup described below. v.sub.gate(t) represents the gate voltages of S.sub.1 and S.sub.2 with removed VHF component. V.sub.out(t) passes through the single pole transfer function H(s) and results in a distorted triangular waveform v.sub.FB(t). Average value of v.sub.FB(t) is slightly lower than the reference V.sub.ref voltage, which is due to t.sub.d,on>t.sub.d,off. This is also the cause of the duty cycle of the comparator output v.sub.cmp(t) to be lower than 50%. Since the referent output voltage is 10 V, a small offset can be observed in V.sub.out(t). This offset is dependent on the duty cycle of the power circuit, the time difference t.sub.d,ont.sub.d,off, and C.sub.out. t.sub.d,on depends on the voltage difference between V.sub.B and V.sub.th. Obtained modulation frequency is very close to 300 kHz.

(72) In order to verify the analysis explained above, a 10.5 W prototype converter with regulation of the output voltage was produced and the measurements for the prototype converter is disclosed below.

(73) Plots of drain, gate, and rectifier voltages in the power circuit are shown in FIG. 15. The drain and rectifier voltages were measured with capacitance of 2.2 pF in series with an oscilloscope probe, in order to reduce influence of the probe to the power circuit. This introduces attenuation of A=0.19 in the measurement and removes the DC component of the measured voltages. Component values of the power circuit are listed in Table I. Switching frequency of the power circuit is f.sub.S=49 MHz. Open loop output voltage and output voltage and current are V.sub.out=10.2 V and I.sub.0=1.04 A, respectively.

(74) When the duty cycle of 50% is obtained, I.sub.out=0.5 I.sub.0=0.52 A. Plots of the waveforms of the relevant voltages in the converter for this case are shown in FIG. 9. Modulation frequency f.sub.M is at its maximum value of 300 KHz at 50% duty cycle, and drops as the duty cycle moves away from 50%. In addition, under these conditions output voltage ripple V.sub.out,.sub.pp is at its maximum as well.

(75) The comparator used in the circuit is AD8468 from Analog Devices. The component datasheet specifies 40 ns propagation delay. For comparison, a high speed TLV3501 comparator has a 4.5 ns propagation delay, which is a reduction by a factor of 9. This is by no means a limit since there are other significant contributors as well (conditioning and power circuit on-off circuit). This delay may be increased even further at a cost of a lower modulation frequency f.sub.M and higher output voltage ripple for a given C.sub.out.

(76) FIGS. 15 and 16 illustrate relationships between the signals in time domain, V.sub.cmp+, v.sub.cmp, v.sub.GS, v.sub.DS, and v.sub.out (upper waveforms) with respect to the comparator output (lower waveforms). High output voltage ripple is caused by a small output filtering capacitance (C.sub.out=3.3 pF).

(77) Efficiency of the converter is shown in FIG. 17(a) as a function of output power. Since f.sub.M is allowed to drop significantly under light load conditions, efficiency is maintained high over wide load range (>75% above 20% load) with peak efficiency above 81%.

(78) Since the control is based on phase shift, a small DC error is introduced in the value of v.sub.out, which varies with the load. If the output voltage ripple is assumed triangular (which is reasonable since i.sub.conv is a current square wave), the peak values of v.sub.out are determined as:

(79) $V_{\mathrm{out}+}=V_{\mathrm{out},\mathrm{ref}}+\frac{I_0-I_{\mathrm{out}}}{C_{\mathrm{out}}}{t}_{+}$$V_{\mathrm{out}-}=V_{\mathrm{out},\mathrm{ref}}+\frac{-I_{\mathrm{out}}}{C_{\mathrm{out}}}{t}_{-}$

(80) So that the offset of V.sub.out is determined by

(81) $V_{\mathrm{out},\mathrm{offset}}=V_{\mathrm{out},\mathrm{ref}}-\frac{V_{\mathrm{out}+}+V_{\mathrm{out}-}}{C_{\mathrm{out}}}{t}_{-}$

(82) V.sub.out,ref is a target value for the output voltage set by V.sub.ref and R.sub.FB1R.sub.FB2 voltage divider. t.sub.+ and t.sub. are the time delays from a point when v.sub.out crosses v.sub.out,ref to a point where v.sub.out reaches its maximum and minimum value, respectively. Depending on the variables in these equations, v.sub.out, offset may be either positive or negative, and decreases with I.sub.out. Measured dependence of v.sub.out is shown in the lower plot of FIG. 17. Both the offset and the output ripple are reduced with increase in C.sub.out, while the switching frequency will be reduced.

(83) A comparison between the model disclosed above and experimental results show close, but not perfect matching. The reasons for this are subjects of further investigation; it is assumed that imperfections in the active components and tolerances of the passive components are the main contributors. Still, the model gives significant insight into the system operation, and can be used as a good estimate during the converter design.

(84) Compared to hysteresis based burst mode control, the new method of controlling the resonant power converter allows use of a significantly slower and less expensive components in the control circuit, which is of importance for cost sensitive applications such as LED lighting and PoL converters. The illustrated power circuits and control circuits were implemented using only low cost commercially available components, with peak efficiency above 81% and high efficiency over wide load range.

(85) FIG. 18 is a flowchart 100 of the new method of controlling a resonant power converter. The method starts with method step 110 wherein the resonant power converter is turned on.

(86) When the resonant power converter is turned on, the output voltage and/or output current increases. A sense voltage is provided in the resonant power converter that corresponds to the output voltage or output current, and a reference voltage is provided in the resonant power converter that corresponds to a desired resulting output voltage or output current of the resonant power converter.

(87) According to method step 120, the output voltage and/or output current continue to increase until the corresponding sense voltage V.sub.sense is equal to or larger than the reference voltage V.sub.ref, and

(88) according to method step 130, the output voltage and/or output current continue to increase until also a second time period t.sub.2 has elapsed since a previous turn-on of the resonant power converter.

(89) Thus, when the sense voltage V.sub.sense is equal to or larger than the reference voltage V.sub.ref, and a second time period t.sub.2 has elapsed since a previous turn-on of the resonant power converter, the resonant power converter is turned-off in method step 140.

(90) When the resonant power converter is turned on, the output voltage and/or output current decreases.

(91) According to method step 150, the output voltage and/or output current continue to decrease until the corresponding sense voltage V.sub.sense is equal to or less than the reference voltage V.sub.ref, and

(92) according to method step 160, the output voltage and/or output current continue to decrease until also a first time period t.sub.1 has elapsed since a previous turn-off of the resonant power converter.

(93) Thus, when the sense voltage V.sub.sense is equal to or less than the reference voltage V.sub.ref, and a first time period t.sub.1 has elapsed since a previous turn-off of the resonant power converter, the resonant power converter is turned-off in method step 110.

(94) In the following, properties of the phase-shift burst mode control method for very high frequency (VHF) DC-DC converters are compared with a conventional control method with hysteresis based on comparison of a sense voltage with two threshold values. Again, an on-off controllable current source is used to model the low-frequency behaviour of VHF converters. Large output capacitance is used for output voltage filtering. The model is shown in FIG. 19(a).

(95) FIG. 19(b) shows the model of FIG. 19(a) controlled with a conventional hysteretic control circuit and FIG. 19(c) shows the model of FIG. 19(a) controlled with a phase-shift burst mode control circuit.

(96) For both circuits, the VHF power converter is operating (turned-on) when V.sub.ctrl is high, e.g. 2 Volt, delivering an average current of I.sub.0=2 A. The VHF power converter is turned-off when V.sub.ctrl is low, e.g. 0 Volt. In the present example, capacitor C.sub.out and load R.sub.load are set to 10 F and 10, respectively. Reference voltage V.sub.ref equals 1 V, high impedance signal conditioning network H(s) has ratio of V.sub.sense/V.sub.out=1:N, e.g. 1:10, independent of frequency. The circuit configurations and component values are selected so that the target output V.sub.out is equal to 10 V and at nominal load, the VHF power converter operates at a 50% duty cycle. It is assumed that gate drivers do not introduce any delay in any of the circuits of FIGS. 19(a)-(c) so that V.sub.ctrl=V.sub.cmp.

(97) In the control circuit with hysteresis shown in FIG. 19(b), instantaneous response of the comparator is assumed so that the comparator does not add a delay in the control loop. In the present example, the hysteresis window is V.sub.H=20 mV. The comparator turns the converter on when V.sub.sense<V.sub.ref and turns it off otherwise. Simulated waveforms of the converter voltages of the converter with hysteresis control are shown in FIG. 20.

(98) Modulation frequency f.sub.M, i.e. the frequency at which the converter turns on and off, is given by:

(99) $f_M=\frac{I_0/2}{2V_{\mathrm{out}}{C}_{\mathrm{out}}}=\frac{I_0/2}{2{\mathrm{NV}}_H{C}_{\mathrm{out}}}$

(100) This equation is derived under the assumption that propagation delay t.sub.D of the comparator, the gate driver, and the power stage of the converter is zero, and the equation is a good approximation when t.sub.D 1/f.sub.M. Expensive components, e.g. comparators, gate drivers, etc., have to be used in VHF designs to realize small propagation delays in the feedback loop.

(101) Time difference T from V.sub.sense=V.sub.ref until V.sub.sense=V.sub.ref+V.sub.H in FIG. 20 equals 1/(4 f.sub.M). If V.sub.H->0 and t.sub.D->1/(4 f.sub.M), the waveforms shown in FIG. 20 turn into the waveforms shown in FIG. 21 showing simulated waveforms of the converter voltages of the converter with phase shift burst mode control. The waveforms in FIGS. 20 and 21 are aligned so that V.sub.sense voltages cross the respective V.sub.ref voltages at the same time, e.g. 2 s, 4 s, 6 s, etc. The output voltage ripples are identical in FIGS. 20 and 21, however the signal propagation delay through the feedback loop is 1/(4 f.sub.M), see the time difference between converter currents I.sub.conv,H/PS, comparator output voltages V.sub.cmp,H/PS, etc.

(102) With the component values mentioned above, the modulation frequency is 250 kHz.

(103) In FIG. 21, the power converter is turned-on at 3 s, 7 s, 11 s, and 15 s, and the power converter is turned-off at 1 s, 5 s, 9 s, and 13 s, and the first time period is equal to the second time period that is equal to 2 s and the fourth time period, i.e. the turn-on delay t.sub.D,on, is equal to the third time period, i.e. the turn-off delay t.sub.D,off, that is equal to 1 s.

(104) The converter with phase shift burst mode control provides the same output voltage ripple (i.e. V.sub.out,H=V.sub.out,PS) as the converter with conventional hysteresis control, while using one or more components in the feedback loop with significantly larger respective delays. The resulting delay may be distributed arbitrarily between the power stage, the comparator, and the gate driver(s). This is very important for VHF converters, since numerous start-up and shutdown techniques (self-oscillating gate drivers and converters) with small, but finite delays may be utilized in a VHF converter with phase shift burst mode control.

(105) Turn-on and turn-off delay (t.sub.D,on and t.sub.D,off) do not need to be equal, either. Any one of the components in the feedback loop in any combination may contribute to the values of the turn-on and turn-off delays, with the restraint that:

(106) 0$t_{D,\mathrm{on}}+t_{D,\mathrm{off}}=\frac{1}{2f_M}$

(107) Output voltage of a converter with hysteresis control resides within the range from H(s).sup.1(V.sub.ref,HV.sub.H) to H(s).sup.1(V.sub.ref,H+V.sub.H), resulting in a voltage ripple of V.sub.out,H.

(108) This is different of a converter with phase shift burst mode control as illustrate in FIG. 19(c) in which the output voltage V.sub.0 is load dependent. The output voltage V.sub.0 decreases with increased load. If output voltage ripple at I.sub.out=1A is V.sub.out,PS and under assumptions of constant delay in the comparator (and otherwise ideal components), average value of V.sub.out,PS ranges from V.sub.out,PS/2 at I.sub.out=0 to V.sub.out,PS at I.sub.out=I.sub.0 linearly with I.sub.out.

(109) The variation of the output voltage V.sub.o as a function of output current may be decreased in various ways. One way is to allow the reference voltage to change as a function of the output voltage V.sub.o to compensate for the change in the output voltage V.sub.o.

(110) FIG. 22(a) shows a control circuit in which the sense voltage 20 is compared to a reference voltage 28 that is adjusted as a function of the mean output voltage V.sub.o. H.sub.1(s) is an ordinary low-pass filter. In the illustrated circuit V.sub.ref1=V.sub.ref(V.sub.ref,meanV.sub.ref), where V.sub.ref,mean is the output of the low-pass filter H.sub.1(s). Thus, V.sub.ref1=V.sub.ref when V.sub.ref,mean=V.sub.ref and V.sub.ref1 decreases when the mean output voltage V.sub.o increases and vice versa whereby the variation of the mean output voltage V.sub.o as a function of output current is counteracted.

(111) FIG. 22(b) shows another control circuit in which the sense voltage 20 is compared to a reference voltage 28 that is adjusted as a function of the mean of the comparator output voltage V.sub.cmp,PS 16. The operation of the illustrated control circuit is based on the fact that the average value of V.sub.cmp,PS varies linearly with the output current I.sub.out.

(112) Reference voltage V.sub.ref1 is formed by superposition of V.sub.ref,PS and low-pass filtered V.sub.cmp,PS. The resistor and capacitor values in the compensation network need to be chosen to provide sufficient attenuation of the ac component of V.sub.cmp,PS.

(113) In the illustrated control circuit, when the converter operates at 50% modulation, the average of V.sub.cmp,PS equals V.sub.ref. If the output current I.sub.out is reduced, the average value of V.sub.cmp,PS is reduced, thus decreasing reference voltage V.sub.ref1 28 thereby counteracting the increase of the output voltage V.sub.o that would otherwise result for the reduced output current I.sub.out. If the output current I.sub.out is increased, the average value of V.sub.cmp,PS is increased, thus increasing reference voltage V.sub.ref1 28 thereby counteracting the decrease of the output voltage V.sub.o that would otherwise result from the increased output current I.sub.out. V.sub.ref1 is calculated with the following formulae:

(114) $V_{\mathrm{ref}1}=V_{\mathrm{ref},\mathrm{PS}}\frac{R_1.Math..Math.\left(R_2+R_3\right)}{R_1}+V_{\mathrm{cmp},\mathrm{PS},\mathrm{high}}\frac{I_{\mathrm{out}}}{I_0}\frac{R_1.Math..Math.\left(R_2+R_3\right)}{R_1}.$